EXHIBIT 1002
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN MODULE
`TWO LLC & CO. KG
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`U.S. Patent No. 5,965,924
`Claims 1-6, 13, 14 and 16
`____________________________________________
`
`
`
`DECLARATION OF RICHARD BLANCHARD, PH.D.
`ON BEHALF OF PETITIONER
`
`
`
`
`
`
`
`
`
`
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`
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`Qualcomm v. DSS
`Qualcomm, Exhibit 1002
`Page 1 of 81
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`

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`U.S. Patent No. 5,954,924
`
`Claims 1-6, 13, 14 and 16
`
`TABLE OF CONTENTS
`
`I.
`
`Relevant Law ................................................................................................. ..7
`
`A.
`
`B.
`
`C.
`
`Claim Construction.............................................................................. ..7
`
`Anticipation ......................................................................................... ..8
`
`Obviousness ......................................................................................... ..8
`
`II.
`
`Summary of Opinions .................................................................................. ..l1
`
`III.
`
`Introduction To the ’924 Patent ................................................................... ..l1
`
`IV. Brief Description of the Technology ........................................................... ..l4
`
`A.
`
`Overview of Transistor Fabrication .................................................. ..l5
`
`1. Basic Structure of Transistors ........................................................... ..l5
`
`2. Formation of Transistor Components ............................................... ..l6
`
`3. Local Interconnects ........................................................................... ..l7
`
`B.
`
`Overview of the ’924 Patent .............................................................. ..l9
`
`1. Problem Disclosed in the ’924 Patent ............................................... ..l9
`
`2. Summary of Invention of the ’924 Patent ......................................... ..21
`
`3. Prosecution History ........................................................................... ..22
`
`V.
`
`Overview of the Primary Prior Art References ........................................... ..25
`
`A.
`
`B.
`
`Overview of Sakamoto (Ex. 1003) .................................................... ..25
`
`Overview of Cederbaum (Ex. 1004) ................................................. ..27
`
`VI.
`
`Claim Construction ...................................................................................... ..29
`
`VII. Level of Ordinary Skill In The Art .............................................................. ..32
`
`VIII. Specific Grounds for Petition ...................................................................... ..33
`
`A.
`
`Ground I: Claims 1-3, 14 and 16 are anticipated by Sakamoto ....... ..33
`
`1. Independent Claim 1 ......................................................................... ..33
`‘
`....................................... ..50
`
`2. Claim 2:
`
`
`
`3. Claim 3: ‘
`
`..................................... ..5l
`
`1
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`Qualcomm,
`Exhibit 1002
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`Page 2 of 81
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`Page 2 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`4. Claim 14: “
`
`5. Claim 16: “The structure according to claim 1, wherein said gate
`comprises polysilicon.” .......................................................................... ..53
`
`B.
`
`Ground 11: Claims 4-6 and 13 are obvious in View of the combination
`
`of Sakamoto and Cederbaum ............................................................ ..53
`
`1. Claim 4: “a semiconductor structure accordin to claim 1, wherein
`
`said electrically conducting plug isi Claim 5: “a
`
`semiconductor structure according to claim 1, wherein said electrically
`conducting plug is a refractory metal plug.” / Claim 6: “a semiconductor
`structure according to claim 1, wherein said electrically conducting plug
`is formed of a material selected from the group consisting of titanium,
`tantalum, molybdenum and tungsten” .................................................... ..54
`2. —A semiconductor structure according to claim 1, wherein
`said conducting plug comprises an outer glue layer and a plug material
`therein ..................................................................................................... ..60
`
`IX. Availability for Cross-Examination ............................................................ ..62
`
`X.
`
`Right to Supplement .................................................................................... ..62
`
`2
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`Exhibit 1002
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`Page 3 of 81
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`Page 3 of 81
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`U.S. Patent No. 5,954,924
`
`Claims 1-6, 13, 14 and 16
`
`I, Richard Blanchard, declare as follows:
`
`1.
`
`2.
`
`My name is Richard Blanchard.
`
`My academic credentials include both a Bachelor of Science Degree
`
`in Electrical Engineering (BSEE) and a Master of Science Degree in Electrical
`
`Engineering (MSEE) from the Massachusetts Institute of Technology in 1968 and
`
`1970, respectively. I subsequently obtained a Ph.D. in Electrical Engineering in
`
`1982 from Stanford University
`
`3.
`
`I have worked or consulted for more than 40 years as an
`
`Electrical Engineer. My primary focus has been on the development,
`
`manufacture, operation, and use of devices and integrated circuits, the
`
`assembly of these devices and integrated circuits, products that use them,
`
`and their failures. My employment history following my graduation from
`
`MIT began at Fairchild Semiconductor in 1970. At Fairchild, my
`
`responsibilities included circuit and device design, process development, and
`
`product engineering in the Linear Integrated Circuits Department.
`
`4.
`
`In 1974, Ijoined Foothill College as an Associate Professor in
`
`the Engineering & Technology Division. My responsibilities included
`
`developing a program in Semiconductor Technology as well as teaching
`
`other courses in the division. While at Foothill College, I co-founded two
`
`3
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`Exhibit 1002
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`Page 4 of 81
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`Page 4 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`companies, Cognition and Supertex, and later joined Supertex as a Vice
`
`President in 1978. At Supertex, I designed and developed discrete DMOS
`
`(double-diffused metal oxide semiconductor) transistors, as well as
`
`integrated circuits that contained DMOS transistors. At Supertex, I also
`
`supervised the in-house assembly area, which included responsibility for the
`
`associated manufacturing processes.
`
`I left Suptertex to join Siliconix in
`
`1982, where I soon became Vice President of Engineering, with the
`
`responsibility for directing all of the company's product design and
`
`development. At Siliconix, I directed and contributed to the development of
`
`both discrete transistors and integrated circuits, including aspects of their
`
`assembly.
`
`5.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President
`
`with the responsibility for organizing an integrated circuit department. At
`
`IXYS, I developed integrated circuits that contained DMOS devices or that
`
`interfaced to DMOS devices. My responsibilities included the design,
`
`assembly, and testing of these integrated circuits.
`
`6.
`
`These duties continued until 1991, when I left IXYS to set up
`
`Blanchard Associates, a consulting firm specializing in semiconductor
`
`technology, including intellectual property. Soon thereafter, I was invited to
`
`4
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`Exhibit 1002
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`Page 5 of 81
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`Page 5 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`join Failure Analysis Associates, which I did in late 1991. At Failure
`
`Analysis Associates, I investigated failures in electrical and electronic
`
`systems in addition to performing design and development consulting.
`
`7.
`
`I left Failure Analysis in 1998 to join IP Managers, which later
`
`merged with Silicon Valley Expert Witness Group, now known as Thomson
`
`Reuters Expert Witness Services ("Thomson Reuters"). At Thomson Reuters,
`
`I work with companies on patent and trade secret matters.
`
`I also consult for
`
`a number of semiconductor companies, working with them to develop
`
`products and intellectual property, or assisting them in other technical areas
`
`through Blanchard Associates. Design and development projects that I have
`
`worked on range from the design and evaluation of specific components, to
`
`the selection of the technology appropriate for the fabrication of different
`
`subsystems of a system.
`
`8.
`
`I am a member of a number of professional societies, including
`
`the Institute of Electrical and Electronic Engineers, the International
`
`Microelectronics and Packaging Society, the American Vacuum Society, the
`
`Electronic Device Failure Analysis Society, and the Electrostatic Discharge
`
`Society. A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`5
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`Exhibit 1002
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`Page 6 of 81
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`Page 6 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`9.
`
`I have reviewed the specification, claims and file history of U.S.
`
`Patent No. 5,965,924, as well as the petition for inter partes review of this patent:
`
`IPR2016-00289, including the Declaration of Dr. John C. Bravman. I understand
`
`that the ’924 patent was filed on July 24, 1997, issued from a “continued
`
`prosecution application” (“CPA”) of U.S. App. No. 08/561,951 and claims priority
`
`to an application filed on November 22, 1995.
`
`I understand that, for purposes of
`
`determining whether a publication will qualify as prior art, the earliest date that
`
`the ’924 patent could be entitled to is November 22, 1995. However, I further
`
`understand that the prior assignee claimed a conception date of May 17, 1995
`
`during prosecution of the ’924 application. Amendment and Rule 131 Declaration
`
`dated Jan. 5, 1998 (Ex. 1006). Even under that conception date, the cited
`
`references are prior art and invalidate the ’924 patent.
`
`10.
`
`I have reviewed the following patents in preparing this declaration:
`
`0 U.S. Patent No. 5,475,240 (“Sakamoto”) (Ex. 1003).
`
`0 U.S. Patent No. 5,100,817 (“Cederbaum”) (Ex. 1004).
`
`11.
`
`I have reviewed the above patents and any other publication cited in
`
`this declaration.
`
`12.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’924 patent application
`
`6
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`Exhibit 1002
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`Page 7 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`was filed. In my opinion, a person of ordinary skill in the art for the ’924 patent
`
`would have found the ’924 patent invalid.
`
`13.
`
`I have been retained by the Petitioner as an expert in the field of
`
`semiconductor device fabrication and design.
`
`I am working as an independent
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $375 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`14.
`
`I have no financial interest in the Petitioner.
`
`I similarly have no
`
`financial interest in the ’924 patent, and have had no contact with the named
`
`inventor of the ’924 patent.
`
`I. RELEVANT LAW
`
`15.
`
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`
`16.
`
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that I should apply what is known as “the Phillips standar ,”
`
`rather than the broadest reasonable interpretation standard.
`
`7
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`Exhibit 1002
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`Page 8 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`17.
`
`Specifically, I have been informed and understand that since the ’924
`
`patent expired on November 22, 2015, the Phillips standard applies for the
`
`purposes of claim construction. I further understand that the Phillips standard
`
`means that claim terms are given their plain and ordinary meaning as understood
`
`by a person of ordinary skill in the art at the time of the invention in light of the
`
`claim language and the patent specification.
`
`18.
`
`I have also been informed and understand that any claim term that
`
`lacks a definition in the specification is therefore given its plain and ordinary
`
`meaning as understood by one of ordinary skill in the art.
`
`B. Anticipation
`
`19.
`
`I have been informed and understand that a patent claim may be
`
`“anticipated” if each element of that claim is present either explicitly, implicitly, or
`
`inherently in a single prior art reference. I have also been informed that, to be an
`
`inherent disclosure, the prior art reference must necessarily disclose the limitation,
`
`and the fact that the reference might possibly practice or contain a claimed
`
`limitation is insufficient to establish that the reference inherently teaches the
`
`limitation.
`
`C. Obviousness
`
`20.
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`8
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`Exhibit 1002
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`Page 9 of 81
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`the application was filed. This means that, even if all of the requirements of a
`
`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`21.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
`0
`
`0
`
`the level of ordinary skill in the art at the time the application was filed;
`
`the scope and content of the prior art; and
`
`0 what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`22.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
`9
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`0 whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
`0 whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
`0 whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
`0 whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
`
`0 whether there is some teaching or suggestion in the prior art to make the
`
`modification or combination of elements claimed in the patent; and
`
`0 whether the innovation applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`23.
`
`I understand that one of ordinary skill in the art has ordinary
`
`creativity, and is not an automaton.
`
`24.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`10
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`Exhibit 1002
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`Page 11 of 81
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`U.S. Patent No. 5,954,924
`
`Claims 1-6, 13, 14 and 16
`
`II. SUMMARY OF OPINIONS
`
`25.
`
`It is my opinion that every limitation of the structures described in
`
`claims 1 through 6, 13, 14 and 16 of the ’924 patent are disclosed by the prior art,
`
`and are anticipated and/or rendered obvious by the prior art.
`
`The following discussion and analysis is substantially the same as that of Dr.
`
`John C. Bravman in IPR20l6-00289, supplemented with additional analysis and
`
`comments provided throughout this declaration.
`
`III.
`
`INTRODUCTION TO THE ’924 PATENT
`
`26.
`
`The ’924 patent is directed to certain aspects of the structure and
`
`fabrication of transistors used in semiconductor and integrated circuit products
`
`such as microprocessors and memory. Transistors act as microscopic switches that
`
`turn on and off at extraordinarily high rates to enable aggregations of transistors
`
`(and other components) to process data. Transistors are made up of various
`
`structures including “contacts” that provide electrically conductive pathways into
`
`and out of certain structures within a transistor, and which thereby are used to
`
`connect transistors together.
`
`27.
`
`The ’924 patent is concerned with electrically connecting different
`
`transistor parts to each other in a particular way. Transistors typically have three
`
`terminals through which electrical signals may pass: a “source,” a “drain,” and a
`
`1 1
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`Page 12 of 81
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`“gate.” The ’924 patent is concerned with connecting the gate of one transistor to,
`
`for example, the source or drain of a neighboring transistor.
`
`28. According to the specification of the ’924 patent, there were many
`
`well-known ways of making electrical connections between different transistor
`
`parts. As shown in Figure 2B (below), for instance, one of the prior art ways of
`
`connecting the components of two transistors was by using two electrical
`
`connections called “plugs”—one connected to the gate of one transistor, and the
`
`other connected to the source or drain of the other—and then connecting those
`
`plugs together. As shown in Figure 3B (below), the purported invention of
`
`the ’924 patent was to replace the two plugs with one plug. 1
`
`Admitted Prior Art: Fig. 2B
`
`Allegedly Novel Structure: Fig. 3B
`
`
`
`29.
`
`In both the prior art (Figure 2B) and the allegedly novel structure of
`
`the ’924 patent (Figure 3B), the gate is connected to a diffusion region (z'.e., a
`
`1 All emphasis and annotations are added unless otherwise indicated.
`
`12
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`source or drain) by either two connected plugs, or a single plug. The patent does
`
`not claim that the one-plug structure provides any performance benefits over the
`
`two-plug structure. Instead, the benefit was that the one-plug structure was easier
`
`to manufacture than the admitted prior art.
`
`’924 patent at 1:57-2:63, 4:18-5:12
`
`(Ex. 1001).
`
`30.
`
`Long before the ’924 patent’s November 22, 1995 priority date, many
`
`others had already developed and used the exact same one-plug structure. U.S.
`
`Patent No. 5,475,240 (“Sakamoto”), for instance, which has an effective filing date
`
`of March 4, 1992, discloses the same one-plug structure that the ’924 patent
`
`contends is novel. Specifically, as shown in the patents’ respective figures, the
`
`one-plug structure of Sakamoto (Figure 1) is in all relevant aspects identical to the
`
`one-plug structure of the ’924 patent (Figure 3B).
`
`Sakamoto: Fig. 1
`
`’924 Patent: Fig. 3B
`
`
`
`13
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`Exhibit 1002
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`Page 14 of 81
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`

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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`31. As shown, both structures include a gate connected to a source or
`
`drain through a single plug.
`
`32.
`
`U.S. Patent No. 5,100,817 (“Cederbaum”) issued on March 31, 1992,
`
`and, just like the ’924 one-plug structure, discloses a single conducting plug
`
`connecting a gate to a source or drain.
`
`Cederbaum: Fig. 7
`
`33.
`
`Sakamoto and Cederbaum were not at issue during prosecution of
`
`the ’924 patent. These references anticipate and/or render obvious claims 1-6, 13,
`
`14 and 16 the ’924 patent.
`
`IV. BRIEF DESCRIPTION OF THE TECHNOLOGY
`
`34.
`
`The ’924 patent generally relates to the field of semiconductor
`
`integrated circuit manufacturing and claims particular structures for transistors in
`
`semiconductors, as well as a related method for manufacturing those structures.
`
`14
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`Exhibit 1002
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`Page 15 of 81
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`Page 15 of 81
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`Qualcomm,
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`

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`U.S. Patent No. 5,954,924
`
`Claims 1-6, 13, 14 and 16
`
`A. Overview of Transistor Fabrication
`
`1. Basic Structure of Transistors
`
`35.
`
`Semiconductor integrated circuits, such as microprocessors and
`
`computer memory, are typically made up of hundreds of millions (and in some
`
`cases billions) of microscopic structures called transistors. Transistors act as
`
`microscopic switches that turn on and off at extraordinarily high rates to enable
`
`aggregations of transistors (and other components) to process data.
`
`36. As shown in the figure below, transistors typically include three
`
`primary “electrodes” or “terminals”—a “gate,” a “source,” and a “drain”:
`
`
`
`37.
`
`The source and drain regions (also referred to as “diffusion regions”)
`
`are transistor components that emit (source) and receive (drain) current/carriers
`
`when the transistor is “on.” The gate typically sits between the source and drain
`
`and is a terminal that can have a Voltage applied to it that in turn causes a current to
`
`flow between the source and drain. As of the time of the invention of the ’924
`
`patent, the source and drain of a transistor were typically formed in the surface of a
`
`15
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`semiconductor “substrate,” while the gate typically sat above the substrate and
`
`separated from it by a thin layer of insulator (“gate oxide”).
`
`2. Formation of Transistor Components
`
`38.
`
`Transistor fabrication typically starts with a silicon substrate. In
`
`typical planar transistors, the source and drain regions (“diffusion regions”) are
`
`created by implanting regions of the substrate with ions (charged atomic particles)
`
`of different materials—called “dopants” or “impurities.” (Once implanted the ions
`
`become neutral atoms). This process—referred to as “doping” because it dopes the
`
`silicon substrate with atomic particles that have additional charge carriers—is
`
`shown below:
`
`
`
`A mask can be used for directing the charged particles to specific locations in the
`
`substrate.
`
`39.
`
`Structures can then be formed above the substrate by depositing layers
`
`of other materials onto the substrate. A gate electrode, for example, is formed by
`
`first growing or depositing a “gate oxide” (an insulator) on the substrate followed
`
`by depositing a conductive material (metal or polysilicon) on top of the gate oxide.
`
`16
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`Page 17 of 81
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`The conductive material acts as the gate, and the gate oxide creates a layer of
`
`isolation between the gate and the source/drain regions (“S/D regions” or
`
`“diffusion regions”).
`
`40.
`
`Insulating materials may then be deposited around and over the gate
`
`and the S/D regions to maintain electrical isolation where desired. Sidewall
`
`spacers, for instance, can be formed on each side of the gate electrode as shown
`
`below:
`
`
`
`As was known as of the time of the ’924 invention, such sidewall spacers help to
`
`prevent direct electrical contact between the gate electrode and nearby components
`
`and thus help to prevent short-circuits.
`
`3. Local Interconnects
`
`41. Many transistors can be connected together to form electronic circuits.
`
`For certain types of circuits, it is sometimes useful to connect the gate of one
`
`transistor to a diffusion region (the source or drain) of a nearby transistor. This
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`type of connection is called a “local interconnect,” because connections are made
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`locally between nearby transistors.
`
`42. According to the specification of the ’924 patent, a variety of different
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`types of local interconnects were well-known prior to the purported invention. For
`
`example, as shown in Figure 1B of the ’924 patent, one well-known way to form a
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`local interconnect was to position the gate in a location where it physically touches
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`the diffusion region on one side, creating an electrical connection. As shown in
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`Figure 2B of the ’924 patent, another well-known way to make a local interconnect
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`was to place one electrically conductive “plug” above the gate and another “plug”
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`above the diffusion (e. g., source or drain) region, and then electrically connect the
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`two plugs together.
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`Admitted Prior Art: Fig. 1B
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`Admitted Prior Art: Fig. 2B
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`
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`43.
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`The ’924 patent acknowledges that both examples were known prior
`
`art. See ’924 patent at Figs. 1A, 1B, 2A, 2B, 1:25-2:45, 3:30-35 (Ex. 1001).
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`1 8
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`B. Overview of the ’924 Patent
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`44.
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`The ’924 patent issued from U.S. App. No. 08/900,047, which was
`
`filed on July 24, 1997, and claims priority to an application filed on November 22,
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`1995.
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`’924 patent at cover page (Ex. 1001). The invention of the ’924 patent is a
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`single plug to connect different transistor parts.
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`’924 patent at 2:32-67, 4: 18-5: 12
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`(Ex. 1001).
`
`1. Problem Disclosed in the ’924 Patent
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`45.
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`The ’924 patent addresses manufacturing inefficiencies in forming
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`local interconnects. Figures 1 and 2 of the ’924 patent are prior art and show
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`examples of two well-known types of local interconnects that (according to
`
`the ’924 patent) are inefficient to manufacture.
`
`46.
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`Figure 1B shows a “buried contact” local interconnect structure in
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`which the gate directly touches—z'.e., is in direct electrical connection with—a
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`diffusion region. According to the ’924 patent, the problem with this structure is
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`that the gate has to be implanted with the same type of impurities as those
`
`implanted in the diffusion region. See ’924 patent at 1:57-2:11 (Ex. 1001). But
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`most manufacturers use a Variety of different types of impurities in different
`
`transistors. To use the “buried contact” approach, a manufacturer would have to
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`ensure that any two transistors connected using this approach use the same
`
`impurities, which complicates the manufacturing process. See id.
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`19
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`Admitted Prior Art: Fig. 1B
`
`Admitted Prior Art: Fig. 2B
`
`
`
`47.
`
`Figure 2B shows another prior art local interconnect structure, using
`
`what is called a “strapping” technique. To form this “strapping” local interconnect
`
`structure, a manufacturer creates two electrically conductive plugs (numbers 44
`
`and 46)—one above the gate and one above a diffusion region. The manufacturer
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`then places an electrically conductive “local strap” (number 50) on top of the
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`plugs, electrically connecting the two plugs together. This local strap is also
`
`sometimes called a “shunt” or a “shunt layer.” In combination, the two plugs and
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`the local strap electrically connect the gate to a diffusion region. See ’924 patent at
`
`2: 12-32 (Ex. 1001). According to the ’924 patent, the problem with the strapping
`
`technique is that it requires a large number of manufacturing process steps, as well
`
`as significant space to accommodate the two plugs and the local strap. See ’924
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`patent at 2:33-41 (Ex. 1001).
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`20
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`Page 21 of 81
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
`
`2. Summag of Invention of the ’924 Patent
`
`48.
`
`The ’924 patent’s claimed structure includes nearly identical
`
`components as the prior art described in the specification. Specifically, both the
`
`claimed structure and the prior art include a substrate, a gate, a diffusion region, a
`
`sidewall spacer adjacent to the gate, and an insulating layer.
`
`Admitted Prior Art: Fig. 2B
`
`Preferred Embodiment: Fig. 3B
`
`
`
`49. As shown in Figures 2B and 3B, in both the prior art of the ’924
`
`patent and the structure of the disclosed embodiment, the gate is connected to the
`
`diffusion region (source or drain), by either two connected plugs, or a single plug.
`
`The diffusion region is located in a substrate and is not directly connected to the
`
`gate. The gate is substantially covered by an insulating layer.
`
`50.
`
`The only feature that the patent describes as novel, which is shown in
`
`Figure 3B, is the use of a single metal plug to connect the gate and the diffusion
`
`region, rather than connecting the two components directly (as in the prior art
`
`21
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`“buried contact” technique (Figure 1B)) or using two plugs (as in the prior art
`
`“strapping” technique (Figure 2B)). ’924 patent at 2:64-67, 3:35-36 (describing
`
`Figure 3B as “a cross-sectional View of a preferred embodiment of the present
`
`invention.”), 4:18-5:12, claims 1, 7 (Ex. 1001); see also id. at 2:42-63.
`
`3. Prosecution History
`
`51.
`
`The ’924 patent issued from a “continued prosecution application”
`
`(“CPA”) of U.S. App. No. 08/561,951. CPA Request dated Feb. 10, 1999 (Ex.
`
`1005). During prosecution of the ’924 patent, the Applicant tried to antedate a
`
`prior art reference, based on a lab notebook dated May 17, 1995. Amendment and
`
`Rule 131 Declaration dated Jan. 5, 1998 (Ex. 1006). For purposes of this Petition,
`
`I understand that the references relied upon by Petitioner all qualify as prior art
`
`even if the Patent Owner could ultimately prove a conception date as early as May
`
`1 7, 1 995.
`
`52. According to this lab notebook, the novelty of the ’924 invention
`
`arises from the use of a single plug—which is what allegedly leads to fewer
`
`processing steps as compared to known prior art techniques. See Rule 131
`
`Declaration dated January 5, 1998, Exhibit A (“By placing a metallic plugged
`
`contact where poly is required to shunt to diffusion, contacts to [different types of]
`
`diffusion can be achieved
`
`[T]his will require no more layout area than the
`
`22
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`traditional buried contact. This method has potential [manufacturing] process step
`
`savings of 8-11 steps over Trad. BC [traditional buried contact local interconnect
`
`(as shown in Figure 1B of the ’924 patent)] and 6-8 steps over strapping [local
`
`interconnect (as shown in Figure 2B of the ’924 patent)].”) (Ex. 1006).
`
`53. However, during prosecution, rather than relying on this “single plug”
`
`structure, the Applicant relied on other alleged differences to overcome the prior
`
`art applied by the Examiner. The present petition relies on prior art that was not
`
`before the Examiner. This prior art teaches not only the “single plug” aspect of the
`
`claims, but also all of the additional minor differences that the Applicant used to
`
`try to distinguish the Examiner’s prior art.
`
`a. The “sidewall spacer” limitations
`
`54.
`
`The Examiner rejected the original claims under 35 U.S.C. § 102(e)
`
`based on U.S. Patent No. 5,451,434 to Nicholls (“Nicho1ls”). Office Action dated
`
`Nov. 7, 1996 at p. 3 (Ex. 1007). Nicholls taught a single metal plug that connects a
`
`diffusion region and a gate. In order to overcome the rejection, the Applicant
`
`added a limitation to the claims requiring a sidewall spacer adjacent to the gate.
`
`Amendment dated June 9, 1997 at pp. 2-3 (Ex. 1009). Nicholls expressly teaches
`
`the placement of a sidewall during manufacture, but also teaches that the sidewall
`
`can be completely or “partially removed” in a later manufacturing step. Nicholls at
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`23
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`U.S. Patent No. 5,954,924
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`Claims 1-6, 13, 14 and 16
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`4:25-32 (Ex. 1008). The Applicant overcame the rejection by arguing that the
`
`removal of the sidewall during manufacturing taught away from retaining a
`
`sidewall spacer adjacent to the gate. Amendment dated June 9, 1997 at pp. 3-4
`
`(Ex. 1009). The prior art relied upon in this petition teaches the “sidewall spacer”
`
`lin1itation.
`
`b. Direct electrical connection
`
`55.
`
`The Examiner also rejected the claims under 35 U.S.C. § l02(e) based
`
`on U.S. Patent No. 5,541,427 to Chappell (“Chappell”). Office