United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,100,317
`
`Cederbaum et al.
`
`[45] Date of Patent: Mar. 31, 1992
`
`llllllllllllllllllllll|||||IllllllllllllllIlllllllllIIIIHIIIIIIIIIIIIHIII
`US005100817A
`
`Assistant Examiner-——Michae1 Trinh
`Attorney, Agent. or Firm—Richard A. Romanchik
`
`ABSTRACI‘
`[57]
`A stacked semiconductor structure including a base
`structure (18/19) is comprised of a semiconductor sub-
`strate having active regions (21) of devices (N1, .
`.
`. )
`formed therein and/or a plurality of polysilicon lines
`(231, .
`.
`. ) formed thereupon; a first thick passivating
`layer (26/27) having a set of first metal contact studs
`(30—1, .
`.
`. ) therein contacting at least one of said active
`regions (21) and/or said polysilicon lines (23-1, . . . ), the
`surface of said first metal contact studs being coplanar
`with the surface of said first thick passivating layer; a
`plurality of first polysilicon lands (31-1, .
`. . ) formed on
`the said thick passivating layer, certain portions of said
`first polysilicon lands defining the source, drain and
`channel regions forming the body of a PFET device
`with at least one region (SP1) contacting one of said
`first metal contact studs; a thin insulating layer (33)
`forming the gate dielectric layer of said PFET device; a
`plurality of highly doped second polysilicon lands (35-
`1A, .
`.
`. ) formed over by said thin insulating layer (33);
`a certain portion of said second polysilicon lands (35-
`IA,
`.
`.
`.
`) forming the gate electrode (GPI) of said
`PFET device (SP1) which is self-aligned with said
`source (SP1) and drain (DP!) regions; a second thick
`passivating layer (37/38) having a set of second metal
`contact studs (40-1, .
`.
`. ) therein contacting at least one
`of said first or second polysilicon lands (31-1, . . . ; 35-1,
`.
`.
`. ) and/or said first contact studs (30-1,
`.
`.
`. ); the
`surface of said second metal contact studs is coplanar
`with the surface of said second thick passivating layer;
`a first metal interconnection configuration having metal
`lands (41-1, .
`.
`. ) electrically contacting at least one of
`said second metal contact studs (40-1, .
`.
`. ); and, a final
`insulating film (42).
`
`14 Claims, 7 Drawing Sheets
`
`[54] METHOD OF FORMING STACKED
`SELF-ALIGNED POLYSILICON PFET
`DEVICES AND STRUCTURES RESULTING
`THEREFROM
`
`[75]
`
`Inventors: Carl Cederbaum, Paris; Roland
`Chanclou, Perthes; Myriam Combes,
`Evry; Patrick Moné, Ponthierry, all
`of France
`
`[73] Assignee:
`
`International Business Machines
`Corporation, Arinonk, N.Y.
`
`[21] Appl. No.: 729,250
`
`[22] Filed:
`
`Jul. 12, 1991
`
`Foreign Application Priority Data
`[30]
`Jul. 31, 1990 [EP]
`European Pat. Off.
`........ 904801123
`
`Int. Cl.5 ......................................... .. H01L 21/265
`[51]
`
`.
`.
`[52] U.S.Cl.
`437/41;437/56;
`437/57; 437/200; 437/915; 437/245; 437/913;
`437/52
`[58] Field of Search ................... .. 437/41, 195, 52, 56,
`437/915, 245, 200, 59, 913, 57, 58
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`437/915
`4,498,226 2/1985 Inoue et al.
`437/245
`4,795,722
`1/1989 Welch et al.
`. .. .. .. 437/41
`4,868.l37 9/1989 Kubota .. .. . . . . ... . ...
`..... .. 437/56
`4,902.637
`2/1990 Kondou et al.
`4,987,099
`l/l9_9l Flanner ............................. .. 437/245
`FOREIGN PATENT DOCUMENTS
`
`
`
`.
`0223920 7/1986 European Pat. Off.
`CD56456 4/1983 Japan ................................. .. 437/915
`0253228 10/1989 Japan ..
`.
`0268151 10/1989 Japan ..
`(£76233
`3/1990 Japan ................................... 437/195
`
`
`
` —_; I
`.
`Z
`/2 22 ’ra>..‘.-.;.
`‘V’
`a
`
`1
`
`In‘)
`
`
`
`INTEL 1 104
`
`
`
`
`
`— 5-iA(GF I1
`
`9:
`
`A74
`“er:
`
`l\\\__§
`
`\*
`§ =°-=
`1...» -==\\.\ i"m:=’
`
`é,‘§'v/””“”"”'§ ”
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 1 of 7
`
`5,100,817
`
`WL
`
`. d .
`5.
`f3‘)
`sx§\\\x?/ ,;,«:\
`
`
`
`
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 2 of 7
`
`5,100,817
`
`
`
`"7/N120
`23-1]
`7 1.’//l/X
`
`26
`23-2
`2
`I
` _ 5
`
`..__—__._...—
`
`\/
`
`E
`
`21
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 3 of 7
`
`5,100,817
`
`
`!‘§‘-
`§
`§ 2.9:
`
`
`
`
`
`
`,/
`
`\
`
`
`
`
`
`j 17
`l9(p )
`
`753’
`< §§‘
`—I
`—§
`1}?
`§
`
`
`
`x
`
`
`
`19<p-)
`
`FIG. 8
`
`|
`
` §j
`
`an--§
` s§\-Wfimfl/2% §
`
`
`
` ¢i’—"’”//--I--
`
`K
`
`*
`
`
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 4 of 7
`
`5,100,817
`
`311
`
`
`
`\Ҥx% 2
`%~*xx~..‘*§;~\x\‘\\
`
`
`~.§§7§f\ }\\§ ‘X ,
`«$5 ,
`5
`Max gwzwx
`V
`
`I“— \
`\I
`
`?# \
`
`
`
`
`
`
`
`i
`§/155%’; %m
`I?-—
`
`
`
`
`
`’
`-§ "§§l
`\\”fi§
`>w$ié%§-
`
`
`
`§
`
`.4§a.\
`
`I9(p-)
`
`

`
`-U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 5 of 7
`
`5,100,817
`
`@ §§}};{§%§\A_v-.:"'
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 6 of 7
`
`5,100,817
`
`

`
`U.S. Patent
`
`Mar. 31, 1992
`
`Sheet 7 of 7
`
`5,100,817
`
`V
`
`&
`L\Vk\\\\\\\‘\Vs\\\Vk\V!%!L ‘
`
`
`
`
`
`
`
`'/4%"E.
`
`
`Azggr/////////////Apt‘ I
`
`.._-_._.,
`[/1
`
`
`
`
`
`
`u’////
`
`4’?
`.,£5
`
`I7////Z $5/////Aééfié
`
`-
`7'7’///////.—
`
`///////////1.
`
`
`

`
`1
`
`5,100,817
`
`METHOD OF FORMING STACKED
`SELF-ALIGNED POLYSILICON PFET DEVICES
`AND STRUCTURES RESULTING THERE}-‘ROM
`
`TECHNICAL FIELD
`
`The present invention relates to Integrated Circuit
`manufacturing and more specifically, to a method of
`forming stacked, self-aligned polysilicon gate PFET
`devices in semiconductor chips and to the structures
`resulting therefrom. In particular, the method has appli-
`cability in the forming of stacked self-aligned polysili-
`con gate PFETS to be used as load devices in six device
`(6D) SRAM cells.
`BACKGROUND ART
`
`Polycrystalline silicon (polysilicon) resistors are com-
`monly used as load devices in a variety of digital and
`analog applications, and in particular, in Static Random
`Access Memories (SRAMs). SRAM cells with resistive
`loads are hereinafter referred to as the 4D/ZR SRAM
`cells. Stacking polysilicon load resistors above the
`NFETS in 4D/ZR SRAM cells is much appreciated in
`the design of the SRAM chip layout, because it results
`in a significant reduction in the SRAM cell size due to
`the fact that the cell area is only determined by the area
`used by the NFETs. It is now a general practice in the
`industry to have the load resistors of 4D/2R SRAM
`cells fonned by resistive polysilicon lands obtained
`from a very thin layer of either intrinsic or lightly
`doped polysilicon material. However, because these
`load resistors must be fairly high-valued, i.e. in the tera-
`ohms 00120) range or above, limitations on the current
`drawn by the cell results in a limit of l megabit capacity
`of 4D/2R SRAM cell chips. As a matter of act, for
`increased capacities, the polysilicon layer must be so
`thin that the process tolerances are too difficult to con-
`trol. In addition, 4D/2R SRAM cells are also very
`sensitive to soft errors produced by alpha particles. For
`memory larger than l megabit, stacked PFETs instead
`of polysilicon resistors have to be used as load devices,
`although this is at the cost of a significantly more com-
`plicated manufacturing process.
`FIG. 1 shows a conventional 6D SRAM cell circuit,
`referenced 1, with PFETs as load devices. Two cross-
`coupled NFETS N1 and N2, referred to as the driver
`transistors, are connected between common node 2,
`which is tied to a first supply voltage Vs (usually the
`ground Gnd), and respective nodes 3 and 4, hereinafter
`referred to as charge storage nodes. These nodes 3, 4 are
`connected to a common node 5 which is tied to a second
`supply voltage (usually a positive voltage Vc), respec-
`tively, through PFETS P1 and P2. Nodes 3 and 4 are
`also respectively connected to the bit lines BLT and
`BLC through NFETs N3 and N4, hereinafter referred
`to as to access transistors. The gate electrodes of
`NFETs N3 and N4 are connected to the word line WL
`for READ and WRITE operations.
`FIG. 2 is a partial cross-sectional view of the struc-
`ture of the 6D SRAM cell circuit of FIG. 1 when inte-
`grated in a semiconductor substrate according to a con-
`ventional CMOS manufacturing process offering
`stacked polysilicon gate PI’-‘ET devices (sPFETs). The
`structure referenced 6 is a good example of the ad-
`vanced state of the art known to date and is extracted
`from an article entitled: “A .l p.A stand-by current
`ground-bounce-immune l-M bit CMOS SRAM by M.
`Ando et al, published in the IEEE JSSC vol. 24, N° 6,
`
`10
`
`20
`
`25
`
`30
`
`35
`
`45
`
`55
`
`65
`
`2
`Dec. 89, pp. 1708-1713. Reference numeral 7 indicates
`the P type silicon substrate. Numerals 8 indicate the
`different field recess oxide (ROX) regions that are used
`to isolate the different active regions of the structure.
`Numerals 9 are active N+ implanted source and drain
`regions of the NFETs. Numeral 12 indicates the gate
`dielectric layer,
`typically an SiOz layer. The highly
`doped N + polysilicon gate electrodes of driver NFETS
`N1 and N2 are respectively referenced 11-1 and 11-2.
`Polysiliccn gate electrode 11-2 forms a buried contact
`with region 9' which is a protrusion of the drain region
`9 of NFET N1. The gate electrodes 11-1 and 11-2 and
`the source and drain regions of NFETS N1 and N2 are
`covered by a thin insulating protective layer 12 of SiO2,
`which also forms oxide sidewalls or spacers on the
`lateral sides of gate electrode 11-1 of NFET N1. A
`polysilicon land 13 surmounts gate electrodes 11-1 and
`11-2 and is isolated therefrom by the SiO2 layer 12.
`Polysilicon land 13 results from the patterning and se-
`lective doping of an intrinsic or lightly doped polysili-
`con layer that has been deposited to form the body of
`sPFETs. As apparent from FIG. 2, this polysilicon land
`13 is highly doped with a P type dopant except just
`above gate electrode 11-1. The undoped region forms
`the channel region of the sPFET Pl while the adjacent
`P+ doped regions form the source and drain regions
`thereof. An extension of the drain region of sPFET P1,
`referred to as.the extended drain region, contacts the
`small portion of gate electrode 11-2, which is exposed
`through an opening in oxide layer 12. N+ doped gate
`electrode 11-1 of NFET N1 also serves as the gate
`electrode of sPFET P1, while layer 12 is the gate dielec-
`tric thereof. For each cell, oxide layer 12 is opened in all
`locations where it is necessary to make a contact be-
`tween the N+ doped polysilicon gate electrode of a
`NFET and the adjacent P+ extended drain region of
`the corresponding sPFET. Note that region 9, protru-
`sion 9', gate electrode 11-2, and the extended drain
`region of sPFET P1 13 are at the potential of node 3,
`thereby achieving the desired cross-coupling of the
`devices as illustrated in the cell circuit of FIG. 1. At this
`stage of the process, the structure is said to have com-
`pleted the Master Slice processing steps of a polysilicon
`gate CMOS FET technology. The structure is conse-
`quently passivated by a relatively thick insulating SiO2
`layer 14 of about 500 nm. All of the aforementioned
`components 7-14 of the structure 6 result from the
`FEOL (Front End Of the Line) processing.
`Elements that will now be described are formed dur-
`ing the personalization steps or BEOL (Back End Of
`the Line) processing. Numeral 15 is a typical example of
`a polycide land or line used as a power bus. In FIG. 2,
`polycide land 15 connects a N+ active region 9 (the
`source region of a NFET not illustrated in FIG. 2) to
`Grid and is hereinafter referred to as the God bus. An
`additional insulating SiOz layer 16 terminates the struc-
`ture. Layer 16 is provided with contact openings (not
`shown) to allow appropriate contacting with the metal
`bit lines BLT and BLC and power busses (e.g. the Vc
`power bus). As apparent from FIG. 2, all the succeed-
`ing layers, and in particular polysilicon layer 13, are
`conformally deposited, thereby resulting in the typical
`“corrugated” relief aspect of the upper layers of struc-
`ture 6.
`The cell construction of FIG. 2, wherein PFETs used
`as load devices are stacked above N'FETs, is of great
`interest in terms of density, because the cell area is only
`
`

`
`5,100,817
`
`10
`
`20
`
`25»
`
`30
`
`35
`
`55
`
`3
`determined by the area of NFETS. However, the dis-
`closed semiconductor structure and its corresponding
`manufacturing process have some major
`inconve-
`niences which are recited below.
`1. The said conventional manufacturing process is not
`of the self-aligned type. Self-aligned processes com-
`bined with oxide spacers are preferred in order to
`avoid hot electrons and punch-through problems. In
`the structure of FIG. 2, no oxide spacers on the side-
`walls of gate electrodes are provided to the sPFETs.
`2. The structure of FIG. 2 requires six additional masks
`with respect to a conventional manufacturing process
`of 6D SRAM cell chips not offering sPFETs. The
`first mask is used to remove the gate oxide layer 10
`above protruded source region 9' of NFET N1 to
`allow the buried contact between gate electrode 11-2
`and said region 9’. The second mask makes an open-
`ing above gate electrode ll-2. The third mask deline-
`ates the N type lightly doped polysilicon layer 13.
`The third mask is used to shape the desired polysili-
`con land wherein sPFET P1 and its related extended
`drain region (for connection with underlying gate
`electrode 11-2). The fourth mask is a block-out mask
`that
`is required to protect
`the channel region of
`sPFET Pl from the implantation of P type dopants,
`while forming the highly doped P+ source and drain
`regions thereof, along with said extended drain re-
`gion. The fifth mask defines contact openings where
`polycide lands conveying the Gnd potential contact
`source regions 9 of NFE'l's e.g. driver transistors. An
`example of a Gnd bus is shown in FIG. 2. Also. the
`sixth mask delineates polycide land such as the word
`lines and some power busses.
`3. sPFET P1 is dependent upon the underlying NFET
`NI size and lay-out which in turn, results in less flexi-
`bility in the design. Because the gate electrode 11-1 of
`NFET N] is also the gate electrode of sPFET Pl, the
`layout of the two devices are strongly coupled both
`in terms of device size and device lay-out. More gen-
`erally, since the gate Iength of the NFET (e.g. N1)
`must be at the minimum allowed by the lithography
`- for maximum performance, so must be the gate length
`of the corresponding sPFET (e.g. Pl). This consti-
`tutes a potential source of reliability hazards. For
`example, if the out—diffusion of the P+ dopants con- 45
`tained in the implanted source and drain regions of
`the sPFET P1 is not well controlled, the source and
`drain regions get
`too large,
`thereby reducing the
`effective channel length of sPFET P1. As a conse-
`quence, punch-through problems can occur. The
`channel
`length of sPFET Pl cannot be increased
`since this length is dictated by the performance re-
`quirements of NFET N1 as mentioned above. In
`addition, since the block-out mask defining the chan-
`nel region of sPFET P1 is also at minimum image
`size, alignment tolerance between this bIock—out mask
`and the channel region can result in a channel region
`not correctly aligned with the gate electrode.
`FIGS. 3A and 3B illustrate the effect of misalignment
`on sPFET P] as to the introduction of parasitic de-
`vices to an ideal PFET P (that would be obtained
`should misregistration not exist), that has inherently
`poor performance. In the fust case (positive misalign-
`ment) shown in FIG. 3A, the diode D (forwardly-
`biased) and a high value resistor R are in series with
`the source region s of the ideal PFET P. These para-
`sitic devices decrease the effective gate to source
`overdrive voltage (VGS- VT) of sPFET P] (which
`
`65
`
`4
`has already a high threshold voltage VT) and hence
`will decrease the “ON” current of sPFET P1. In the
`second case (negative misalignment), shown in FIG.
`3B, the parasitic devices: resistor R and diode D (now
`reversely-biased) are in series with the drain region d
`of the ideal PFET P and similarly decrease the cur-
`rent capability of sPFET P1. As a result, the latter is
`far from an ideal PFET P.
`.
`4. The gate electrode of the sPFET Pl does not have an
`optimized work function. Since both NFET N1 and
`the corresponding sPFET P1 formed thereupon
`share the same N+ gate electrode 11-1,
`the gate
`electrode of the sPFET is therefore of the N+ type
`while P+ type would have been preferred. It is well
`recognized that this situation creates punch-through
`problems, because in this case, the channel region is
`buried instead of being in surface. Punch-through
`effects induce leakage currents which are critical for
`the SRAM cell stand-by power consumption.
`5. As pointed out above in conjunction with FIG. 2, the
`conventional manufacturing process results in a non
`planarized structure 6. The gate oxide layer 12 and
`the polysilicon layer 13 forming sPFET P1 are depos-
`ited over the castellated topology of the NFET N1
`gate electrode 11-1, although slightly smoothed by
`protective layer 12, thereby creating reliability prob-
`lems known as “step coverage”, since polysilicon
`layer 13 is much thinner than gate electrode 11-1.
`6. A parasitic P+/N+ diode is formed between N+
`gate electrode 11-2 of NFET N2 and the P+ ex-
`tended drain region of sPFET P1. This diode deterio-
`rates the contact quality which is no longer of the
`ohmic type, thereby slowing down the SRAM cell
`performance.
`7. The word lines WL, some power busses and possibly
`the local interconnect scheme that makes straps and
`short distance connections at the silicon wafer level,
`are made of polycide. Polycide is a quite good con-
`ductive material, however it
`is known to exhibit
`higher resistivities than metal.
`8. Finally, the structure of FIG. 2 has a poor design
`flexibility because of the difficult contacting of source
`region of sPFET P1 to Vc power bus because the
`presence of the polycide lands 15.
`DISCLOSURE OF THE INVENTION
`
`An object of the present invention is to provide a
`method of forming stacked self—aligned polysilicon gate
`PFET devices according to a self-aligned technique,
`wherein said devices are provided with spacers to re-
`duce punch-through problems.
`Another object of the present invention is to provide
`a method of forming stacked self-aligned polysilicon
`gate PFET devices that requires a reduced number of
`masking steps.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`con gate PFET devices that is independent of NFET
`device size and lay out, thereby avoiding potential prob-
`lems related to misregistration.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`con gate PFET devices wherein the gate electrodes of
`said devices are made of P+ polysilicon for adequate
`work function.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`
`

`
`10
`
`I5
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`5
`con gate PFET devices wherein said devices are
`formed on planar surfaces for better reliability.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`con gate PI-‘ET devices wherein no parasitic diodes are
`produced in the contacts.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`con gate PFET devices wherein word lines and power
`busses are all made of metal for improved conductivity.
`Yet another object of the present invention is to pro-
`vide a method of forming stacked self-aligned polysili-
`con gate PFET devices offering quite good design flexi-
`bility for easy contacting of the source regions of PFET
`devices to the Vc power bus.
`According to the invention, a stacked semiconductor
`structure includes a base structure comprised of a semi-
`conductor substrate having active regions of devices
`formed therein and a plurality of polysilicon lines
`formed thereupon after completion of the Master Slice
`processing steps characterized in that
`it further in-
`cludes:
`a first thick passivating layer disposed on said base
`structure having a set of first metal contact studs therein
`contacting at least one of said active regions and/or said
`polysilicon lines; the surface of said first metal contact
`studs is coplanar with the surface of said first thick
`passivating layer;
`a plurality of first polysilicon lands formed on the said
`thick passivating layer, certain portion of said first
`polysilicon lands define the source, drain and channel
`regions forming the body of a PFET device; at least one
`region contacting one of said first metal contact studs;
`a thin insulating layer disposed onto the resulting
`structure forming the gate dielectric layer of said PFET
`device;
`a plurality of highly doped second polysilicon lands
`formed over said thin insulating layer; certain portion of
`said second polysilicon lands forming the gate electrode
`of said PFET device which is self-aligned with said
`source and drain regions; and
`a second thick passivating layer disposed onto the
`resulting structure having a set of second metal contact
`studs therein contacting at least one of said first or sec-
`ond polysilicon lands and/or said first contact studs; the
`surface of said second metal contact studs is coplanar
`with the surface of said second thick passivating layer.
`The manufacturing method used to produce this
`stacked semiconductor structure includes the following
`sequence of steps:
`a) depositing a first thick passivating layer of a dielec-
`tric material that can be planarized onto the said base
`structure;
`'
`b) forming a set of first stud openings in said first
`thick passivating layer exposing at least one active re-
`gion and/or one of said polysilicon lines;
`c) depositing a first layer of a conductive material, to
`fill said first stud openings and define a set of first
`contact studs;
`d) planarizing the structure to make the top surface of
`said first contact-studs coplanar with the surface of said
`first thick passivating layer;
`e) depositing a first polysilicon layer lightly doped
`with an impurity of a first type of conductivity;
`f) patterning said polysilicon layer to define a plural-
`ity of first polysilicon lands to be used either as the body
`of PFET devices and/or interconnection conductors
`contacting said first contact studs at desired locations;
`
`5,100,817
`
`6
`g) depositing a thin insulating layer to form the gate
`dielectric of PFET devices and patterning it to define
`contact openings to expose certain first contact studs at
`desired locations;
`h) depositing a second layer of polysilicon and pat-
`terning it to define a plurality of second polysilicon
`lands, to be used either as the gate electrodes of the said
`PFET devices or as interconnection conductors, con-
`tacting first contact studs through said contact open-
`11185;
`i) blanket implanting ions of a second type of conduc-
`tivity to define in particular self-aligned source and
`drain regions in said first polysilicon lands using the said
`gate electrodes of PFET devices as a block-out mask
`and dope said interconnection conductors;
`j) depositing a cap layer at least over said second
`polysilicon lands;
`k) depositing a second thick passivating layer of a
`dielectric material that can be planarized;
`l) forming a set of second stud openings in said second
`thick passivating layer to expose desired portions of said
`first and/or second polysilicon lands and/or portions of
`said first contact studs;
`in) depositing a second layer of a conductive material
`to fill said second stud openings and define a set of
`second contact studs; and,
`n) planarizing the structure to make the top surface of
`said second contact studs coplanar with the surface of
`said second thick passivating layer.
`Preferably, said conductive material is a metal, typi-
`cally tungsten and said ions of a second type of conduc-
`tivity are boron ions.
`Compared to the prior art approach described in
`conjunction with the structure of FIG. 2, the present
`method of forming stacked self-aligned polysilicon gate
`PFET devices and the structures resulting therefrom
`have the following advantages:
`1. It is a self-aligned process.
`2. Only three extra masks are required.
`3. The sPFET is independent of the underlying
`NFET size and layout.
`4. The sPFET is controlled by a P+ doped polysili-
`con gate electrode.
`5. The SPFET device is formed onto a planarized
`surface.
`‘
`6. The N+/P+ diode contact structure is replaced
`by a tungsten contact stud forming an ohmic contact.
`7. Word Line WL, Grid and Vc power busses are
`made of metal instead of polycide.
`8. Very high design flexibility which allows easy
`contacting of the sPFET source regions to the Vc
`power bus.
`These and other objects and advantages thereof, may
`best be understood by reference to the following de-
`tailed description of an illustrated preferred embodi-
`ment to be read in conjunction with the accompanying
`drawings.
`
`55
`
`60
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a schematic diagram of a conventional 6D
`SRAM cell circuit including two PFETs as load de-
`vices.
`
`FIG. 2 is a cross-sectional view, partially broken
`away, of the structure of the 6D SRAM cell circuit of
`FIG. 1 when integrated in a silicon substrate according
`to a conventional CMOS FET manufacturing process
`offering stacked polysilicon gate PFET devices.
`
`

`
`5,100,817
`
`I0
`
`15
`
`20
`
`7
`FIG. 3A is a cross-sectional view, partially broken
`away, of the PFET device structure of FIG. 2, utilizing
`positive mask misregistration, and a schematic diagram '
`of the parasitic device introduced thereby.
`FIG. 3B is a cross-sectional view, partially broken
`away. of the PFET device structure of FIG. 2, utilizing
`negative mask misregistration, and a schematic diagram
`of the parasitic device introduced thereby.
`FIG. 4 shows a partial cross-sectional view of a con-
`ventional base structure of the 6D SRAM cell of FIG.
`1 after having completed the Master Slice processing
`steps of a standard CMOS FET manufacturing process.
`FIGS. 5-14 show the structure of FIG. 4 being pro-
`cessed through a sequence of processing steps in accor-
`dance with a preferred embodiment of the method of
`the present invention.
`FIGS. 15 and 16 are plan views of a typical lay-out of
`the 6D SRAM cell with stacked self-aligned polysilicon
`gate PFETS as load devices of the present invention, at
`two different stages of the manufacturing.
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`FIG. 4 shows a partial cross-sectional view of a con-
`ventional base structure of the prior art after source/-
`drain region and polysilicon gate electrode formation
`that results from a standard CMOS manufacturing pro-
`cess. The disclosed portion shows structural parts of the
`driver NFETS N1 and N2 of the 6D SRAM cell circuit
`of FIG. 1 and is comparable in some respect with the
`structure shown in FIG. 2. In FIG. 4, the whole struc-
`ture is designated by reference 17 and is briefly de-
`scribed thereafter. The starting material consists of a
`conventional P+ silicon substrate 18 having a P“ epi-
`taxial layer 19 thereon. ROX regions 20 are used as it is
`well known for the skilled man to isolate active regions
`one from the others at the surface of the wafer. N+
`implanted active regions 21 have been formed in the
`epitaxial
`layer 19 to constitute the source and drain
`regions of the NFETs. Active regions 2] are generally
`provided with a thin TiSi2 contact layer to reduce their
`sheet resistance, thereby improving electrical contact
`quality with the contact studs yet to be formed. The
`gate dielectric layer, typically an SiO2 layer, is refer-
`enced 22. Numerals 23 indicate the remaining portions
`of the N+ highly doped polysilicon layer 23 that has
`been patterned to create the polysilicon gate electrodes.
`Numerals 23-1 and 23-2 designate respectively the gate
`electrodes of NFETs N1 and N2. Oxide sidewalls or
`spacers 24 have been formed on the lateral sides of the
`polysilicon gate electrodes for a better definition of the
`charmel length of NFETS. The above-described device
`structure of FIG. 4 is shown for the purpose of illustrat-
`ing the present invention, and is a conventional struc-
`ture in the art, amenable to fabrication by the use of
`many known semiconductor CMOS FET manufactur-
`ing processes, but is not limited to CMOS technology.
`It is to be noted that, the remaining polysilicon portions
`_are not limited to gate electrodes, they could be lands
`used as conductors, as such forming the extrinsic base
`contact in a polysilicon self-aligned bipolar transistor
`manufacturing process. Consequently,
`the remaining
`polysilicon portions 23 will be referred to more gener-
`ally as polysilicon lines. Also, active regions 21 are not
`limited to source and drain regions of FETS, but also
`include emitter, base and collector regions of bipolar
`devices. Taking into account that the structure of FIG.
`4 could be adapted to result either from a bipolar,
`
`25
`
`30
`
`35
`
`45
`
`55
`
`65
`
`8
`CMOS or BiCMOS manufacturing process, any base
`structure, at the stage of FIG. 4, is said to have com-
`pleted the Master Slice processing steps.
`In other
`words, the active regions 21 (irrespective of the type of
`devices formed therein), and optionally, polysilicon
`lines 23-1, .
`.
`. have been formed.
`Now a preferred embodiment of the method of the
`present invention will be described with reference to
`FIGS. 5 to 14.
`I) First, the wafer having a structure according to
`FIG. 4 is cleaned by dipping in a tank containing an
`H2804/I-I202 (4:1) acidic solution. This cleaning step
`will hereinafter be referred to as the Piranha clean. A
`thin (about 50 nm) Si3N4 diffusion barrier layer (not
`shown) is then blanket deposited over the wafer. The
`Si 3N4 diffusion barrier layer avoids potential dissolution
`of the TiSi2 layer in the upper layers to be subsequently
`formed. This step is completed in a standard LPCVD
`equipment at 785' C. with a SiH2Cl9/NI-I3 reactive gas.
`An intrinsic polysilicon etch stop layer 25 is then con-
`formally deposited over the surface of the wafer using
`conventional CVD process to a thickness in the range
`of 50 nm. The etch stop layer is used to protect the
`bird's beak of the ROX regions should a contact stud
`overlying both silicon (e.g. at a source/drain region)
`and SiO2 (e.g. at a ROX region) be required. The mate-
`rial forming this etch stop layer must have a good etch-
`ing selectivity with the phosphosilicate glass (PSG)
`layer 26 to be subsequently formed. A1203 is suitable,
`but intrinsic polysilicon is preferred, because it has not
`only the desirable high etch ratio with PSG, (about
`25:1), but it is easier to etch. The structure is cleaned
`again in two steps: first, using the Piranha clean fol-
`lowed by a clean in an H20/HCl/I-I202 (5:l:l) acidic
`solution, (hereinafter referred to as a I-lung B clean),
`then rinsed. The PSG layer 26 is now deposited confor-
`mally at 400° C., using a SiH4/PI-I3 gas with N2 as the
`carrier gas in a APCVD reactor to reach a thickness of
`900 nm. Optionally, a 200 nm thick intermediate pyro-
`litic SiO2 layer (not shown) can be inserted between
`intrinsic polysilicon layer 25 and PSG layer 26 to pro-
`tect the intrinsic polysilicon layer 22 from the phospho-
`rous dopants contained in the PSG layer 26. The depo— '
`sition is achieved in a PECVD tool, at 440‘ C. in an
`02/Sil-I4/N2 ambient. Next, the PSG layer 26 is chem-
`mech polished for fine planarization using a solution of
`colloidal SiO2 in water, (e.g. the slurry referenced SC]
`sold by SPEAR CARBO). After polishing, the remain-
`ing thickness is 600 nm. This step is followed by a post-
`clean in a SVG double-sided brush cleaner.
`After a new two-step cleaning a mentioned above,
`the process continues with the deposition of a PECVD
`SiO2 layer 27. The purpose of this layer is to act as a
`diffusion barrier layer in blocking the out-diffusion of
`the phosphorous dopants contained in the PSG layer
`into ‘the upper layer of polysilicon to be subsequently
`formed. This step is completed using a standard
`PECVD tool. The desired thickness of layer 27 is about
`2CD nm. Should a non contaminating passivating and
`planarizing dielectric material be used, e.g. quartz, the
`need of layer 27 could be eliminated. Quartz is appropri-
`ate, but results in an expensive process. Organic materi-
`als, such as polyimide, are also appropriate but behave
`badly in hot processing steps. Finally, phosphosilicate
`glass (PSG) is the preferred material although it necessi-
`tates an etch stop layer and at least two diffusion barrier
`layers. The wafer is then annealed in a furnace at 750’
`C. during ll-I in an N2 ambient. The resulting structure
`
`

`
`5,100,817
`
`9
`is shown in FIG. 5. This terminates the list of elements
`formed during the FEOL processing steps.
`2) At this point of the process, the step of forming
`first stud openings is now carried out. After a new two-
`step cleaning, a photoresist adhesion promoter such as
`HMDS is applied onto the structure (prebake time 7
`mn). then a standard photoresist, (e.g. the e-MERCK
`resin), is applied and baked. After alignment, the resist is
`exposed to UV light through a mask and developed to
`produce an in-situ resist mask (not shown) having the
`desired configuration. First stud openings, generically
`referenced 28, are formed by etching first the PECVD
`diffusion barrier layer 27 then, the thick PSG planarized
`layer 26 (and the optional pyrolitic Si