`571-272-7822
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`Paper 6
`Entered: August 29, 2016
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN
`MODULE TWO LLC & CO. KG,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-01311
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
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`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
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`IPR2016-01311
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`I. INTRODUCTION
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`Qualcomm Incorporated, Globalfoundries Inc., Globalfoundries U.S.
`Inc., Globalfoundries Dresden Module One LLC & Co. KG, and
`Globalfoundries Dresden Module Two LLC & Co. KG (collectively,
`“Petitioner”) filed a Petition (Paper 3, “Pet.”), requesting an inter partes
`review of claims 1–7 (the “challenged claims”) of U.S. Patent No. 6,784,552
`B2 (Ex. 1001, “the ’552 patent”) owned by DSS Technology Management,
`Inc. (“Patent Owner”). 35 U.S.C. § 311. Petitioner also timely filed a
`Motion for Joinder (Paper 4, “Mot. for Joinder”) of this proceeding with
`Intel Corporation v. DSS Technology Management, Inc., IPR2016-00287
`(“Intel IPR2016-00287”), which is the subject of a Decision to Institute
`entered on June 8, 2016. Petitioner represents that the instant Petition “is
`identical to the petition in [Intel IPR2016-00287].”1 Mot. for Joinder 6. We
`have jurisdiction under 37 C.F.R. § 42.4(a) and 35 U.S.C. § 314, which
`provides that an inter partes review may not be instituted unless the
`information presented in the Petition “shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” Having considered the arguments and the
`associated evidence presented in the Petition, for the reasons described
`below, we institute inter partes review of claims 1–7.
`
`1 We understand Petitioner to mean identical in all substantive matters, as
`the identity of the parties is different. Petitioner also acknowledges that it
`relies on the testimony of a different expert than the expert witness in Intel
`IPR2016-00287, but states that the testimony is essentially the same. Mot.
`for Joinder 4, 6.
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`A. Real Parties In Interest
`Petitioner Qualcomm Incorporated, Globalfoundries Inc.,
`Globalfoundries U.S. Inc., Globalfoundries Dresden Module One LLC &
`Co. KG, Globalfoundries Dresden Module Two LLC & Co. KG identifies
`itself as real parties-in-interest. Pet. 7.
`
`B. Related Proceedings
`Petitioner states that Patent Owner has asserted the ’552 patent in the
`following patent infringement cases: DSS Tech. Mgmt., Inc. v. Intel Corp.,
`Case No. 6:15-cv-130-JRG (E.D. Tex.); DSS Tech. Mgmt., Inc. v. Samsung
`Elec. Co., Ltd., Case No. 6:15-cv-690 (E.D. Tex.); DSS Tech. Mgmt., Inc. v.
`SK Hynix, Inc., Case No. 6:15-cv-691 (E.D. Tex.); and DSS Tech. Mgmt.,
`Inc. v. Qualcomm, Inc., Case No. 6:15-cv-692 (E.D. Tex.). Pet. 7.
`Petitioner notes that it has filed a separate petition for inter partes
`review of claims 8–12 of the ’552 patent. Id. at 8. That proceeding has been
`designated IPR2016-01314. The ’552 patent is also the subject of Samsung
`Elec. Co., Ltd. v. DSS Tech. Mgmt., Inc., Case IPR2016-00782, as well as
`the following instituted trial proceedings: Intel Corp. v. DSS Tech. Mgmt.,
`Inc., Cases IPR2016-00287 and IPR2016-00288; SK Hynix, Inc. v. DSS
`Tech. Mgmt., Inc., Case IPR2016-00192. Id. at 7–8.
`
`C. The ’552 Patent
`The ’552 patent describes a process of semiconductor device
`fabrication and a structure of a semiconductor device having “substantially
`rectangular” lateral insulating spacers adjacent to gate electrodes. Ex. 1001,
`Abstract. The ’552 patent defines the term “substantially rectangular” to
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`mean that “a side of the spacer has an angle relative to the substrate surface
`of more than 85°.” Id. at col. 8, ll. 40–42. Figure 4(D) of the ’552 patent is
`reproduced below.
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`Figure 4(D) illustrates a cross-sectional view of a series of gates 415 (also
`called conducting layers or polysilicon layers) completely encapsulated in
`insulating material 420, e.g., TEOS (tetraethyl orthosilicate glass), where
`spacers 435 of the insulating material adjacent to the gates have substantially
`rectangular profiles. Id. at col. 9, ll. 9–13; col. 11, ll. 40–46. As shown in
`Figure 4(D), gates 415 are insulated from sources or drains 405 by insulating
`dielectric layers 410. See id. at col. 10, ll. 49–50. The ’552 patent describes
`a process of making high quality contacts to the sources or drains, such as
`“self-aligned” contacts, by etching structures over substrate 400 and sources
`or drains 405. Id. at col. 7, ll. 19–22; col. 8, ll. 4–6.
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`Figure 4(I) of the ’552 patent is reproduced below.
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`Figure 4(I) illustrates additional structures deposited and etched over the
`structure described in Figure 4(D), such as second dielectric layer 440
`(called etch stop layer), blanket layer 450, and photoresist mask layer 455.
`Id. at col. 9, ll. 33–39; col. 11, ll. 63–65; col. 12, ll. 34–42. According to the
`’552 patent, etch stop layer 440, e.g., silicon nitride layer 440, depicted in
`Figure 4(I) is distinct or different from the underlying TEOS insulating
`layer. Id. at col. 12, ll. 10–11. The etch stop layer protects the underlying
`TEOS layer when blanket layer 450 made of BPTEOS2 is etched away to
`create contact openings 460 and 465 above source or drain 445. See id. at
`col. 12, ll. 36–42; col. 4, ll. 41–59.
`A second etch is then performed to remove etch stop layer 440
`covering source or drain 445 in contact openings 460 and 465. Id. at col. 12,
`ll. 48–52; col. 7, ll. 43–45. The ’552 patent describes that the second etch is
`“almost completely anisotropic,” which means that the etchant etches in the
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`2 BPTEOS is an acronym for borophosphosilicate tetraethyl orthosilicate
`glass. See Ex. 1001, col. 11, ll. 6–7.
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`vertical direction, or perpendicular relative to the substrate surface. Id. at
`col. 7, ll. 45–48; col. 12, ll. 55–58. Hence, the etch removes the etch stop
`material covering the area of the contact openings or contact regions 460 and
`465, but does not significantly etch the etch stop material adjacent to the
`spacer portions 435. Id. at col. 7, ll. 53–55; col. 12, ll. 58–61. Figures 4(J)
`and 4(K) of the ’552 patent are reproduced below.
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`Figures 4(J) and 4(K) illustrate the structure of the semiconductor device of
`the ’552 patent after the second etch for removing the etch stop layer from
`the contact regions 460 and 465 is completed. As shown in Figures 4(J) and
`4(K), due to the anisotropic or vertical nature of the second etch, only a
`small portion, i.e., portion 475, of the TEOS spacer portion 435 is removed
`during the etch. Id. at col. 13, ll. 6–9. Of primary significance, according to
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`the ’552 patent, the spacer portion 435 of the TEOS insulating layer 420
`retains its substantially rectangular profile, in contrast to the conventional
`prior art method which transforms a substantially rectangular spacer into a
`sloped spacer. Id. at col. 13, ll. 9–10; col. 7, ll. 48–51; col. 5, ll. 4–14.
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`D. Illustrative Claim
`Claim 1 is illustrative of the challenged claims and is reproduced
`below:
`1. A structure, comprising:
`(a) a conductive layer disposed over a substrate;
`(b) a first insulating layer on the conductive layer:
`(c) a contact region in said first insulating layer;
`(d) at least one insulating spacer in the contact region adjacent
`to the first insulating layer; and
`(e) an etch stop material over said first insulating layer and
`adjacent to the insulating spacer, the etch stop material being a
`different material from the insulating spacer,
`wherein a side of the insulating spacer has an angle relative to
`the substrate surface that is either a right angle or an acute angle
`of more than 85°.
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`E. Asserted Grounds of Unpatentability
`Petitioner asserts the following grounds of unpatentability (Pet. 9–10):
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`Claim(s) Challenged Statutory Basis
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`Ground
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`1, 2, 4–7
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`§ 102(b)
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`Anticipated by Heath3
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`3 Ex. 1003, U.S. Patent No. 4,686,000 (Aug. 11, 1987) (“Heath”).
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`Claim(s) Challenged Statutory Basis
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`3
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`1, 2, 4–7
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`3
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`Ground
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`Obvious over Heath, Hawley,4 and
`Chappell5
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`Obvious over Heath and Dennison6
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`Obvious over Heath, Dennison,
`Hawley, and Chappell
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`II. ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`Petitioner states that the instant Petition is substantially identical to the
`petition in Intel Corporation v. DSS Technology Management, Inc., which
`was filed December 8, 2015 and assigned Case No. IPR2016-00287 (Intel
`IPR2016-00287). Pet. 1. Based on the claims identified in the Petition and
`on the representations in Petitioner’s Motion for Joinder, we understand
`Petitioner to represent that the instant Petition is identical in substance to the
`petition filed in Intel IPR2016-00287, in which Intel challenged claims 1–7
`of the ’552 patent. Id.; Mot. for Joinder 6. Petitioner also acknowledges
`that it relies on the testimony of a different expert than the expert witness in
`Intel IPR2016-00287, but states that the testimony is essentially the same.
`Mot. for Joinder 4, 6. Thus, we understand that Petitioner challenges the
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`4 Ex. 1004, European Patent Application No. 0592078 A1 (Apr. 13, 1994)
`(“Hawley”).
`5 Ex. 1005, U.S. Patent No. 5,541,427 (July 30, 1996) (“Chappell”).
`6 Ex. 1006, U.S. Patent No. 5,338,700 (Aug. 16, 1994) (“Dennison”).
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`claims of the ’552 patent on the same grounds on which we instituted inter
`partes review in Intel IPR2016-00287.
`We incorporate by reference our decision in Intel IPR2016-00287 and
`institute inter partes review in this proceeding on the same grounds, for the
`same reasons.
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`III. SUMMARY
`For the reasons discussed above, on the current record we are
`persuaded that Petitioner has demonstrated a reasonable likelihood that it
`will prevail in the following challenges to patentability:
`Claims 1, 2, and 4–7 as anticipated under 35 U.S.C. § 102(b) by
`Heath; and
`Claim 3 as obvious under 35 U.S.C. § 103(a) over the combination
`Heath, Hawley, and Chappell.
`Any discussion of facts in this Decision are made only for the
`purposes of institution and are not dispositive of any issue related to any
`ground on which we institute review. The Board has not made a final
`determination as to the patentability of any of the challenged claims. The
`Board’s final determination will be based on the record as fully developed
`during trial.
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`IV. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that pursuant to 35 U.S.C. § 314, an inter partes review is
`hereby instituted as to claims 1–7 of the ʼ552 patent on the following
`grounds:
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`1. Claims 1, 2, and 4–7 as anticipated under 35 U.S.C. § 102(b) by
`Heath; and
`2. Claim 3 as obvious under 35 U.S.C. § 103(a) over the combination
`Heath, Hawley, and Chappell;
`FURTHER ORDERED that no other ground of unpatentability
`alleged in the Petition for any claim is authorized for this inter partes
`review;
`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial, the trial
`commencing on the entry date of this Decision; and
`FURTHER ORDERED that the trial will be conducted in accordance
`with the Scheduling Order entered in Intel IPR2016-00287.
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`PETITIONER:
`David M. O’Dell
`David L. McCombs
`HAYNES AND BOONE, LLP
`david.odell.ipr@haynesboone.com
`david.mccombs.ipr@haynesboone.com
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`PATENT OWNER:
`Andriy Lytvyn
`Anton J. Hopen
`Nicholas Pfeifer
`Smith & Hopen, P.A.
`andriy.lytvyn@smithhopen.com
`anton.hopen@smithhopen.com
`nicholas.pfeifer@smithhopen.com
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