United States Patent
`[11] Patent Number:
`5,374,836
`_
`Vmal et a],
`[45] Date of Patent:
`Dec. 20, 1994
`
`
`[191
`
`=1:
`
`USOO5374836A
`
`\l\:I.izu1no ...............................
`lfla .. . ... . . ..
`.. . ..
`,
`,
`257/336
`3/1993 Stevens
`5,192,990
`
`3/1993 Vinal ................................. .. 257/268
`5,194,923
`FOREIGN PATENT DOCUMENTS
`
`.
`.1/1983 ‘European Pat. Off.
`0070744
`(List continued on next page.)
`
`OTHER PUBLICATIONS
`
`Characteristics of P—Channel MOS Field Effect Transis-
`tors with Ion-Implanted Channels, Hswe, M. et al.,
`Solid—State Electronics, vol. 15, pp. 1237-1243, 1972.
`(List continued on next page.)
`
`firi’?4tarytEExami4er'_‘2:4i13::tm D'AL4:4é-kins
`_
`5515 0”
`xa"””9""_ 0
`De)’
`-
`OWCTS
`Attorney, Agent, or Fzrm—Bell, Seltzer, Park & Gibson
`
`ABSTRACT
`[57]
`includes an injcctof region
`current
`A
`of the same conductivity type as the Fermi-Tub region
`and the source and drain regions, located adjacent the
`source region and facing the drain region. The injector
`region is preferably doped at a doping level which is
`:1t::‘;:.:‘..:%a?.:%.‘2.13:1:61:11:55.1;*;.1;%.°;°:;.:’;r:;::’:..‘:f
`tration of the source region. The injector region con-
`trols thedepthiofi the carriers injected into the channel
`and maximizes injection of carriers into the channel at a
`predetermined depth below the gate. The injector re-
`gion may also extend to the Fermi-tub depth to decrease
`bottom leakage current. Alternatively a bottom leak-
`t
`t
`I
`.
`b
`’ d t
`d
`age curren con ro region may _e use
`o
`ecrease
`bottom leakage onrrent. Lower pm_ch-off voltage. and
`increased saturation current are obtained by providing a
`gate sidewall spacer which extends from adjacent the
`source injector region to adjacent the sidewall of the
`ptcillysilifion gate elegtroldle of the Itiermi-F.ET.I'lt'he tgate
`S1 ewa
`spacer pre'era_ y comprises an insu a or ‘ av-
`ing permittivity which is greater than the permittivity
`of the gate insulating layer.
`
`46 Claims, 28 Drawing Sheets
`
`INTEL 1009
`
`. 1
`
`[54] HIGH CURRENT FERMI THRESHOLD
`FIELD
`[75]
`Inventors: Albert W. Vinal, Cary; Michael W.
`'
`,
`.C.
`D°'“‘°"’ Ralmgh b°th °f N
`'I'hnnderbird Technologies, Inc.,
`Research Triangle Park’ N-C.
`_
`_
`The portion of the term of this patent
`subsequent to Mar. 16, I993 has been
`disclainied.
`
`[73] Assignee:
`
`[ * ] Notice:
`
`[2]] Appl. No.: 37,636
`
`[22] Filed:
`
`Feb. 23, 1993
`
`[63]
`
`[51]
`
`Related U.S. Application Data
`Continuation-in-part of Ser. No. 977,689, Nov. 18,
`1992, which is a continuation of Ser. No. 826,939, Jan.
`28, 1992, Pat. No. 5,194,923.
`
`Int. c1.s ........................................... .. H01L 29/10
`US. Cl. ....................................
`257/403; 257/403; 257/900
`Of Search ...............
`340, 344,
`357/345: 403: 403: 335: 900: 404
`
`.
`
`'
`
`we we
`U-S- PATENT DOCUMENTS
`Re. 32,800 12/1988 Han et al.
`.
`3,653,978
`4/1972 Robinson et al.
`3.789.504 2/1974 Jaddam -
`3v372r491
`3/1975 Ha“5°“ C‘ 31-
`4042’945
`8/1977 Lin et 4]‘
`‘
`4,l08,686
`8/1978 Jacobus, Jr.
`.
`4,274,105
`6/1981 Cmwder at at _
`4,491,307
`1/1985 Hoover ............................... 331/111
`4,697,198
`9/1987 Komori et al.
`.
`-
`4,737,471 4/1988 Shirato Ct 81-
`4,771,012 9/I988 Yabu et al.
`.......................... 257/344
`giznzwta at 31‘
`‘
`6/1989 Noguchi .
`4,841,346
`4’899’202 2/1990 Blake et at _
`4,907,048
`3/1990 Huang .
`4,928,156 5/I990 Alvis et al.
`.
`4,984,043
`1/I99] Vinal .
`4,990,974 2/1991 Vinal
`.
`4,994,872 2/199] Nisliizawa et al.
`
`

`
`Page 2
`
`
`5,374,836
`
`FOREIGN PATENT DOCUMENTS
`0073623
`3'/1983 European Pat. Off.
`.
`0274278
`7/1988 European Pat. Off.
`.
`55-87481
`7/1980 Japan ................................... 257/403
`55-87483
`7/1980 Japan.
`56-91473
`7/1981 Japan .
`57-10268
`1/1982 Japan.
`59-29460 2/1984 Japan .
`61-53775
`3/1986 Japan ................................. .. 257/900 ‘
`61-160975
`7/1986 Japan.
`62-248255 10/1987 Japan .
`63-53975
`3/1988 Japan.
`1097139
`4/1987 U.S.S.R.
`
`.
`
`OTHER PUBLICATIONS
`
`The Junction MOS (JMOS) Transistor-A High Speed
`Transistor for VLSI. Sun, E. et al., IEEE, pp. 791-794,
`1980.
`
`Optimization of Sub-Micron P-Channel FET Structure
`Chiang, S. et a1., IEEE, pp. 534-535, 1983.
`
`Gate Material Work Function Considerations for 0.5 Illi-
`cron CMOS, Hellenius, S. J. et a1., IEEE, pp. 147-150,
`1985.
`
`A Normally-Off Type Buried Channel MOSFET for
`VLSI Circuits, Nishiuchi, K. et al., IEDM Technical
`Digest, 1979, pp. 26-29.
`Ultra-High Speed CMOS Circuits in Thin SIMOX Films,
`A. Kamgar et a1., IEDM vol. 89, pp. 829-832, 1989.
`Fabrication of CMOS on Ultrathin S01 Obtained by Epi-
`taxial Lateral Overgrowth and Chemical-Mechanical
`Polishing, ‘G. Shahidi et a1., IEDM vol. 90, pp. 587-590,
`1990.
`
`Submicron MOSFET Structure for Minimizing Channel
`Hot-Electron Injection, Takeda E., et a1., 1981 Sympo-
`sium on VLSI Technology, Hawaii (Sep. 1981), Dig.
`Tech. Papers pp. 22-23.
`A New Half-Micrometer P-Channel MOSFET with Efi‘i-
`cient Punchthrough Stops, Odanaka S., et aI., IEEE
`Transactions on Electron Devices, vol. ED—33, No. 3,
`Mar., 1986, pp. 317-321.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 1 of 28
`
`5,374,836
`
`1.
`
`FIG.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 2 of 28
`
`5,374,836
`
`""lIIII||||Illl
`
`lwifiiiiiilllumlnlll
`
`
`|l|ll""||lllIl|l|IllII
`mI|II|IiiiiiIr"========!
`
`'HuIIIlii-
`
`
`DEPTH(pm)
`
`FIG.2B.
`
`
`lllllllllllllllllllllllllllllllllllllllllllllll
`
`d
`|l|||||ll||||||lillilllllflllllllllll
`llllllllllllllll|l||l|||.I!!!l|!1..!!!!!!!!!!!!!3
`DEPTH(pm)
`
`
`illlllllllllllllllllllll I!"
`
`W, AIIIIIIIIIIIIIIII
`
`
`mmgganlllllll ||||Ii||||||Il||||||I
`
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`
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`1020
`
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`
`
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`
`3722REGION21r"Ir‘L-1r—““1r“L"1r““—-“"‘“‘-"“‘"1
`
`
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 3 of 28
`
`5,374,836
`
`:1|||||||1I1...!!!|I|1l||||lIlllllllll
`
`
`
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`
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`38
`
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`
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`
`
`
`0.8ARBITRARYDISTANCE(W)
`
`0.4
`
`
`
`
`
`
`
`1016
`
`FIG.2C.
`
`-ii
`
`36
`
`REGION
`
`C57.
`
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`1O2Or—EE——I
`
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`
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`
`03
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`
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`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 4 of 28
`
`5,374,836
`
`FIG. 3.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994*
`
`Sheet 5 of 28
`
`5,374,836
`
`_.C
`
`3,3.9zmmmaozo:
`
`<m:»<m
`
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`
`OO86
`
`OO
`
`,3.5
`
`
`
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`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 6 of 28
`
`5,374,836
`
`
`
`155-7
`
`so
`
`10
`75
`GATE INSULATI
`
`175_
`150
`125
`LAYER THICKNESS, A
`
`200
`
`<O
`
`FIG. 4C.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 7 of 28
`
`5,374,836
`
`1800
`
`,5OO Mwwwmwwgwmwmwwgu
`
`M) S o O
`
`
`
`
`
`DRAINCURRENT(}JA/}J
`
`on O O
`
`300
`
`DRAIN BIAS (vows)
`
`FIG. 5A,
`
`

`
`U.S. Patent
`
`Dec. 20, 1994 >
`
`Sheet 8 of 28
`
`5,374,836
`
`1800
`
`M) :13 O O
`
`
`
`
`
`DRAINCURRENT(}.IA/)1
`
`0) o ,0
`
`300
`
`DRAIN BIAS (vows)
`
`FIG. 5B.
`
`

`
`U.S. Patent
`
`Dec.20, 1994
`
`Sheet 9 of 23
`
`5,374,836
`
`1800
`
`M) F3 0 O
`
`
`
`
`
`DRAINCURRENT()JA/)1
`
`(D O O
`
`300
`
`DRAIN BIAS (vows)
`
`FIG. 5C.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 10 of 28
`
`5,374,836
`
`=1.o112mV/D=5.o115mV/D\
`
`> E
`
`00
`o
`
`0'
`II
`§’ Vd Vd
`
`
`
`GATEBIAS(vows)
`
`FIG.6/-\.
`
`DRAIN CURRENT IN AMPERES (LOG SCALE)
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 11 of 28
`
`5,374,836
`
`
`
`
`
`GATEBIAS(VOLTS)
`
`Q_
`
`.|
`,O
`
`SLOPEI93m_V/DECADE=1.o95mV/DECADE=5.o105mV/DECADE
`f) Vd=O.1 Vd Vd
`
`IU
`
`)
`LIJ
`CE
`
`II
`
`-
`CD
`
`3(
`
`DRAW CURRENT lN AMPERES (LOG SCALE)
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 12 of 28
`
`5,374,836
`
`800
`
`U'|(}JAg2JM)\l888
`
`DRAINCURRENT, L»! o o
`
`-P- O O
`
`0
`
`i
`
`3
`.5.
`DRAIN BIAS,
`
`«S,
`(VOLTS)
`
`5
`
`5
`
`FIG. 7.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 13 of 28
`
`5,374,836
`
`FIG. 8A.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 14 of 28
`
`5,374,836
`
`FIG. 8B.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 15 of 28
`
`5,374,836
`
`FIG. 8C.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 16 of 23
`
`%
`
`5,374,836
`
`FIG.9A.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`«
`
`Sheet 17 of 28
`
`5,374,836
`
`FIG.9B.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 18 of 28
`
`5,374,836
`
`FIG.WOB.
`
`Of.
`
`ARBlTRA
`
`
`
`FIG.10A.
`
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`1*
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`F
`
`
`
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`
`21
`
`REGION
`
`51
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`
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`
`9
`53
`DOPING DENSITY (cm'3)
`
`
`
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`
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`
`REGION
`
`21
`
`22
`
`26
`
`

`
`U.S. Patent
`
`Dec. 20, 1994 ,
`
`V
`
`Sheet 19 of 28
`
`5,374,836
`
`lllllllllillllllll !!iI|||I|||l!l|lvllllllllllllllll
`
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`
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`
`NET DOPlNG DENSITY (cm.‘3)
`
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`‘CD
`
`
`
`
`
`21
`
`REGION
`
`37
`
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`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`%
`
`Sheet 20 of 28
`
`5,374,836
`
`
`
`ICILOGOFDRNNCURRENT
`
`GATE VOLTAGE
`
`HQ. 11.
`
`
`
`0.4
`
`0.6
`
`0.8
`CHANNEL LENGTH, )4
`FIG. 13.
`
`1
`
`1.2
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 21 of 28
`
`5,374,836
`
`
`
`DEPLETED
`
`SUBSTRATE
`
`21
`
`BOTTOM EDOE OF SUBSTRATE
`DEPLETION REGION
`
`FIG. T2/\.
`
`32
`
`_K—Hl‘_:_
`
`’N+ 3_ §_"YL N+§'§g2 #2
`
`DEPLETION REGION
`
`BOTTOM EDGE OF SUBSTRATE
`
`FIG. 12B.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994 7
`
`Sheet 22 of 28
`
`5,374,836
`
`
`
`0.4
`
`0.8
`0.6
`CHANNEL LENGTH, }J
`
`1
`
`”
`
`1.2
`
`FIG. N14/A.
`
`FIG. 14B.
`
`

`
`U.S., Patent
`
`Dec. 20, 1994
`
`Sheet 23 of 28
`
`5,374,836
`
`12OMhz
`
`1ooMhz
`
`FIG. 15.
`
`SECONDS
`DELAYTlME—PlCO
`
`
`04
`
`as
`
`1
`as
`CHANNEL LENGTH,p
`FIG. 16.
`
`L2
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 24 of 28
`
`5,374,836
`
`ei
`
`TOX
`
`
`--------
`
` 8
`
`CHANNEL
`
`F|G. T7.
`
`Ndo
`
`Wdn Wdn
`
`FIG. 19.
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 25 of 28
`
`5,374,836
`
`18
`
`15.5
`
`16
`
`0
`
`200
`
`600
`400
`DEPTH A
`
`FM}. 20.
`
`800
`
`4000
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 26 of 28
`
`5,374,836
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 27 of 28
`
`5,374,836
`
`

`
`U.S. Patent
`
`Dec. 20, 1994
`
`Sheet 23 of 28
`
`5,374,836
`
`
`
`
`
`
`L‘-’ ‘f'0._.._.."'0——
`3 £_._...”"""'_=:- 0-1
`0
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`
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`
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`
`
`
`
`
`
`
`0
`
`
`1800
`
`400
`
`1200
`800 _
`DEPTH (AN GSTROM 8)
`
`FIG. 23.
`
`2000
`
`

`
`1
`
`5,374,836
`
`2
`
`HIGH CURRENT FERMI THRESHOLD FIELD
`EFFECT TRANSISTOR
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation-in-part of copend-
`ing application Ser. No. 07/977,689, filed Nov. 18, 1992,
`which is itself a continuation of application Ser. No.
`07/826,939, filed Jan. 28, 1992, now U.S. Pat. No.
`5,194,923. The disclosures of both of these prior appli-
`cations are hereby incorporated herein by reference.
`FIELD OF THE INVENTION
`
`This invention relates to field effect transistor devices
`and more particularly to integrated circuit field effect
`transistors which are capable of producing high cur-
`rents.
`
`5
`
`10
`
`15
`
`BACKGROUND OF THE INVENTION
`
`20
`
`Field effect transistors (FET) have become the domi-
`nant active device for very large scale integration
`(VLSI) and ultra large scale integration (ULSI) applica-
`tions, such as logic devices, memory devices and micro-
`processors, because the integrated circuit FET is by
`nature a high impedance, high density, low power de-
`vice. Much research and development activity has fo-
`cused on improving the speed and integration density of
`FETS, and on lowering the power consumption thereof.
`A high speed, high performance field effect transistor
`is described in U.S. Pat. Nos. 4,984,043 and 4,990,974,
`both by coinventor Albert W. Vinal, both entitled
`Fermi Threshold Field Ejfect Transistor and both as-
`signed to the assignee of the present invention. These
`patents describe a metal oxide semiconductor field ef-
`fect transistor (MOSFET) which operates in the en-
`hancement mode without requiring inversion, by set-
`ting the device’s threshold voltage to twice the Fermi
`potential of the semiconductor material. As is well
`known to those having skill in the art, Fermi potential is
`defined as that potential for which an energy state in a
`semiconductor material has a probability of one-half of
`being occupied by an electron. As described in the
`above mentioned Vinal patents, when the threshold
`voltage is set to twice the Fermi potential, the depen-
`dence of the threshold voltage on oxide thickness, chan-
`nel length, drain voltage and substrate doping is sub-
`stantially eliminated. Moreover, when the threshold
`voltage is set to twice the Fermi potential, the vertical
`electric field at the substrate face between the oxide and
`channel is minimized, and is in fact substantially zero.
`Carrier mobility in the channel is thereby maximized,
`leading to a high speed device with greatly reduced hot
`electron effects. Device performance is substantially
`independent of device dimensions.
`Notwithstanding the vast improvement of the Fermi
`threshold FET compared to known FET devices, there
`was a need to lower the capacitance of the Fermi-FET
`device. Accordingly, in U.S. patent application Ser.
`Nos. 07/826,939 and 07/977,689, both by coinventor
`Albert W. Vinal, and both entitled Fermi Threshold
`Field Eflect Trarzsistor With Reduced Gate and Diffusion
`Capacitance, a Fermi-FET device is describedwhich
`allows conduction carriers to flow within the channel at
`a predetermined depth in the substrate below the gate,
`without requiring an inversion layer to be created at the
`surface of the semiconductor in order to support carrier
`conduction. Accordingly,
`the average depth of the
`
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`35
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`40
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`45
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`50
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`55
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`60
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`65
`
`channel charge requires inclusion of the permittivity of
`the substrate as part of the gate capacitance. Gate ca-
`pacitance is thereby substantially reduced.
`As described in the aforesaid patent applications, the
`low capacitance Fermi-FET is preferably implemented
`using a Fermi-tub region having a predetermined depth
`and a conductivity type opposite the substrate conduc-
`tivity type and the same conductivity type as the drain
`and source. The Fermi-tub extends downward from the
`substrate surface by a predetermined depth, and the
`drain and source diffusions are formed in the Fermi-tub
`within the tub boundaries. The Fermi-tub forms a uni-
`junction transistor, in which the source, drain, channel
`and Fermi-tub are all doped the same conductivity type,
`but at different doping concentrations. A low capaci-
`tance Fermi-FET is thereby provided. The low capaci-
`tance Fermi-FET including the Fermi-tub will be re-
`ferred to herein as a “low capacitance Fermi-FET” or a
`“Tub-FET”.
`
`Notwithstanding the vast improvement of the Fermi-
`FET and the low capacitance Fermi-FET compared to
`known FET devices, there is a continuing need to in-
`crease the current per unit channel width, which is
`produced by the Fermi-FET device. Higher current
`Fermi-FET devices will allow even greater integration
`density, and/or much higher speeds for logic devices,
`memory devices, microprocessors and other integrated
`circuit devices.
`
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the invention to provide an
`improved Fermi threshold field effect transistor (Fermi-
`FET).
`It is another object of the invention to provide a
`Fermi-FET which is capable of producing very high
`current per unit channel width.
`These and other objects are provided, according to
`the present invention, by a Fermi-FET which includes
`an injector region of the same conductivity type as the
`Fermi-tub region and the source region, adjacent the
`source region and facing the drain region. The injector
`region is preferably doped at a doping level which is
`intermediate to the relatively low doping concentration
`of the Fermi-tub and the relatively high doping concen-
`tration of the source. The injector region controls the
`depth of the carriers injected into the channel and en-
`hances injection of carriers in the charmel, at a predeter-
`mined depth below the gate.
`Preferably,
`the source injector region is a source
`injector tub region which surrounds the source region.
`In other words, the source injector tub region is formed
`within the Fermi-tub region, and the source is prefera-
`bly formed within the source injector tub region. Simi-
`larly, a drain injector tub region is also formed within
`the Fermi-tub region and the drain region is preferably
`formed within the drain injector tub. The source region
`and drain regions may also extend deeper into the sub-
`strate than the respective source injector tub region and
`drain injector tub region. The source injector tub region
`and drain injector tub region are of the same conductiv-
`ity type as the source, drain and Fermi-tub, and are
`preferably doped at a concentration which is intermedi-
`ate to that of the Fermi-tub and the source and drain
`regions.
`According to another aspect of the invention, lower
`pinch-off voltage and increased saturation current are
`obtained by providing a gate sidewall spacer which
`
`

`
`3
`extends from adjacent the source injector region to
`adjacent the gate electrode of the Fermi-FET. The gate
`sidewall spacer preferably comprises an insulator hav-
`ing permittivity which is greater than the permittivity
`of the gate insulating layer. For example, in typical field
`effect transistor devices, where the gate insulator is
`silicon dioxide, the gate sidewall spacer is preferably
`silicon nitride. The gate sidewall spacer also preferably
`extends from adjacent the drain injector region to adja-
`cent the gate electrode. The gate sidewall spacer typi-
`cally surrounds the gate electrode on the sidewall
`thereof.
`
`5,374,836
`
`4
`FIG. 4C graphically illustrates simulated gate capaci-
`tance versus gate insulating layer thickness for a Fermi-
`FET.
`
`FIG. 5A graphically illustrates simulated transistor
`drain current characteristics of a conventional 0.8 pm
`N-channel MOSFET.
`
`FIGS. 5B and 5C graphically illustrate simulated
`transistor drain current characteristics of a 0.8 pm N-
`channel high current Fermi-FET according to the pres-
`ent invention.
`
`FIGS. 6A and 6B graphically illustrate simulated
`bottom current and subthreshold leakage behavior for
`N-channel and P-channel high current Fermi-FETs
`respectively.
`FIG. 7 graphically illustrates simulated worst case
`comparisons of drain current versus drain bias for dif-
`ferent sidewall spacer structures in a high current Fer-
`mi-FET.
`
`10
`
`15
`
`The gate electrode of a Fermi-FET preferably in-
`cludes a polycrystalline silicon (polysilicon) layer on
`the gate insulating layer, and a conductor layer such as
`metal on the polysilicon layer. The polysilicon layer is
`preferably of opposite conductivity type from the
`source, drain and tub regions of the Fermi-FET. The
`gate sidewall spacer extends from the sidewall of the
`polysilicon layer onto the source and drain injection
`tubs. The gate sidewall spacer lowers the pinch-off
`voltage of the device and increases the saturation cur-
`rent of the device.
`
`20
`
`FIGS. 8A-8C illustrate enlarged cross-sections of the
`sidewall spacer structures which are graphically illus-
`trated in FIG. 7.
`FIG. 9A illustrates a cross-sectional view of a first
`embodiment of a short channel low leakage current
`The source and drain injector regions may be used in
`Fermi-FET according to the present invention.
`FIG. 9B illustrates a cross-sectional view of a second
`the Tub-FET structure to provide a high current Fer-
`mi-FET device. The source and drain injector regions
`embodiment of a short channel low leakage current
`are preferably used in combination with the gate side-
`Fermi-FET according to the present invention.
`wall spacer to provide a high current device with low
`FIGS. 10A and 10B graphically illustrate preferred
`pinch-off voltage.
`doping profiles and geometries for designing a 0.5 pm
`When short charmel FETs, for example FETs with
`channel low leakage current Fermi-FET of FIG. 9A.
`channel length of about 0.5 pm or less, are fabricated,
`FIGS. 10C and 10D graphically illustrate preferred
`bottom leakage current increases as a result of the drain
`doping profiles and geometries for designing a 0.5 pm
`field terminating in the source depletion region, to cause
`channel low leakage current Fermi-FET of FIG. 9B.
`drain induced injection. According to another aspect of
`FIG. 11 graphically illustrates basic subthreshold
`voltage-current behavior of a field effect transistor.
`the invention, bottom leakage current is reduced by
`extending the source and drain injector regions to the
`FIGS. 12A and 12B are enlarged cross-sectional
`depth of the Fermi-tub. Alternatively, a bottom leakage
`views of a field effect transistor illustrating drain in-
`duced injection.
`control region of the same conductivity type as the
`substrate may be provided.
`FIG. 13 graphically illustrates simulated theoretical
`limits for gate slew rate of a field effect transistor.
`The bottom leakage control region is doped at a high
`concentration relative to the substrate and extends
`FIGS. 14A and 14B graphically illustrate simulated
`across the substrate from between an extension of the
`frequency response of ring oscillators constructed using
`facing ends of the source and drain regions or source
`‘Fermi-FET designs with different diffusion capacitance
`and drain injector regions, and extends to both sides of 45 values.
`the Fermi-tub/substrate junction. High current, short
`FIG. 15 graphically illustrates simulated theoretical
`channel devices with low pinch-off voltage and low
`frequency limits for a ring oscillator using Fermi-FET
`leakage current are thereby provided.
`technology.
`It will be understood by those having skin in the art
`FIG. 16 graphically illustrates simulated inverter
`that the bottom leakage control region or extended
`delay time with only gate capacitive loading.
`injector regions may also be used in Tub-FETs having
`FIG. 17 illustrates an enlarged cross-sectional view of
`channel length which is greater than about 0.5 pm. The
`a distributed channel charge capacitor.
`bottom leakage current control region can also be used
`FIG. 18 schematically illustrates the transition of
`in a Tub-FET which does not include injector regions. 55 N-type doping concentration decreasing from a higher
`to a lower concentration.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`25
`
`30
`
`35
`
`FIG. 1 illustrates a cross-sectional view of an N-chan-
`nel high current Fermi-FET according to the invention.
`FIGS. 2A—2C graphically illustrate preferred doping 50
`profiles and geometries for the high current Fermi-FET
`of FIG. 1 having a 0.8 pm charmel.
`FIG. 3 illustrates an enlarged cross-sectional view of
`FIG. 21 illustrates an enlarged cross-sectional view of
`a portion of the high current Fermi-FET of FIG. 1.
`the electric field produced by the gate electrode in a
`FIGS. 4A and 4B graphically illustrate simulated 55 Fermi-FET transistor.
`drain saturation current for N-charmel and P-channel
`FIG. 22A graphically illustrates simulated carrier
`Fermi-FETs respectively, as a function of channel
`concentration as a function of depth for a typical Fermi-
`FET.
`length and gate insulating layer thickness.
`
`FIG. 19 schematically illustrates two differently
`doped N-type semiconductor regions forming an abrupt
`junction, and the electric field diagram therefor.
`FIG. 20 graphically illustrates simulated profiles of
`carrier injection as a function of depth for a Fermi-
`FET.
`
`

`
`5,374,836
`
`5
`FIGS. 22B and 22C graphically illustrate simulated
`carrier concentration as a function of depth in the chan-
`nel of a conventional MOSFET.
`FIG. 23 graphically illustrates simulated excess car-
`rier distribution injected into the source end of the
`channel and acquired at the drain end of a Fermi-FET.
`
`Where Yfis the depth of the conduction channel called
`the Fermi channel, esis the permittivity of the substrate,
`and B is the factor that determines the average depth of 65
`the charge flowing within the Fermi channel below the
`surface. ,8 depends on the depth dependant profile of
`carriers injected from the source into the channel. For
`
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`30
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`35
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`45
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`50
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`55
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`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`The present invention now will be described more
`fully hereinafter with reference to the accompanying
`drawings, in which preferred embodiments of the in-
`vention are shown. This invention may, however, be
`embodied in many different forms and should not be
`construed as limited to the embodiments set forth
`herein; rather, these embodiments are provided so that
`this disclosure will be thorough and complete, and will
`fully convey the scope of the invention to thoseskilled
`in the art. In the drawings, the thickness of layers and
`regions are exaggerated for clarity. Like numbers refer
`to like elements throughout.
`Before describing the high current Fermi threshold
`field effect transistor of the present invention, the Fermi
`threshold field effect transistor with reduced gate and
`diffusion
`capacitance
`of
`application
`Ser. Nos.
`07/826,939 and 07/977,689 (also referenced as the “low
`capacitance Fermi-FET” or the “Tub-FET” will first
`be described. A more complete description may be
`found in these applications, the disclosures of which are
`hereby incorporated herein by reference. After describ-
`ing the low capacitance Fenni-FET, the high current
`Fermi-FET of the present invention will be described as
`will the low leakage current short channel Fermi-FET.
`
`Fermi-FET With Reduced Gate and Diffusion
`Capacitance
`
`The following summarizes the low capacitance Fer-
`mi-FET including the Fermi-tub. Additional details
`may be found in application Ser. Nos. 07/826,939 and
`O7/977,689.
`Conventional MOSFET devices require an inversion
`layer to be created at the surface of the semiconductor
`
`in order to support carrier condugtion. The depth of the
`inversion layer is typically 100 A or less. Under these
`circumstances gate capacitance is essentially the permit-
`tivity of the gate insulator layer divided by its thickness.
`In other words, the channel charge is so close to the
`surface that effects of the dielectric properties of the
`substrate are insignificant in determining gate capaci-
`tance.
`
`Gate capacitance can be lowered if conduction carri-
`ers are confined within a channel region below the gate,
`where the average depth of the channel charge requires
`inclusion of the permittivity of the substrate to calculate
`gate capacitance. In general, the gate capacitance of the
`low capacitance Fermi-FET is described by the follow-
`ing equation:
`
`Cg =
`
`1
`
`Tax
`Yf
`/395 + 9:’
`
`(1)
`
`6
`the low capacitance Fermi-FET, ,8 :12. To, is the thick-
`ness of the gate oxide layer and e; is its permittivity.
`The low capacitance Fermi-FET includes a Fermi-
`tub region of predetermined depth, having conductivity
`type opposite the substrate conductivity type and the
`same conductivity type as the drain and source regions.
`The Feririi-tub extends downward from the substrate
`surface by a predetermined depth, and the drain and
`source diffusions are formed in the Fermi-tub region
`within the Fermi-tub boundaries. The preferred Ferrni-
`tub depth is the sum of the Fermi channel depth Yfand
`depletion depth Yo. A Fermi channel region with prede-
`termined depth Yf and width Z, extends between the
`source and drain diffusions. The conductivity of the
`Fermi channel is controlled by the voltage applied to
`the gate electrode.
`The gate capacitance is primarily determined by the
`depth of the Fermi channel and the carrier distribution
`in the Fermi channel, and is relatively independent of
`the thickness of the gate oxide layer. The diffusion
`capacitance is inversely dependant on the difference
`between [the sum of the depth of the Fermi-tub and the
`depletion depth Yo in the substrate] and the depth of the
`diffusions Xd. The diffusion depth is preferably the same
`depth as the Fermi channel. For deeper configurations,
`diffusion depth is less than the depth of the Fermi-tub,
`Yrub. The dopant concentration for the Fermi-tub re-
`gion is preferably chosen to allow the depth of the
`Fermi channel to be greater than three times the depth
`of an inversion layer within a MOSFET.
`Accordingly,
`the low capacitance Fermi-FET in-
`cludes a semiconductor substrate of first conductivity
`type having a first surface, a Fermi-tub region of second
`conductivity type in the substrate at the first surface,
`spaced apart source and drain regions of the second
`conductivity type in the Fermi-tub region at the first
`surface, and a channel of the second conductivity type
`in the Fermi-tub region at the first surface between the
`spaced apart source and drain regions. The channel
`extends a first predetermined depth (Yf) from the first
`surface and the tub extends a second predetermined
`depth (Y0) from the channel. A gate insulating layer is
`provided on the substrate at the first surface between
`the spaced apart source and drain regions. Source, drain
`and gate electrodes are provided for electrically con-
`tacting the source and drain regions and the gate insu-
`lating layer respectively.
`At least the first and second predetermined depths are
`selected to produce zero static electric field perpendicu-
`lar to the first surface at the first depth, upon application
`of the threshold voltage of the field effect transistor to
`the gate electrode. The first and second predetermined
`depths are also selected to allow carriers of the second
`conductivity type to flow from the source to the drain
`in the channel, extending from the first predetermined
`depth toward the first surface upon application of the
`voltage to the gate electrode beyond the threshold volt-
`age of the field effect transistor. The carriers flow from
`the source to the drain region beneath the first surface
`without creating an inversion layer in the Fermi-tub
`region. The first and second predetermined depths are
`also selected to produce a voltage at the substrate sur-
`face, adjacent the gate insulating layer, which is equal
`and opposite to the sum of the voltages between the
`substrate contact and the substrate and between the
`polysilicon gate electrode and the gate electrode.
`
`

`
`7
`When the substrate is doped at a doping density N5,
`has an intrinsic carrier concentration N; at temperature
`T degrees Kelvin and a permittivity es, and the field
`effect transistor includes a substrate contact for electri-
`cally contacting the substrate, and the channel extends a
`first predetermined depth Yf from the surface of the
`substrate and the Fermi-tub region extends a second
`predetermined depth Yo from the channel, and the Fer-
`mi-tub region is doped at a doping density which is a
`factor a times N5, and the gate electrode includes a
`polysilicon layer of the first conductivity type and
`which is doped at a doping density Np, the first prede-
`termined depth (Yf) is equal to:
`
`5
`
`10
`
`Yf =
`
`2e,
`qNsa
`
`[(7
`q
`
`(2)
`
`15
`
`where q is l.6>< 10-19 coulombs and K is l.38>< 10-23
`jou1es/“Kelvin. The second predetermined depth (Y0) is
`equal to:
`
`20
`
`2&4):
`‘qrvzrtfir ’
`
`Y0 =
`
`(3)
`
`25
`
`where 42, is equal to 2¢f+ KT/q lna, and 4:,/is the Fermi
`potential of the semiconductor substrate.
`
`High Current Fermi-FET Structure
`
`Referring now to FIG. 1, an N-channel high current
`Fermi-FET according to the invention is illustrated. It
`will be understood by those having skill in the art that
`a P-channel Fermi—FET may be obtained by reversing
`the conductivities of the N and P regions.
`As illustrated in FIG. 1, high current Fermi-FET 20
`is fabricated in a semiconductor substrate 21 having first
`conductivity type, here P-type, and including a sub-
`strate surface 21a. A Fermi-tub region 22 of second
`conductivity type, here N-type, is formed in the sub-
`strate 21 at the surface 210. Spaced apart source and
`drain regions 23 and 24, respectively, of the second
`conductivity type, here N-type, are formed in the Fer-
`mi-tub region 22 at the surface 211:. It will be under-
`stood by those having skill in the art that the source and
`drain regions may also be formed in a trench in the
`surface 21a.
`A gate insulating layer 26 is formed on the substrate
`21 at the surface 210 between the spaced apart source
`and drain regions 23 and 24, respectively. As is well
`known to those having skill in the art, the gate insulat-
`ing layer is typically silicon dioxide. However, silicon
`nitride and other insulators may be used.
`A gate electrode is formed on gate insulating layer 26,
`opposite the substrate 21. The gate electrode preferably
`includes a polycrystalline silicon (polysilicon) gate elec-
`trode layer 28 of first conductivity type, here P-type. A
`conductor gate electrode layer, typically a metal gate
`electrode layer 29, is formed on polysilicon gate elec-
`trode 28 opposite gate insulating layer 26. Source elec-
`trode 31 and drain electrode 32, typically metal, are also
`formed on source region 23 and drain region 24, respec-
`tively.
`A substrate contact 33 of first conductivity type, here
`P-type, is also formed in substrate 21, either inside Fer-
`mi-tub 22 as shown or outside tub 22. As shown, sub-
`strate contact 33 is doped