1709905
`
`VERIFICATION OF TRANSLATION
`
`I,
`
`Yukiko T. Buntin
`
`of
`
`1950 Roland Clarke Place
`
`Reston, VA 20191
`
`declare that I am well acquainted with both the Japanese and English languages, and that
`the attached is an accurate translation, to the best of my knowledge and ability, of
`Japanese Unexamined Patent Application Publication No. H09-64044, published March
`
`7,1997.
`
`I further declare that all statements made herein of my own knowledge are true and that
`all statements made on information and belief are believed to be true; and further that
`these statements were made with the knowledge that willful false statements and the like
`so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 1 8
`of the United States Code and that such willful false statements may jeopardize the
`validity of the above-captioned application or any patent issued thereon.
`
`Signature
`
`Yukiko T. Buntin
`
`Date
`
`3 - )- >ol'7
`
`{J709905 03037s20.DOC}
`
`Page 1 of 19
`
`IP Bridge Exhibit 2021
`TSMC v. IP Bridge
`IPR2016-01264
`
`

`

`
`
`(19) Japan Patent Office (JP)
`
`(12) Patent Publication (A)
`
`(11) Patent Publication No.
`
`JP H09-64044
`
`(43) Publication Date: March 7, 1997
`
`(51) Intl. Cl.6
`
`H01L
`
`21/3205
`
`ID No.
`
`PTO Ref. No.
`
`F1
`
`
`
`Technology Indication Area
`
`
`
`
`
`
`
`
`
`21/28
`
`301
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`H01L 21/88
`
`21/28
`
`21/88
`
`
`
`
`
`R
`
`301T
`
`M
`
`Request for Examination Not Requested
`
`No. of Claims: 2
`
`FD (9 pages total)
`
`(21) Application No. Application H07-238972
`
`(71) Applicant
`
`000003078
`
`
`
`(22) Application Date August 25, 1995
`
`
`
`
`
`
`
`
`
`Toshiba Corporation
`
`72 Horikawa-cho, Saiwai-ku,
`
`Kawasaki-shi, Kanagawa-ken
`
`(72) Inventor
`
`Tadashi IIJIMA
`
`
`
`
`
`
`
`c/o Toshiba Corporation R&D Center
`
`1 Komukai Toshiba-cho, Saiwai-ku,
`
`Kawasaki-shi, Kanagawa-ken
`
`(72) Inventor
`
`Kyoichi SUGURO
`
`
`
`
`
`
`
`c/o Toshiba Corporation R&D Center
`
`1 Komukai Toshiba-cho, Saiwai-ku,
`
`Kawasaki-shi, Kanagawa-ken
`
`(72) Inventor
`
`Yoshiaki SHIMOOKA
`
`
`
`
`
`
`
`c/o Toshiba Corporation R&D Center
`
`1 Komukai Toshiba-cho, Saiwai-ku,
`
`Kawasaki-shi, Kanagawa-ken
`
`(74) Representative Patent Agent Takehiko SUZUE
`
`
`
`{J709905 03023377.DOC}
`
`1
`
`Page 2 of 19
`
`

`

`
`
`
`
`
`
`(54) [Title of Invention]
`
`SEMICONDUCTOR DEVICE AND
`
`MANUFACTURING METHOD
`
`THEREOF
`
`(57) [Abstract] (Revised)
`
`PURPOSE: Improving barrier
`
`properties of a barrier metal layer, and
`
`which is aimed at improving
`
`characteristics of an element, improving
`
`reliability of wiring, and the like.
`
`[Solution]
`
`In a semiconductor device in which a
`
`wiring is formed on a semiconductor
`
`substrate through a barrier metal, a groove
`
`33 is formed on a surface of a
`
`semiconductor substrate 31, and, on bottom
`
`and side surfaces of the groove 33, an
`
`amorphous alloy layer 34 of W-Si-N is
`
`formed, the alloy layer internally including
`
`micro crystallites of W. A Cu film 35 is
`
`embedded as the wiring within the groove
`
`33 through the alloy layer 34.
`
`
`
`{J709905 03023377.DOC}
`
`2
`
`Page 3 of 19
`
`

`

`
`
`[Scope of the Claims]
`
`[Claim 1] A semiconductor device comprising an amorphous alloy layer of W-Si-N formed
`
`on at least a bottom surface of an electrode or wiring layer, and the alloy layer internally has
`
`a structure including micro crystallites each having a diameter smaller than a film thickness
`
`of the alloy layer.
`
`[Claim 2] A manufacturing method of the semiconductor device comprising a step of
`
`forming, on an area where an electrode or wiring layer is to be formed over a semiconductor
`
`substrate, an amorphous alloy layer of W-Si-N that internally includes micro crystallites, and
`
`a step of forming a conductive film to be used as an electrode or wiring layer over the alloy
`
`layer.
`
`[0001]
`
`[Field of the invention]
`
`The present invention relates to a semiconductor device, and
`
`more particularly to a semiconductor device which has an improved barrier metal layer
`
`incorporated in an electrode or a wiring, and a manufacturing method of the same.
`
`[0002]
`
`[Conventional technology]
`
` Conventionally, a barrier metal layer has been interposed
`
`between one wiring layer and another wiring layer or an element when electrical contact is
`
`made. This intends to prevent reaction/diffusion between the wiring layers or between the
`
`wiring layer and the element, and to obtain favorable and reliable contact. Further, the
`
`barrier metal layer is used, not only for contacting portions, but also for forming a wiring or
`
`electrode on an insulating film.
`
`[0003]
`
`At present, TiN, TiW, and the like are used as a barrier metal material. Such materials are
`
`formed into a film by a sputtering process or the like, and the film produced is a polycrystal
`
`and is a columnar crystal in which a grain boundary is at right angles to a ground film.
`
`Therefore, the film has a grain boundary which is likely to produce diffusion in a direction in
`
`which diffusion is to be prevented, and the film has an unsuitable structure for ensuring
`
`barrier properties.
`
`[0004]
`
`It is also desired that the wiring layer has low resistance in order to enable the element to
`
`work with high efficiency. In order to do this, a future barrier metal layer must achieve
`
`lowered resistance by still further reduction in film thickness. The barrier properties of a
`
`reduced thickness barrier metal layer deteriorate more than those of a thick film. Therefore, it
`
`{J709905 03023377.DOC}
`
`3
`
`Page 4 of 19
`
`

`

`
`
`is expected that barrier properties are insufficient in the barrier metal layer formation method
`
`currently in use. Moreover, in order to obtain perfect barrier properties, a thin film of a
`
`monocrystalline body must be used. However, creating a thin film of a monocrystalline body
`
`without any defects is extremely difficult and cannot be achieved with present technology.
`
`[0005]
`
`In addition, polysilicon is conventionally used for gate electrodes. Since polysilicon has high
`
`electric resistance, an element has an increased parasitic resistance, thereby deteriorating the
`
`characteristics of the element. Therefore, use of a metal or a silicide as a low resistance
`
`material has been tried. However, when a metal film is formed on a gate insulating film by an
`
`ordinary sputtering technique and the like, it becomes polycrystalline and the crystal faces are
`
`not uniform, thereby creating differences in work functions between different crystal faces.
`
`Therefore, unstable difference is created in work functions in the semiconductor beneath the
`
`gate insulating film, causing the threshold voltage to become unstable and the element cannot
`
`be practically used.
`
`[0006]
`
`In addition, with the conventional barrier metal manufacturing method, when forming a film
`
`to a contact, a groove, and the like with a high aspect ratio, step coverage is poor, and the
`
`film thickness on a bottom or a side surface is reduced, thereby posing a problem that the
`
`performance of a barrier metal is deteriorated.
`
`[0007]
`
`[Problems to be solved by the invention]
`
`Thus, in the conventional semiconductor device,
`
`one could not say that the barrier property of the barrier metal layer used for an electrode or
`
`wiring was sufficient, and this had become a factor which causes degradation of an element
`
`characteristic, the reliability deterioration of wiring, and the like. Since control of the work
`
`function of the metal electrode on gate insulating film could not be performed, there was a
`
`problem that it was difficult to use a metal film as a gate electrode.
`
`[0008]
`
`With film-forming methods such as sputtering, when forming a film to a contact, a slot, and
`
`the like with a high aspect ratio, due to poor step coverage, the film thickness in a bottom or a
`
`side surface is reduced, thereby posing a problem that the performance of a barrier metal is
`
`deteriorated.
`
`[0009]
`
`The present invention was made in consideration of the above-mentioned situation, and it
`
`intends to improve the barrier property of a barrier metal layer, and to provide a
`
`{J709905 03023377.DOC}
`
`4
`
`Page 5 of 19
`
`

`

`
`
`semiconductor device and manufacturing method for the same, which can achieve element
`
`characteristics improvement and wiring reliability improvement.
`
`[0010]
`
`[Means for solving the problems]
`
`[Summary]
`
`In order to solve the above-described problems, the present invention has
`
`adapted the following configurations.
`
`[0011]
`
`Specifically, in the present invention, a semiconductor device in which an electrode or wiring
`
`is formed on a semiconductor substrate through a barrier layer comprises an amorphous alloy
`
`layer of W-Si-N formed on at least a bottom surface of the electrode or wiring layer, and the
`
`alloy layer internally has a structure including micro crystallites each having a diameter
`
`smaller than a film thickness of the alloy layer.
`
`[0012]
`
`In addition, in the present invention, a manufacturing method of the semiconductor device of
`
`the above-described configuration comprises a step of forming, on an area where an electrode
`
`or wiring layer is to be formed over a semiconductor substrate, an amorphous alloy layer of
`
`W-Si-N that internally includes micro crystallites, and a step of forming a conductive film to
`
`be used as an electrode or wiring layer over the alloy layer.
`
`[0013]
`
`Here, preferable embodiments of the present invention are as follows:
`
`(1) The element which constitutes the micro crystallites should be W.
`
`(2) The element which constitutes the micro crystallites should be a nitride of W.
`
`(3) The diameter of the micro crystallites should be 2 nm or less.
`
`(4) The amorphous alloy layer of W-Si-N should be formed by the CVD (chemical vapor
`
`deposition) method.
`
`(5) For the source gas in the CVD method, one should use at least a halogenated compound
`
`as a raw material for W (WF6 for example); an organic silane compound as a raw material for
`
`Si (inorganic silane compound such as SiH4 or SiH2Cl2, organic silane compound gas such as
`
`tetramethylsilane and tetraethoxysilane, for example); and N2 or NH3 as a nitride agent.
`
`(6) The CVD method should be performed under reaction control conditions.
`
`(7) The amorphous alloy layer of W-Si-N should be formed with the CVD method, and it
`
`should be used as a sputtering target.
`
`(8) The composition ratio of the amorphous alloy layer should be at WSixNy, where y is
`
`bigger than 0 and equal to or smaller than (1+x).
`
`{J709905 03023377.DOC}
`
`5
`
`Page 6 of 19
`
`

`

`
`
`[Operation] According to the present invention, as a cross sectional view is shown in Fig. 1
`
`(a) and a plan view is shown in Fig. 1 (b), by using the amorphous alloy layer of W-Si-N
`
`which has the structure containing the micro crystallites of W with a size of the film thickness
`
`or smaller inside the amorphous structure, there is no diffusion by grain boundary diffusion
`
`with TiN being used for example, and thereby, the barrier property can be improved. By
`
`forming the alloy layer having the above-mentioned structure on the gate insulating film, the
`
`work function can be uniformly controlled and thereby the reliability and performance of the
`
`element can be improved.
`
`[0014]
`
`According to the present invention, by using the CVD method for film formation of the W-
`
`Si-N alloy layer, the step coverage of the barrier metal to a contact or groove having a high
`
`aspect ratio can be improved, and the barrier property can be improved.
`
`[0015]
`
`In addition, in the above-mentioned CVD method, it is preferable that the growth of the W-
`
`Si-N alloy layer is performed not under a supply control but under reaction control, with the
`
`following reasons: The relationship of the film growth rate and growth temperature in the
`
`CVD method is proportional until a certain temperature, and after it exceeds the certain
`
`temperature, the growth rate becomes constant, as shown in Fig. 8. In Fig. 8, the reaction
`
`condition equivalent to the region which has a fixed inclination (i.e., the region where the
`
`membranous growth rate and growth temperature are proportional) is called a reaction control
`
`condition. Under the reaction control condition, since the catabolic rate of the raw material is
`
`slow, the raw material diffuses with sufficient distance before producing a thermal
`
`decomposition reaction even after arriving at a substrate surface. Therefore, as a result of the
`
`film depositing uniformly even on the portion where the raw material cannot reach easily, the
`
`film thickness becomes uniform and the step coverage on the substrate having a level
`
`difference becomes favorable.
`
`[0016]
`
`Further, according to the present invention, an alloy target of W-Si-N can be manufactured
`
`using a film formation of the W-Si-N alloy layer with the CVD method, and a W-Si-N alloy
`
`layer can be formed by the sputtering method using the same.
`
`[0017]
`
`Here, in the manufacturing method of the conventional W-Si-N alloy target, it was very
`
`difficult and impossible to uniformly distribute and sinter W and Si3N4 crystal, due to the
`
`difference in melting points of W and Si3N4. Also, when trying to perform mixing of WNx
`
`{J709905 03023377.DOC}
`
`6
`
`Page 7 of 19
`
`

`

`
`
`and Si, WNx decomposes by itself near the melting point of Si, thereby presenting a problem
`
`of WNx separating into W and N. However, by using the CVD method according to the
`
`present invention, it is possible to easily manufacture a W-Si-N alloy target.
`
`[0018]
`
`[Embodiments of the invention]
`
`Hereafter, embodiments of the present invention is
`
`described with reference to the drawings.
`
`[First Embodiment] Fig. 4 is for describing a semiconductor device according to a first
`
`embodiment of the present invention, and is a cross sectional view showing an embedded
`
`wiring formation process.
`
`[0019]
`
`First, as shown in Fig. 4 (a), a SiO2 film 32 is deposited as an insulating film with the CVD
`
`method and the like on a semiconductor substrate 31, and a groove 33 is formed on a surface
`
`of this SiO2 film 32 by RIE and the like. Here, although the SiO2 film was used as an
`
`insulating layer, polyimide, fluoridated SiO2, or the like may instead be used. As for a
`
`surface of the groove 33, it is desirable to perform smoothing by a method such as CDE,
`
`polishing or the like. In this case, as smoothness, it is desirable that the average roughness to
`
`be 1 nm or less.
`
`[0020]
`
`Subsequently, as shown in Fig. 4 (b), 20 nm of a W-Si-N film (alloy layer) 34 which is a
`
`ternary compound of W, and Si, and N, is formed as a diffusion barrier film and an adhesion
`
`layer. Here, although W is used as a refractory metal in the alloy layer 34, there is no problem
`
`if another refractory metal (Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or the like) is used.
`
`[0021]
`
`As for the formation method of the W-Si-N film 34, a target of W silicide (for example,
`
`WSi0.6) is used, using DC magnetron sputtering equipment. Formation sputtering was
`
`performed with flow rates of argon and N being 30 and 10sccm, respectively, in the pressure
`
`of 0.3 Pa at about power of 0.5kW. The sputtered film is analyzed by a TEM (transmission
`
`electron line microscope) and an electron diffraction image. The result is shown in Fig. 2 and
`
`Fig. 3.
`
`[0022]
`
`The TEM photograph shown in Fig. 2 shows that the W-Si-N film 34 is an amorphous film
`
`structure without grain boundaries. From the electron diffraction image photograph shown in
`
`Fig. 3, a broad diffraction ring of W is seen, and it can be understood that a micro crystallite
`
`of imperfect W in a crystallized state exists. It can be also understood, from the half-width,
`
`{J709905 03023377.DOC}
`
`7
`
`Page 8 of 19
`
`

`

`
`
`that it has the structure where the micro crystallite of W around 13 angstrom exists.
`
`[0023]
`
`With the structure like this, since the grain boundaries do not exist crossing through the film,
`
`the barrier property is kept in a favorable condition. Further, due to the existence of micro
`
`crystallites of W, low resistance is attained, thereby making it possible to form a barrier metal
`
`having an excellent barrier property and electric resistance. The film quality of this film was
`
`as shown in the following (Table 1).
`
`[0024] [Table 1]
`
`Composition ratio: WSi0.6N1.0
`
`Crystallinity: Micro crystallites exist in a noncrystalline [structure].
`
`[0025]
`
`Film stress: 0.5GPa (pulling)
`
`Specific resistance: 0.45mΩcm
`
`Adhesion: Good
`
`Barrier property: Good
`
`Resistance to acid: It is insoluble to hydrofluoric acid and oxidizes to H2O2.
`
`[0026]
`
`The micro crystallites of W are confirmed in this example. Even when other refractory metal
`
`is used, it has a similar structure where micro crystallites of the refractory metal exist.
`
`However, when W is used as a refractory metal for the alloy layer 34, micro crystallites of W
`
`were round. However, in case of other refractory metal (M), it is also considered that micro
`
`crystallites of nitrides (MxN etc.) or silicides (MxSi etc.) exist simultaneously. Also in the
`
`case of W, there is a possibility that micro crystallites of the nitrides or silicides exist
`
`simultaneously. Therefore, there is no problem if micro crystallites of at least one of them
`
`exist.
`
`[0027]
`
`The W micro crystallites of this type do not have a crystal growth even in a high temperature
`
`annealing (750 degrees C). Therefore, the grain boundaries crossing through the film do not
`
`exist, and stable micro crystallites are formed, and the barrier property does not deteriorate.
`
`However, when annealing for 30 minutes at 1000 degrees C is performed, the barrier property
`
`will deteriorate. Therefore, it is necessary to use it with conditions of 30 minutes at 1000
`
`degrees C or less. Since such a high temperature process is not used in an actual wiring
`
`formation process of a semiconductor device, there is no particular problem.
`
`[0028]
`
`{J709905 03023377.DOC}
`
`8
`
`Page 9 of 19
`
`

`

`
`
`In this embodiment, while the DC magnetron sputtering method was used for film formation
`
`of the W-Si-N film 34, other methods and conditions may be used as long as this structure is
`
`obtained. As for sputtering methods, a sputtering method using collimator and a method of
`
`using a WSixNy target maybe used, for example.
`
`[0029]
`
`At this time, in order to further improve adhesion, there is no problem even if a thin film is
`
`formed in advance, for example, the film comprising a refractory metal, such as Ti, etc.
`
`Moreover, an amorphous substance generally has low stress, and since the ternary compound
`
`of W, Si, and N is amorphous in the main structure, film stress is low (for example, 5 × 108
`
`dyn/cm2) as compared to a crystalline film and it is unlikely that there will be adverse effects
`
`on an element.
`
`[0030]
`
`Subsequently, as shown in Fig. 4 (c), a Cu film 35 used as a main wiring layer is deposited
`
`for 400 nm by a sputtering method and the like. At this time, adhesion of the Cu film 35 and
`
`the W-Si-N film 34 dramatically improves by depositing continuously, without exposing to
`
`the atmosphere. This improvement in adhesion shows its effect at the time of annealing of
`
`Cu in the following process. That is, if adhesion with Cu is favorable, there is little repelling
`
`or aggregation due to surface tension of Cu, and embedding to a groove or a hole can be
`
`favorably performed.
`
`[0031]
`
`Subsequently, as shown in Fig. 4 (d), by performing an annealing (about 200 degrees C - 700
`
`degrees C) during sputtering or after sputtering, a reflow of the Cu film 35 is carried out, and
`
`it is embedded evenly. Alternatively, it is also possible to embed by performing short-time
`
`melt by laser radiation. As for the condition, energy-density of 1.8 J/cm2, irradiation time of
`
`20 ns, substrate temperature of 300 degrees C, the pressure of Ar400Pa, and laser of XeCl
`
`(308 nm) may be used.
`
`[0032]
`
`Subsequently, as shown in Fig. 4 (e), portions other than the groove are etched and the
`
`embedded wiring layer comprising the Cu film 35 is formed. The etching is done by RIE, ion
`
`milling, CMP, polishing, etc. Thereby, a highly reliable embedded wiring is formed.
`
`[0033]
`
`When the barrier property of the W-Si-N film 34 to the Cu film 35 is checked, with a junction
`
`leak measurement, the leakage current in reverse bias did not increase, in the contact area of
`
`300 µm × 80 µm, and the diffusion-zone depth of 0.2 µm, until after the annealing in the
`
`{J709905 03023377.DOC}
`
`9
`
`Page 10 of 19
`
`

`

`
`
`foaming gas at 600 degrees C for 30 minutes, and favorable barrier property was shown.
`
`When diffusion of Cu to inside of the Si substrate is checked with an atomic absorption
`
`method, even after the annealing inside the foaming gas at 600 degrees C and for 30 minutes,
`
`the Cu concentration is at or below a detection limit (2 × 1010/cm3), and favorable barrier
`
`property is shown.
`
`[0034]
`
`Further, the film thickness of the W-Si-N film 34 shows the above-mentioned barrier
`
`property, even with 5 nm. Therefore, this film is an excellent film as a barrier metal, and
`
`since it shows favorable barrier property even if it is thin and even with continuous
`
`sputtering, it is effective even when the process is simplified.
`
`[0035]
`
`Although groove wiring was used in this embodiment, without this limitation, it may also be
`
`a structure where micro crystallites smaller than a film thickness exist inside of an amorphous
`
`structure as shown Fig. 1 as a barrier metal, and may employ a method of patterning after
`
`laminating Cu and its alloy film over a plane surface instead of the groove structure. Further,
`
`although the semiconductor Si was used as an element for the configuration, other
`
`semiconductors may be used, such as 4 group semiconductors or compound semiconductors
`
`such as 3-5, 2-6, 2-4-6, 2-4-5, 3-4-6, 1-3-6, and 2-5-7 group semiconductors. Although Cu
`
`was used as wiring, it may be combined with another substance such as Al, Ag, Au, W, or its
`
`alloy.
`
`[0036]
`
`The following shows the composition ratio when the flow ratio of Ar and N is changed in the
`
`sputtering for W-Si-N film formation. That is, when Ar/ N2 flow ratio was 30/10, the
`
`composition ratio was WSi0.6N1.0. When the flow ratio was 25/15, the composition ratio was
`
`WSi0.6N1.4. When the flow ratio was 20/20, the composition ratio was WSi0.6N1.7.
`
`[0037]
`
`The specific resistance at that time is shown in Fig. 5. The specific resistance ρ (mΩcm)
`
`increases as the nitrogen partial pressure ratio {N2/(Ar + N2)} increases.
`
`[0038]
`
`Accordingly, since values, such as specific resistance, change with the conditions of the
`
`sputtering, the W-Si-N film of desired film quality can be obtained by changing conditions.
`
`Since the W-Si-N film is insoluble to hydrofluoric acid, it is advantageous to post-processing
`
`of CMP, and the like. Thus, not only with the W-Si-N film of this embodiment but even with
`
`other W-Si-N film with a changed composition ratio, if a desired property is obtained, it will
`
`{J709905 03023377.DOC}
`
`10
`
`Page 11 of 19
`
`

`

`
`
`be satisfactory in any way. The completely similar property is also obtained for a Mo-Si-N
`
`system.
`
`[Second embodiment] Fig. 6 is a cross sectional view illustrating a semiconductor device
`
`according to a second embodiment, and showing a wiring formation process.
`
`[0039]
`
`First, as shown in Fig. 6 (a), 60 nm of an ONO films (SiO2/Si3N4/SiO2 structure) 52 are
`
`formed as a gate insulating film on a Si substrate 51. Then, as shown in Fig. 6 (b), a W-Si-N
`
`film (alloy layer) 53 is formed, which is a ternary compound of W (which is metal in which
`
`the micro crystallites of W smaller than the film thickness exist in a noncrystalline), Si, and
`
`N.
`
`[0040]
`
`Here, the above-mentioned alloy layer 53 is noncrystalline. A noncrystalline film generally
`
`has little surface unevenness, and there is little generating of interface state. Further, unlike a
`
`polycrystal, there is no difference in the work function by crystal orientation. For this reason,
`
`the threshold voltage is stabilized and stable element characteristic is acquired. Since W
`
`micro crystallites exist inside, the film has lower resistance and the speed is improved due to
`
`a gate electrode having lowered resistance.
`
`[0041]
`
`Subsequently, as shown in Fig. 6 (c), 300 nm of a W film 54 is formed as a gate electrode.
`
`Since the W-Si-N film 53 shows favorable barrier property toward a W film 54 at this time,
`
`degradation of the gate insulating film by W can be prevented. Then, as shown in Fig. 6 (d),
`
`processing is performed using photo lithography and the RIE method. Thereby, the gate
`
`electrode is formed.
`
`[0042]
`
`According to this embodiment, although the alloy of W, and Si, and N was used as a barrier
`
`layer, it may be a structure where micro crystallites smaller than the film thickness exist in
`
`the amorphous internal part as shown in Fig. 1, and the structure material is not particularly
`
`limited. Although W was used as the gate electrode, it may be combined with another
`
`substance such as Al, Ag, Au, Cu, W, or its alloy. The alloy itself may be also used as a gate
`
`electrode.
`
`[0043]
`
`The above-described method is an example of the method of forming the wiring using a
`
`barrier metal, and there is no problem of forming wiring of the above-described structure
`
`using the other methods at all. In addition, although the compound of W, and Si, and N was
`
`{J709905 03023377.DOC}
`
`11
`
`Page 12 of 19
`
`

`

`
`
`used as a barrier metal, without being limited to the above-described method, it may be a
`
`structure where micro crystallites smaller than the film thickness exist in the amorphous
`
`structure as shown in the aforementioned Fig. 1 as a barrier metal. Although Cu was used as
`
`wiring, it may be combined with another substance such as Cu, Al, Ag, Au, W, or its alloy.
`
`[0044]
`
`According to these embodiments, while wiring and electrode were used as examples, it is also
`
`applicable to a contact part with another wiring or element. In addition, in the range which
`
`does not deviate from the summary of the present invention, various changes may be made.
`
`[Third embodiment] Next, a third embodiment of the present invention is described. In this
`
`embodiment, a W-Si-N film is formed using the CVD method.
`
`[0045]
`
`The CVD method, being a method of growing a thin film by karyogenesis, has a property in
`
`which the film-forming rates in a transverse direction and a longitudinal direction are
`
`substantially the same (reaction control conditions). For this reason, a favorable shape with
`
`favorable step coverage is obtained, even in the contact/groove portions where aspect ratios
`
`are high. Therefore, even if an aspect ratio increases in the future due to micronization and
`
`high integration, a favorable barrier property is guaranteed in the future. Hereinafter, a
`
`specific method for forming a W-Si-N film with the CVD method is described.
`
`[0046]
`
`A halogenated compound of W (for example, WF6 gas) as W raw material, an NH3 gas as
`
`nitriding agent, a SiH4 gas as Si raw material, were used to form the W-Si-N film by the
`
`chemical vapor deposition method in the growing temperature of 360 degrees C, and pressure
`
`of 0.2Torr. The regulation of composition ratio was performed by each of the gas flow ratios.
`
`[0047]
`
`Fig. 7 is a schematic configuration diagram showing the CVD device for forming a thin film
`
`used in this embodiment. In this case, the relation between pressure and temperature was
`
`used as a reaction method. However, in order to further enhance the efficiency of the
`
`reaction, there is no problem of using a method that further lowers the reaction temperature
`
`using the plasma assistance (for example, PE (plasma enhanced) CVD method, ECR(electron
`
`cyclotron resonance) CVD, etc.).
`
`[0048]
`
`This equipment is roughly divided into a reaction container 68 which performs a chemical
`
`vapor deposition, and a supply and exhaust conductor system which performs supply and
`
`discharge of the raw material gas and the nitriding agent to this reaction container 68. The
`
`{J709905 03023377.DOC}
`
`12
`
`Page 13 of 19
`
`

`

`
`
`gas supply system comprises a WF6 cylinder 61, a NH3 cylinder 62, and a SiH4 cylinder 63,
`
`and the raw material gas cylinders 61-63 are connected to a raw material gas feed pipe 75
`
`each via exclusive-use mass flow controllers (mass flow rate controller) 64, 65, and 66,
`
`respectively.
`
`[0049]
`
`An exhaust pipe 76 that connects to a vacuum pump 73 via a pressure control valve 74 is
`
`connected to the reaction container 68. In the reaction container 68, a resistance heating
`
`heater 70 having a thermo couple 71 is provided. This heater 70 is heated to a prescribed
`
`temperature by a temperature controller 72 which controls a conducting current according to
`
`the detection temperature of the thermo couple 71. Further, a substrate 69 which is to form a
`
`thin film is heated over this resistance heating heater 70. The reaction container 68 is
`
`provided with a pressure detector 67.
`
`[0050]
`
`The Formation of the thin film was performed according to the following procedure using the
`
`above-mentioned chemical vapor deposition apparatus shown in Fig. 7. As a preliminary
`
`stage of film growth, the Si substrate 69 is first placed on the resistance heating heater 70.
`
`The resistance heating heater 70 adjusts so that the Si substrate 69 is held at 360 degrees C.
`
`[0051]
`
`Next, the vacuum pump 73 is operated and the inside of the reaction container 68 is held to
`
`the degree of vacuum of 10-6 Torr or below. And each gas is introduced to the reaction
`
`container 68 from the mass flow controllers 64-66. The flow rate of gas was set to WF6:
`
`NH3: SiH4 = 10:6:10 (SCCM). The pressure control valve 74 was adjusted and the degree of
`
`vacuum in the reaction container 68 was set to 0.2Torr. The film-forming rate at this time
`
`was 50 nm/min.
`
`[0052]
`
`With the above-described process, a 100 nm-thick W-Si-N film was formed. Membrane
`
`quality was analyzed of this thin film. The film composition ratio was W:Si:N=1:0.6:1, and
`
`as shown in the aforementioned (table 1), the film quality was similar to that of the W-Si-N
`
`film formed by the sputtering with a similar composition ratio. The same is said of the
`
`barrier property. Also, by varying the flow ratio of gas, generation of the W-Si-N film with
`
`various composition ratios was possible.
`
`[0053]
`
`According to this embodiment, although WF6/ NH3/ SiH4 is used as gas, nitrides, such as N2,
`
`may be used instead of NH3. Instead of SiH4, inorganic silane compounds such as SiH2Cl2,
`
`{J709905 03023377.DOC}
`
`13
`
`Page 14 of 19
`
`

`

`
`
`or an organic silane system compounds, such as tetramethylsilanes, tetraethoxysilane, and the
`
`like may be used. However, when using SiH2Cl2, the substrate temperature needs to be 500
`
`degrees C or more.
`
`[0054]
`
`While the Si substrate was used in this embodiment, a substrate that acts as a base for a
`
`sputtering target (for example, copperplate) may be used instead, in order to obtain a
`
`sputtering target with a desired composition ratio. That is, it is possible to manufacture the
`
`alloy target of W-Si-N which was unattainable due to the absence of the manufacturing
`
`method in the past. In this case, since a greater film thickness is required for the target, film
`
`formation requires a long time. Since the substrate is large-sized, it is necessary to use a
`
`heating heater with a greater resistance.
`
`[0055]
`
`Thus, by using the sputtering target obtained in this way, a W-Si-N film can be formed by the
`
`sputtering process. And since the material of a target itself is formed on a substrate in this
`
`case, composition of the W-Si-N film formed can be stabilized.
`
`[0056]
`
`The present invention is not limited to the various embodiments described above, and the
`
`embodiments can be achieved with various modifications without deviating from the scope of
`
`the present invention. In addition to W-Si-N, it is also possible to form the film comprising
`
`M-Si-N (M is metal, such as refractory metal, for example, Ti, Mo, V, Ta, and Cr) with the
`
`CVD method using the halogenated compound of composition metal, the above-mentioned
`
`silane system compound, and the above-mentioned nitriding agent, to be used for an
`
`electrode, wiring, etc.
`
`[0057]
`
`[Effect of the Invention]
`
`As described above, according to the present invention