US008115298B2
`
`(12) United States Patent
`Shimanuki
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 8,115,298 B2
`Feb. 14, 2012
`
`(54) SEMICONDUCTOR DEVICE
`
`(75) Inventor: Yoshihiko Shimanuki, Nanyou (JP)
`
`(58) Field of Classi?cation Search ................ .. 257/692,
`257/666, E23.043; 438/123
`See application ?le for complete search history.
`
`(73) Assignees: Renesas Electronics Corporation,
`
`(56)
`
`References Clted
`
`
`
`KanagaWa Electronics Co., Ltd., YoneZaWa (JP) YonezaWa
`
`
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.. 12/897,221
`
`(22) Filed:
`
`(65)
`
`Oct. 4, 2010
`_
`_
`_
`Pnor Pubhcatlon Data
`US 2011/0018122 A1
`Jan. 27, 2011
`_
`_
`Related U's' Apphcatlon Data
`(60) Continuation of application No. 12/610,900, ?led on
`NOV_ 2, 2009, now Pat No_ 7,821,119, which is a
`division of application No. 12/222,099, ?led on Aug.
`1’ 2008, HOW Pat NO_ 7,777,312, which is a division of
`application NO 10/879 010 ?led on Jun 30 2004
`HOW Pat‘ NO 7 804 lsé Winch is a Continuation 0%
`application No. 10/227,817, ?led on Aug. 27, 2002,
`noW abandoned Which is a continuation of application
`NO 09/623 3’44
`?led as
`a lication NO
`PCT/JP00/043’40 ’
`J
`30 2000 pp b d
`d '
`on un'
`’
`’ now a an one '
`.
`.
`.
`.
`.
`Forelgn Apphcatlon Prmnty Data
`_
`
`(30)
`
`.................................
`"""""""""""""""" "
`
`Jin.r3(6),
`p '
`’
`(51) Int_ CL
`(200601)
`H0 1L 23/495
`(52) us. Cl. .............. .. 257/692; 257/666; 257/E23.043;
`438/ 123
`
`5,287,000 A
`
`21994 Takahashi et 31‘
`
`5,409,866 A
`5,521,429 A
`
`tal.
`4/1995 S t
`5/1996 A1302, a1,
`(Continued)
`
`JP
`
`FOREIGN PATENT DOCUMENTS
`03_232264
`10/1991
`
`(Continued)
`Primary Examiner * Steven J Fulk
`(74) Attorney, Agent, or Firm * Mattingly & Malur, PC
`(57)
`ABSTRACT
`A semiconductor device is disclosed Which includes a tab (5)
`for use in supporting a semiconductor chip (8), a seal section
`(12) as formed by sealing the semiconductor Chip (8) With 21
`resin material, more than one tab suspension lead (4) 'for
`SUPPOI't Ofthe tab (5), a P11119111)’ Ofelecmcal leads (2)_Wh1Ch
`have a to-be-connected port1on as exposed to outer perlphery
`on the back surface of the seal section (12) and a thickness
`reduced portion as formed to be thinner than said to-be
`Cohhected Pohioh and Which are, Provided With ah ihher
`groove (26) and Outer groove (2]) In a Wlre bondmg Surface
`(2d) as disposed Within the seal section (12) of said to-be
`connected portion, and Wires (10) for electrical connection
`between the leads (2) and pads (7) of the semiconductor chip
`(8), Wherein said thickness reduced portion of the leads (2) is
`covered by or coated With a sealing resin material While
`causing the Wires (10) to be contacted With said to-be-con
`nected portion at Speci?ed part lying midway between the
`outer groove (2]) and inner groove (2e) to thereby permit said
`thickness reduced portion of leads (2) and the outer groove
`(2]) plus the inner groove (2e) to prevent occurrence of any
`accldehtal lead ‘hOP'dOWh detachment
`14 Claims, 38 Drawing Sheets
`
`Cisco Systems, Inc., EX 1155 Page 1
`
`

`

`US 8,115,298 B2
`Page 2
`
`US. PATENT DOCUMENTS
`King et a1.
`5,583,372
`A 12/1996
`Suetaki
`5,594,274
`A
`1/1997
`5,614,441
`A
`3/1997
`Hosokawa et a1.
`5,637,915
`A
`6/1997
`Sato et a1.
`5,834,831
`A 11/1998
`Kubota et a1.
`5,885,852
`A
`3/1999
`Kishikawa et a1.
`5,888,883
`A
`3/1999
`Sasaki et a1.
`5,942,794
`Okumura et a1.
`A *
`8/1999
`Yagi et a1.
`6,025,640
`A
`2/2000
`Yamaguchi
`6,081,029
`A
`6/2000
`6,111,306
`A
`8/2000
`Kawahara et a1.
`6,133,637
`A * 10/2000
`Hikita et a1. ................ .. 257/777
`Yagi et a1.
`6,201,292
`B1
`3/2001
`6,208,020
`B1
`3/2001
`Minamio et a1.
`6,229,200
`B1
`5/2001
`McCellan et a1.
`6,281,568
`B1
`8/2001
`Glenn et a1.
`Miyaki et a1.
`6,291,273
`B1
`9/2001
`6,352,880
`B1
`3/2002
`Takai et a1.
`Kang et a1.
`6,355,502
`B1
`3/2002
`
`........... .. 257/666
`
`2002/0041010 A1*
`2003/0127711 A1*
`2005/0106783 A1*
`2005/0199987 A1*
`
`4/2002
`7/2003
`5/2005
`9/2005
`
`Shibata ....................... .. 257/666
`Kawai et a1
`257/666
`Miyata ....... ..
`438/123
`Danno et a1. ................ .. 257/672
`
`FOREIGN PATENT DOCUMENTS
`5/1993
`5-129473
`JP
`1/1995
`07-030036
`JP
`8/1995
`07-211852
`JP
`1/1997
`9-8205
`JP
`7/1998
`10-189830
`JP
`12/1998
`10-335566
`JP
`2/1999
`11-040720
`JP
`3/1999
`11-07440
`JP
`3/1999
`11-074440
`JP
`4/1999
`11-111749
`JP
`1/2000
`2000-12758
`JP
`7/1998
`98-029903
`WO
`1/2001
`01/03186
`WO
`* cited by examiner
`
`Cisco Systems, Inc., EX 1155 Page 2
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 1 0f 38
`
`US 8,115,298 B2
`
`FIG. 1
`
`Cisco Systems, Inc., EX 1155 Page 3
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 2 0f 38
`
`US 8,115,298 B2
`
`Cisco Systems, Inc., EX 1155 Page 4
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 3 0f 38
`
`US 8,115,298 B2
`
`FIG. 3
`
`"U'U'U'UUU‘D'EfU‘UU*\
`
`/
`
`I121
`[i3
`[1:1
`[3:3
`@111
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`
`\ B
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`I?”
`:E‘] A
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`g
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`FIG. 4
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`FIG. 5
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`4
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`Q.
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`/
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`/
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`/
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`/_Ll
`
`Cisco Systems, Inc., EX 1155 Page 5
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 4 0f 38
`
`US 8,115,298 B2
`
`FIG. 6
`
`r
`
`Cisco Systems, Inc., EX 1155 Page 6
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 5 0f 38
`
`US 8,115,298 B2
`
`FIG. 9
`
`19/
`8FIG. 10(a)
`
`9
`
`L
`
`2
`
`5
`
`8FIG. 10(1))
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`l
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`T
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`
`Cisco Systems, Inc., EX 1155 Page 7
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 6 0f 38
`
`US 8,115,298 B2
`
`FIG. 1 1
`
`FIG. 12
`
`JL
`
`Cisco Systems, Inc., EX 1155 Page 8
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 7 0f 38
`
`US 8,115,298 B2
`
`FIG. 13
`
`15
`
`16
`
`Ell;
`
`2
`
`FIG. 14
`532?;
`
`6
`
`FIG. 15
`
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`
`16
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`
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`4/
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`
`Cisco Systems, Inc., EX 1155 Page 9
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 8 0f 38
`
`US 8,115,298 B2
`
`FIG. 16
`
`FIG. 17
`
`FIG. 18
`
`1O
`
`75 Ll-I
`
`Cisco Systems, Inc., EX 1155 Page 10
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 9 0f 38
`
`US 8,115,298 B2
`
`FIG. 19
`
`\9
`
`FIG. 21
`
`5 2/1
`
`I
`
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`l
`
`1
`
`5-: I
`
`1
`
`1
`
`19 ,
`
`2
`
`Cisco Systems, Inc., EX 1155 Page 11
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 10 0f 38
`
`US 8,115,298 B2
`
`FIG. 22
`
`Cisco Systems, Inc., EX 1155 Page 12
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 11 0f 38
`
`US 8,115,298 B2
`
`FIG. 24
`
`Cisco Systems, Inc., EX 1155 Page 13
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 12 0f 38
`
`US 8,115,298 B2
`
`FIG. 27
`
`/Dnn mmnmmmmrwmm
`
`12
`
`EEEFLEEr?hLrI-FLEFL
`
`K
`
`BEBBQR
`
`ww/w/wwwq
`
`Cisco Systems, Inc., EX 1155 Page 14
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 13 0f 38
`
`US 8,115,298 B2
`
`H
`
`12
`
`FIG. 29
`36
`/
`
`PRIOR ART
`28
`
`35f
`
`/
`
`FIG. 30
`46
`(
`
`4,2
`\
`
`PRIOR ART
`
`,45
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`1T]
`/) 7 8
`
`(M
`
`Cisco Systems, Inc., EX 1155 Page 15
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 14 0f 38
`
`US 8,115,298 B2
`
`49
`FIG. 31
`mmnmmnnnnmmm'm/ 12
`
`11
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`2
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`E
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`EJHWWW/WQQMBF :
`illlllllllm
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`7
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`FIG. 32
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`49
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`7 8b
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`5%)
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`5
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`128a
`
`2b 2a 20
`
`Cisco Systems, Inc., EX 1155 Page 16
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 15 0f 38
`
`US 8,115,298 B2
`
`FIG. 33
`
`PREPARATION OF
`LEAD FRAME.
`I
`DIE BONDING
`
`I
`WIRE BONDING
`
`I
`MOLD
`
`£81
`
`,82
`
`83
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`,84
`
`I
`OUT FOR SEPARATION
`
`585
`
`I
`COMPLETE QFN
`
`86
`
`Cisco Systems, Inc., EX 1155 Page 17
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 16 0f 38
`
`US 8,115,298 B2
`
`FIG. 34(a)
`8a
`5a 9
`3
`)
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`Y
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`1481
`
`FIG. 34(0)
`5
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`5
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`BQi-H
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`2b 2a
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`1w“
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`>
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`7
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`4
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`2a 20
`
`Cisco Systems, Inc., EX 1155 Page 18
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 17 0f 38
`
`US 8,115,298 B2
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`Cisco Systems, Inc., EX 1155 Page 19
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 18 0f 38
`
`US 8,115,298 B2
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`Cisco Systems, Inc., EX 1155 Page 20
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 19 of 38
`
`US 8,115,298 B2
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`
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`—‘ "I’lll‘vnnl"——
`7.41m"..-
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`b
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`20
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`Cisco Systems, Inc., EX 1155 Page 21
`
`Cisco Systems, Inc., EX 1155 Page 21
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 20 of 38
`
`US 8,115,298 B2
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`Cisco Systems, Inc., EX 1155 Page 22
`
`Cisco Systems, Inc., EX 1155 Page 22
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 21 of 38
`
`US 8,115,298 B2
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`
`
`Cisco Systems, Inc., EX 1155 Page 23
`
`Cisco Systems, Inc., EX 1155 Page 23
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 22 of 38
`
`US 8,115,298 B2
`
`FIG. 43
`
`
`
`Cisco Systems, Inc., EX 1155 Page 24
`
`Cisco Systems, Inc., EX 1155 Page 24
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 23 of 38
`
`US 8,115,298 B2
`
`'0
`
`N C
`
`isco Systems, Inc., EX 1155 Page 25
`
`Cisco Systems, Inc., EX 1155 Page 25
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 24 of 38
`
`US 8,115,298 B2
`
`FIG. 46
`
`
`
`Cisco Systems, Inc., EX 1155 Page 26
`
`Cisco Systems, Inc., EX 1155 Page 26
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 25 of 38
`
`US 8,115,298 B2
`
`FIG. 48(3)
`
`12b~_,‘E
`
`
`
`Cisco Systems, Inc., EX 1155 Page 27
`
`Cisco Systems, Inc., EX 1155 Page 27
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 26 of 38
`
`US 8,115,298 B2
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`
`
`Cisco Systems, Inc., EX 1155 Page 28
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`Cisco Systems, Inc., EX 1155 Page 28
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`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 27 of 38
`
`US 8,115,298 B2
`
`FIG. 50(a)
`
`
`
`Cisco Systems, Inc., EX 1155 Page 29
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`Cisco Systems, Inc., EX 1155 Page 29
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`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 28 of 38
`
`US 8,115,298 B2
`
`FIG. 51
`
`2C -
`
`12
`
`LY
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`’
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`4b
`
`f 12a
`
`51
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`Cisco Systems, Inc., EX 1155 Page 30
`
`Cisco Systems, Inc., EX 1155 Page 30
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`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 29 of 38
`
`US 8,115,298 B2
`
`
`
`
`
`
`
`
`
`
`“IV”
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`wag—1: ‘
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`Cisco Systems, Inc., EX 1155 Page 31
`
`Cisco Systems, Inc., EX 1155 Page 31
`
`

`

`US. Patent
`
`Feb. 14, 2012
`
`Sheet 30 of 38
`
`US 8,115,298 B2
`
`FIG. 54
`
`
`
`
`
` A
`
`Cisco Systems, Inc., EX 1155 Page 32
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`Cisco Systems, Inc., EX 1155 Page 32
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`

`

`US. Patent
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`Feb. 14, 2012
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`Sheet 31 of 38
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`US 8,115,298 B2
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`
`
`Cisco Systems, Inc., EX 1155 Page 33
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`Cisco Systems, Inc., EX 1155 Page 33
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`

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`US. Patent
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`Feb. 14, 2012
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`Sheet 32 of 38
`
`US 8,115,298 B2
`
`
`
`FIG. 57(b)
`
`53
`
`w
`
`Z We; 3
`
`52
`
`53
`
`2
`
`FIG. 57(0)
`m~52
`
`53
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`
`53
`
`FIG. 57(d)
`r—Ee__
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`e
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`2
`
`+F
`
`2
`
`Cisco Systems, Inc., EX 1155 Page 34
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`Cisco Systems, Inc., EX 1155 Page 34
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`

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`US. Patent
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`Feb. 14, 2012
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`Sheet 33 of 38
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`US 8,115,298 B2
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`
`
`Cisco Systems, Inc., EX 1155 Page 35
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`Cisco Systems, Inc., EX 1155 Page 35
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`

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`US. Patent
`
`Feb. 14 2012
`
`Sheet 34 0f38
`
`’lllA
`
`W 5
`
`4
`
`FIG. 59(b)
`
`
`
`
`
`
`
`
`Cisco Systems, Inc., EX 1155 Page 36
`
`

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`US. Patent
`
`Feb. 14 2012
`
`Sheet 35 0f38
`
`FIG. 60(3)
`
`A 2
`
`
`
`
`
`
`
`
`
`
`
`
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`
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`
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`
`Cisco Systems, Inc., EX 1155 Page 37
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`

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`US. Patent
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`Feb. 14, 2012
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`Sheet 36 of 38
`
`US 8,115,298 B2
`
`FIG. 61 (a)
`
`55
`
`55
`
`55
`
`2 5
`
`~54
`
`4
`
`FIG. 61(b)
`
`55
`
`55
`
`55
`
`
`
`Cisco Systems, Inc., EX 1155 Page 38
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`Cisco Systems, Inc., EX 1155 Page 38
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`

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`US. Patent
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`Feb. 14, 2012
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`Sheet 37 of 38
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`US 8,115,298 B2
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`
`
`
`
`
`
`
`
`WA IKEE'fl-Efl'u-L m
`
`
`
`Cisco Systems, Inc., EX 1155 Page 39
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`Cisco Systems, Inc., EX 1155 Page 39
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`

`

`FIG. 64
`
`{ WEWW;
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`
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`
`Cisco Systems, Inc., EX 1155 Page 40
`
`

`

`1
`SEMICONDUCTOR DEVICE
`
`CROSS-REFERENCES
`
`US 8,115,298 B2
`
`2
`
`This is continuation application of US. Ser. No. 12/610,
`900, filed Nov. 2, 2009, which is a continuation application of
`US. Ser. No. 12/222,099, filed Aug. 1, 2008 (now US. Pat.
`No. 7,777,313), which is a divisional application of US.
`patent application Ser. No. 10/879,010, filed Jun. 30, 2004
`(now US. Pat. No. 7,804,159), which is a continuation appli-
`cation of US. patent application Ser. No. 10/227,817, filed
`Aug. 27, 2002 (now abandoned); which is a continuation
`application of US. patent application Ser. No. 09/623,344,
`filed Aug. 31, 2000 (now abandoned); which is a 371 of
`PCT/JP00/04340, filed Jun. 30, 2000. The entire disclosures
`of all of the above-identified applications are hereby incor-
`porated by reference.
`
`TECHNICAL FIELD
`
`The present invention relates generally to semiconductor
`fabrication technologies and, more particularly, to techniques
`adapted for miniaturization and thickness reduction plus cost
`down as well as reliability improvements.
`
`BACKGROUND ART
`
`Those techniques as will be explained in brief below have
`been taken into consideration by the inventors as named
`herein during studying for reduction to practice ofthe present
`invention as disclosed and claimed herein.
`
`The quest for further miniaturization or “downsizing” of
`modern electronic equipment results in shrinkage of dimen-
`sion and weight reduction and tends to grow rapidly in the
`markets of electronics and semiconductor industries. Under
`
`such circumstances, it is becoming more important in the
`manufacture of small size electronic equipment to further
`improve the large-scale integrated circuit (LSI) chip mount
`architecturesithat is, to develop an improved LSI chip pack-
`aging technique with ultra-high integration densities.
`In addition. as the markets of electronics grow. improve-
`ments in productivity have been more strictly required while
`simultaneously reducing manufacturing costs.
`A first prior known approach to satisfying the above tech-
`nological requirements is to employ a resin sealed or hermetic
`surface-mount semiconductor device structure as disclosed
`
`in, for example, Published Unexamined Japanese Patent
`Application (“PUJPA”) No. 5-129473. The prior art device as
`taught thereby is such that as shown in FIG. 29, this device
`employs a lead frame 35 with a pattern of electrical leads 33
`and a chip support paddle or die pad 34, also known as a “tab”
`among those skilled in the art, being located on the same
`surface, wherein the prior art is featured in that the leads 33
`are electrically connected at lower surfaces to a semiconduc-
`tor chip 36 via bonding wires 37, wherein the lower surfaces
`are for use as external electrodes each functioning as an
`electrical connector portion with external circuitry opera-
`tively associated with the semiconductor device.
`Unfortunately the first prior art shown in FIG. 29 is asso-
`ciated with a problem which follows. As this is structurally
`designed so that the tab 34’s parts-mount surface side is
`exposed from the lower surface of the semiconductor device,
`the tab 34 will possibly come into direct contact with leads on
`the parts mount substrate when mounting the semiconductor
`device on the mount substrate, which in turn makes it impos-
`sible to form any leads at corresponding portions ofthe mount
`substrate, resulting in a noticeable decrease in the degree of
`
`freedom of substrate design schemes.Another problem is that
`since the device is structurally arranged so that the tab 34 is
`sealed only at its one surface, the resulting contact area
`between the tab 34 and a sealing material 38 used decreases
`causing the tight contact or adhesiveness to degrade accord-
`ingly, which would result in a decrease in reliability of the
`semiconductor device.
`
`A second prior art resin sealed semiconductor device is
`found in PUJPA No. 10-189830 (JP-A-10189830). This
`device is shown in FIG. 30, which includes a semiconductor
`element 42 as mounted on a tab 41 that in turn is supported by
`a hanging or “suspending” lead 40 of a lead frame 39, metal
`fine leads 45 for electrical interconnection between elec-
`
`trodes 43 on the upper surface of said semiconductor element
`42 and associative inner leads 44, a sealing resin material 46
`for use in sealing an outer surrounding region of the semicon-
`ductor element 42 containing metal fine lead regions over the
`upper surface of semiconductor element 42, and external
`connect terminals 47 that are laid out in a bottom surface
`
`region of said sealing resin 46 for connection with said inner
`leads 44, wherein said suspension lead 40 has been subjected
`to the so-called “up-set” processing thus having step-like
`differences 48, called “stepped portions,” and wherein the
`sealing resin 46 is also formed at part underlying said tab 41
`to a thickness corresponding to the amount of said upset
`processing.
`The second prior art shown herein is such that since the
`suspension lead 40 ofthe lead frame 39 has been subject to the
`up-set processing to have the stepped portions 48, it becomes
`possible to permit the sealing resin 46 to be present at the part
`underlying the tab 41, which in turn makes it possible to
`provide substantially the double-face sealed semiconductor
`device structure with respect to the lead frame 39, thereby
`offering increased reliability when compared to said first
`prior art discussed above.
`Another advantage of the prior art is that in view of the fact
`that this is structurally designed to prevent exposure ofthe tab
`41’s parts-mount substrate side from the lower surface of the
`semiconductor device, the tab 41 will no longer come into
`contact with those leads on the mount substrate. thereby
`increasing the degree of freedom in parts mount design
`schemes.
`
`Other examples of the semiconductor device with its tab
`subjected to the up-set processing (tab finishing treatment)
`are known among those skilled in the art, one of which is
`disclosed in JP-A-11-74440.
`
`Regrettably said first prior art is faced with a problem in
`that a decrease in seal material-to-tab contact area can be
`
`lower the resultant adhesiveness thus reducing the reliability
`of the semiconductor device because of the fact that this
`
`device is structured so that the tab is sealed solely at its one
`surface in order to improve the thickness reducibility.
`Additionally, although said second prior art and the one as
`taught by the above-identified Japanese document JP-A-l 1-
`74440 are drawn to the double-face resin-sealed semiconduc-
`
`tor device with respect to the lead frame used therein, which
`offers an advantage as to an increase in reliability when com-
`pared to said first prior art, stepped portions included are to be
`formed through the up-set processing whereby each of them
`suffers from a problem in that it is impossible to improve the
`thickness reducibility to the extent that is equivalent to the
`first art and also a “tab dislocation” problem including dis-
`placement or strain of the tab occurring during execution of
`such up-set Processing.
`In short, it has been affirmed by the inventors that even the
`first and second prior art devices stated supra have met with
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`Cisco Systems, Inc., EX 1155 Page 41
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`Cisco Systems, Inc., EX 1155 Page 41
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`US 8,115,298 B2
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`3
`limited success as to the capability of solving the conflicting
`or “trade-off” problemsiie. the thickness reducibility and
`increased reliability required.
`It is therefore a primary objective of the present invention
`to provide a new and improved semiconductor device capable
`of achieving both the thickness reducibility and high reliabil-
`ity at a time and also methodology of manufacturing the
`semiconductor device along with a parts mount structure of
`the same.
`
`Another object of this invention is to provide an improved
`semiconductor device capable of increasing productivities
`while reducing production costs and a method of manufac-
`turing the device as well as a parts mount structure of same.
`A further object of the invention is to provide a semicon-
`ductor device capable of-preventing any accidental electrical
`short circuiting and unwanted lead dropdown detachment
`otherwise occurring during parts mounting processes and a
`method of manufacturing the device as well as a parts mount
`structure of same.
`
`These and other objects, features and advantages of the
`invention will be apparent from the following more particular
`description of preferred embodiments of the invention, as
`illustrated in the accompanying drawings.
`
`DISCLOSURE OF THE INVENTION
`
`Some representative ones of the inventive teachings as
`disclosed and claimed herein will be explained in briefbelow.
`A semiconductor device comprising a tab supported by a
`plurality of suspension leads, a plurality of leads disposed to
`surround periphery of said tab, a semiconductor chip
`mounted on one principal surface of said tab and electrically
`connected to one principal surface of said plurality of leads,
`and a sealing resin for sealing said plurality of leads and said
`semiconductor chip plus said tab, wherein the remaining
`principal surface opposite to said one principal surface of said
`plurality of leads is exposed from said sealing resin-and that
`said tab is less in thickness than said plurality of leads.
`In addition, a method of manufacturing a semiconductor
`device comprises the steps of: preparing a matrix lead frame
`including a plurality of lead frames each having a plurality of
`leads and a tab less in thickness than said plurality of leads
`plus a suspension lead for support of said tab; performing die
`bonding for mounting a semiconductor chip on or over the tab
`of each said lead frame; performing wire bonding for connec-
`tion by wires between said semiconductor chip and the plu-
`rality of leads of said lead frame; sealing with a sealing resin
`said lead frame and said semiconductor chip plus saidwires to
`permit said plurality of leads to be exposed on a lower surface
`side thereof; and cutting said matrix lead frame into a plural-
`ity of unitary lead portions at part in close proximity to a seal
`region as sealed at said step of sealing with the sealing resin
`to thereby obtain a plurality of semiconductor devices.
`Furthermore, a mounting structure of a semiconductor
`device in accordance with the invention is a semiconductor
`
`device that is arranged to include a pattern of electrical leads
`on a mount substrate, a tab supported by a plurality of sus-
`pension leads, a plurality of leads as laid out to surround the
`periphery of saidtab, a semiconductor chip that is mounted on
`or over one principal surface of said tab and is electrically
`connected to one principal surface of said plurality of leads,
`and a sealing resin Material for use in sealing said plurality of
`leads and said semiconductor chip plus said tab, wherein the
`remaining principal surface on an opposite side to said one
`principal surface of said plurality of leads is exposed from
`said sealing resin, and wherein an adhesive material is used to
`attain coupling with the other principal surface of those leads
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`4
`ofthe semiconductor device with said tab formed to be less in
`
`thickness than said plurality of leads.
`Moreover, a resin sealed semiconductor device comprises
`a tab for support of a semiconductor chip, a seal section as
`formed by resin sealing of said semiconductor chip, a plural-
`ity of tab suspension leads including a supporting portion for
`use in supporting said tab and an exposed portion as coupled
`thereto and exposed to a surface on a semiconductor device
`mount side surface of said seal section, said supporting por-
`tion being formed to be thinner than said exposed portion, a
`plurality ofleads disposed around saidtab and exposed to said
`semiconductor device mount side surface of said seal section,
`and a connection member for connection between a surface
`
`electrode of said semiconductor chip and a corresponding one
`of said leads, wherein said tab suspension leads are coupled
`together via said tab.
`In accordance with the instant invention, as the support
`portion ofthe tab at the tab suspension leads is formed to have
`a decreased thickness, it is possible to bury or embed the
`support portion in the seal section with the sealing resin
`covering the same thereby enabling provision ofthe intended
`structure with the tab suspension lead’s exposed portion
`being exposed only at the end(s) at a corner or comers on the
`back surface of the seal section.
`
`This in turn makes it possible to form an increased clear-
`ance between the exposed portion of the tab suspension lead
`and its neighboring lead on the back surface ofthe seal section
`while at the same time enabling prevention of electrical short-
`ing otherwise occurring when mounting the semiconductor
`device on a parts mount substrate or board or else due to the
`fact that the tab is buried within the seal section.
`
`Further, a resin sealed semiconductor device is provided
`which comprises a tab supporting a semiconductor chip and
`being smaller than said semiconductor chip, a seal section as
`formed by resin sealing of said semiconductor chip, a sup-
`porting portion for support of said tab, a plurality of leads
`disposed around said tab and exposed to a semiconductor
`device mount side surface of said seal section, and a connec-
`tion member for connection between more than one surface
`
`electrode of said semiconductor chip and a corresponding one
`of said leads, wherein said tab and said semiconductor chip
`are in contact by adhesion with each other at an inside loca-
`tion relative to said surface electrode of said semiconductor
`
`chip.
`According to the invention, it is possible to support the
`specified part at or near the end portion on the back surface of
`the semiconductor device by a bonding stage including a
`heatup wire-bonding process. This makes it possible during
`wire bonding to apply suitable ultrasonic waves and/or heat to
`wires being bonded, thereby enabling improvement in reli-
`ability and adhesiveness of such wire bonding.
`In addition, a method ofmanufacturing a resin sealed semi-
`conductor device comprises the steps of: preparing a lead
`frame including a tab capable of supporting a semiconductor
`chip, a plurality of tab suspension leads having a support
`section for use in supporting said tab and an exposed portion
`coupled thereto with said support section being thinner than
`said exposed portion, and a plurality of leads as disposed
`around said tab; adherently securing said tab and said semi-
`conductor chip together; using a connection member to con-
`nect a surface electrode of said semiconductor chip to a cor-
`responding one of said leads; forming a seal section by
`causing a sealing resin to flow onto an opposite surface to a
`chip support surface of said tab while covering a thickness
`reduced portion of said tab suspension lead with said sealing
`resin and then by disposing said plurality of leads and said
`exposed portion of said tab suspension lead on a semiconduc-
`
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`US 8,115,298 B2
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`5
`tor device mount side surface to thereby resin-mold said
`semiconductor chip; and subdividing saidtab suspension lead
`into portions at said exposed portion of said tab suspension
`lead while separating said plurality of leads from a frame
`body of said lead frame.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A diagram showing FIG. 1 shows a diagram of a perspec-
`tive view of an exterior appearance of a semiconductor device
`in accordance with an embodiment 1 ofthe present invention.
`A diagram showing FIG. 2 shows a diagram of a plan view
`(lower surface side) of the semiconductor device shown in
`FIG. 1.
`
`FIG. 3 shows a plan view of a unitary lead section of the
`embodiment 1 of the invention.
`FIG. 4 shows a cross-sectional view ofthe unit lead section
`
`shown in FIG. 3 as taken along cutaway line A-A.
`FIG. 5 shows a sectional view of the unit lead section
`
`shown in FIG. 3 taken along line B-B.
`FIG. 6 shows a plan view of the semiconductor device
`shown in FIG. 1 as partly broken to make visible its internal
`configuration for illustration purposes only.
`FIG. 7 shows a sectional view ofthe semiconductor device
`
`shown in FIG. 6 taken along line C-C.
`FIG. 8 shows a sectional view ofthe semiconductor device
`
`shown in FIG. 6 taken along line D-D.
`FIG. 9 shows a sectional view ofthe semiconductor device
`
`1 shown in FIG. 6 taken along line E-E.
`A flow diagram showing FIG. 10 shows a diagram of in
`cross-section a method of manufacturing the semiconductor
`device in accordance with the embodiment 1 ofthe invention.
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`FIG. 11 shows a plan view of a matrix lead frame for use
`during manufacture of the semiconductor device in accor-
`dance with the embodiment 1 of the invention.
`
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`FIG. 21 shows a conceptual diagram showing a state in
`which the metal tool is disassembled at the resin sealing step
`of the semiconductor device in accordance with the embodi-
`ment 1 of the invention.
`
`FIG. 22 shows a perspective view ofan exterior appearance
`showing a state in which the semiconductor device in accor-
`dance with the embodiment
`1 of the invention has been
`
`mounted to a parts mount substrate.
`FIG. 23 shows a sectional view of the device structure of
`
`FIG. 22 taken along line H-H.
`FIG. 24 shows a plan view of a unitary lead section of an
`embodiment 2 of the invention.
`FIG. 25 shows a sectional view of the unit lead section
`
`shown in FIG. 24 take along line I-I.
`FIG. 26 shows a sectional view of the unit lead section
`
`shown in FIG. 24 take along line J-J.
`FIG. 27 shows a partial see-through diagram of a semicon-
`ductor device in accordance with the embodiment 2 of the
`invention.
`FIG. 28 shows a sectional view of the semiconductor
`
`device shown in FIG. 27 as taken along line K-K.
`FIG. 29 shows a sectional view of the first prior art semi-
`conductor device that has been already discussed in the intro-
`ductory part of the description.
`FIG. 30 shows a sectional view of the second prior art
`semiconductor device as also stated previously in the intro-
`ductory part of the description.
`FIG. 31 shows a plan view of an exemplary semiconductor
`device in accordance with an embodiment 3 of the invention
`
`as partly broken at its sealing section to render visible its
`internal configuration for illustration purposes only.
`FIG. 32 shows a sectional view of the semiconductor
`
`device shown in FIG. 31 as taken along line L-L.
`FIG. 33 shows a process flow diagram showing an example
`of the procedure for assembly of the semiconductor device
`shown in FIG. 31.
`
`FIG. 34 shows parts (a), (b), (c), (d) and (e) are sectional
`flow diagrams showing an exemplary structure per main pro-
`cess step in the assembly of the semiconductor device shown
`in FIG. 31.
`
`FIG. 35 shows a perspective view ofan exterior appearance
`showing an example of the structure of a semiconductor
`device in accordance with an embodiment 4 of the invention.
`FIG. 36 shows a bottom view of the structure of the semi-
`conductor device shown in FIG. 35.
`FIG. 37 shows a sectional view of the semiconductor
`
`device shown in FIG. 35 taken along line M-M.
`FIG. 38 shows a sectional view of the semiconductor
`
`device shown in FIG. 35 taken along line N—N.
`FIG. 39 shows a partial sectional view of one exemplary
`state at a wire-bonding process step during the assembly of
`the semiconductor device shown in FIG. 35.
`
`FIG. 12 shows an enlarged plan view of main part (upper
`surface side) of a unitary lead frame of the matrix lead frame
`shown in FIG. 11.
`
`FIG. 13 shows an enlarged plan view of main part (lower
`surface side) of the unitary lead frame of the matrix lead
`frame shown in FIG. 11.
`FIG. 14 shows a sectional view of the unit lead frame
`
`shown in FIG. 12 taken along line F-F.
`FIG. 15 shows a sectional view of the unit lead frame
`
`shown in FIG. 12 taken along line G-G.
`FIG. 16 shows a conceptual diagram showing a method of
`depositing an adhesive onto a tab at a die-bonding process
`step of the semiconductor device in accordance with the
`embodiment 1 of the invention.
`
`FIG. 17 shows a conceptual diagram showing a method of
`mounting a semiconductor chip on the tab at the die-bonding
`step of the semiconductor device in accordance with the
`embodiment 1 of the invention.
`
`FIG. 18 shows a conceptual diagram showing a wire-bond-
`ing method of the semiconductor device in accordance with
`the embodiment 1 of the invention.
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`FIG. 19 shows a conceptual diagram showing a state in
`which a metal frame structure such as a metal tool and a
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`matrix lead frame have been aligned in position with each
`other at a resin sealing process step of the semiconductor
`device in accordance with the embodiment 1 ofthe invention.
`
`FIG. 20 shows a conceptual diagram showing a state in
`which the metal tool is clamped at the resin sealing step ofthe
`semiconductor device in accordance with the embodiment 1
`of the invention.
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`FIG. 40 shows a partial plan view of one example of the
`resultant structure when completion ofmolding in a semicon-
`ductor device in accordance with an embodiment 5 of the
`
`invention, which structure is partly broken to visualize its
`internal configuration for illustration purposes only.
`FIG. 41 shows a sectional view of the semiconductor
`
`device shown in FIG. 40 taken along line P-P.
`FIG. 42 shows a partial plan view of an exemplary lead
`frame structure for use during assembl