United States Patent
`
`
`
`
`
`Lowrey et al.
`
`
`
`[19]
`
`
`[11]
`
`
`1451
`
`
`
`
`Patent Number:
`
`
`
`Date of Patent:
`
`5,021,353
`
`Jun. 4, 1991
`
`
`
`
`[54]
`
`
`[751
`
`
`[73]
`
`
`[2 ll
`
`
`SPLIT-POLYSILICON CMOS PROCESS
`
`
`
`INCORPORATING SELF-ALIGNED
`
`
`SILICIDATION OF CONDUCFIVE REGIONS
`
`
`
`
`
`
`Inventors: Tyler A. Lowrey; Dermot M. Durean;
`
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`
`
`Tnmg T. Donn; Gordon A. Haller;
`
`
`
`
`
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`Mark E. Tuttle, all of Boise, Id.
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`
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`Assignee: Micron Technology, Inc., Boise, Id.
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`
`
`Appl. No.: 4ss,o29
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`
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`Filed:
`
`[22]
`
`[51]
`
`[52]
`
`
`[53]
`
`
`[5 6]
`
`
`Feb. 26,‘ 1990
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`
`
`Int. Cl.5 ................. .. I-[0lL 21/265; I-I0lL 21/336
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`U.S. Cl. ............................. ..; ...... .. 437/34; 437/44;
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`437/57; 357/42; 357/44
`
`
`
`Field of Search ..................... .. 437/27, 28, 29, 30,
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`437/34, 56, 57, 200, 192, 40, 41, 44, 233;
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`357/23.3, 23.4, 40, 41, 42, 44
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`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`4,530,150 7/1985 Shirato .................................. 437/44
`
`
`
`
`3/1986
`4,577,391
`
`
`
`
`
`Gasner ..........
`7/1986
`4,599,789
`
`
`
`
`4,637,124
`1/1987 Okuyama el al.
`
`
`
`
`
`4,745,086
`5/1988 Parrillo ........... ..
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`2/1981 Japan .....................................
`0019669
`
`
`
`1/1982 Japan
`0017164
`
`
`
`3/1984 Japan
`0055068
`
`
`
`0213051 10/1985 Japan
`
`
`
`0165355
`7/1987 Japan .......4»
`
`
`
`Primary Examiner-—Olik Chaudhuri
`
`
`Assistant Examiner—M. Wilczewski
`
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`
`
`Attorney, Agent, or Firm—Angus C. Fox, III; Stanley N.
`
`
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`
`
`
`
`Protigal; Albert Crowder
`
`
`
`ABSTRACT
`
`
`
`[57]
`
`
`An improved CMOS fabrication process which uses
`
`
`
`
`
`
`separate masking steps to pattern N-channel and P-
`
`
`
`
`
`
`
`channel transistor gates from a single layer of conduc-
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`
`
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`
`
`
`tively-doped polycrystalline silicon (poly) and incorpo-
`
`
`
`
`
`rates self-aligned salicidation of conductive regions.
`
`
`
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`
`
`The object of the improved process is to reduce the cost
`
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`
`
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`
`
`
`and improve the reliability, performance and manufac-
`
`
`
`
`
`
`turability of CMOS devices by a process which features
`
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`a dramatically reduced number of photomasking steps
`
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`and which further allows self-aligned salicidation of
`
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`
`
`transistor conductive regions. By processing N-channel
`
`
`
`
`
`
`and P-channel devices separately, the number of photo-
`
`
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`
`
`
`masking steps required to fabricate complete CMOS
`
`
`
`
`
`
`
`circuitry in a single-polysilicon-layer or single-metal
`
`
`
`
`
`
`layer process can be reduced from eleven to eight.
`
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`
`Starting with a substrate of P-type material, N-channel
`
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`devices are formed first, with unetched poly left in the
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`future P-channel regions until N-channel processing is
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`complete. The improved CMOS process provides the
`
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`
`
`following advantages over conventional process tech-
`
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`
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`nology: Use of a masked high-energy punch-through
`
`
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`
`
`implant for N-channel devices is not required; individ-
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`
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`
`
`
`ual optimization of N-channel and P-channel transistors
`
`
`
`
`
`is made possible; a lightly-doped drain (LDD) design
`
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`
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`
`
`
`for both N-channel and P-channel transistors is readily
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`
`
`implemented;
`source/drain-to-gate
`offset may be
`
`
`
`
`changed independently for N-channel and P-channel
`
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`
`
`devices; and N-channel and P-channel transistors can be
`
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`
`
`independently controlled and optimized for best LDD
`
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`
`
`performance and reliability.
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`5 Claims, 13 Drawing Sheets
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`"1 V1 V1 V1 V1 H
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`TSMC Exhibit 1017
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`Page 1 of 20
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`U.S. Patent
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`June 4, 1991
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`June 4, 1991
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`1
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`5,021,353
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`SPLIT-POLYSILICON CMOS PROCESS
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`INCORPORATING SELF-ALIGNED
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`SILICIDATION OF CONDUCIIVE REGIONS
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`FIELD OF THE INVENTION
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`This invention describes a process sequence for the
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`fabrication of Complimentary Metal Oxide Semicon-
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`ductor (hereinafter “CMOS”) integrated circuits. More
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`specifically, it relates to the fabrication of LDD transis-
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`tors of both channel types, using self-aligned silicidation
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`of gates and source/drain regions to reduce the number
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`of photomasking steps required in a split-polysilicon
`process.
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`BACKGROUND OF THE INVENTION
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`Although CMOS integrated circuit devices are often
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`referred to as “semiconductor” devices, such devices
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`are fabricated from various materials which are either
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`electrically conductive, electrically nonconductive or
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`electrically semiconductive. Silicon,
`the most com-
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`monly used semiconductor material can be made con-
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`ductive by doping it (introducing an impurity into the
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`silicon crystal structure) with either an element such as
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`boron which has one less valence electron than silicon,
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`or with an element such as phosphorus or arsenic which
`have one more valence electron than silicon. In the case
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`of boron doping, electron “holes" become the charge
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`carriers and the doped silicon is referred to as positive
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`or P-type silicon. In the case of phosphorus or arsenic
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`doping,
`the additional electrons become the charge
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`carriers and the doped silicon is referred to as negative
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`or N-type silicon. If dopants of opposite type conduc-
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`tivity are used, counter doping will result, and the con-
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`ductivity type of the most abundant impurity will pre-
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`vail. Silicon is used either in single-crystal or polycrys-
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`talline form. Polycrystalline silicon is referred to herein-
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`after as “polysilicon” or simply as “poly”. Originally,
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`MOS devices were manufactured from metal (used as
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`the transistor gate), semiconductor material (used as the
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`transistor channel material), and oxide (used as the di-
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`electric between the gate and the substrate. Currently,
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`however, most MOS transistors are fabricated using a
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`conductively-doped polycrystalline silicon layer for the
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`gate material.
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`CMOS processes begin with a lightl_y-doped P-type
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`or N-type silicon substrate, or lightly-doped epitaxial
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`silicon on a heavily doped substrate. For the sake of
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`simplicity,
`the prior art CMOS process _will be‘ de-
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`scribed using P-type silicon as the starting material. If
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`N-type silicon were used, the process steps would be
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`virtually identical, with the exception that
`in some
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`cases, dopant types would be reversed. Fabrication of
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`sub-micron CMOS devices having a silicided single
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`poly layer and a single metal layer using prior art tech-
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`nology generally requires at least 11 photoresist masks
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`(or simply “photomasks”) to create N-channel and P-
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`channel transistors on a silicon substrate (an additional
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`one or two masks is required if lightly-doped drain
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`design is required for both types of transistors). No
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`attempt is made at siliciding source and drain regions in
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`this process. The function of these ll masks is described
`below.
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`The first photoresist mask is _used to define N-wells.
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`This is done by creating a first layer of pad oxide on a
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`lightly-doped P-type substrate, depositing a layer of
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`nitride on top of the pad oxide, masking the nitride layer
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`to expose certain regions which are then implanted with
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`Page 15 of 20
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`2
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`arsenic or phosphorus to create the N-wells. The N-
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`well regions are then oxidized using a first conventional
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`LOCOS (LOCal Oxidation of Silicon) step to create a
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`silicon oxide layer to protect them from an optional
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`boron implant which adjusts the concentration of the
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`P-type substrate for the N-channel devices. During the
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`LOCOS process, the pad oxide serves as a stress relief
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`layer. Alternatively, an oxide deposition or oxide
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`growth step could replace the first LOCOS step, elimi-
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`nating the need for the first pad oxide layer and the first
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`nitride layer. A subsequent high-temperature drive step
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`is used to achieve the desired N-well junction depth.
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`Following removal of the oxide layer, a second layer of
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`pad oxide is grown over the entire wafer. A second
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`silicon nitride layer is then deposited on top of the pad
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`oxide layer.
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`The second photomask is used to pattern portions of
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`the second silicon nitride layer which define the future
`active areas on the wafer.
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`The third photomask is used to cover the N-well
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`regions in order to effect a selective boron field-isola-
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`tion implant. Following the stripping of the third photo-
`mask, the regions on the wafer that are not protected by
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`the remaining portions of the second silicon nitride
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`layer are oxidized to form field oxide regions using a
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`second conventional LOCOS step. The nitride layer is
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`then stripped, as is the pad oxide layer. A layer of sacri-
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`ficial oxide is then grown to eliminate the “white rib-
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`bon” or Kooi effect in the active areas that follows field
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`oxidation. An unmasked implant may be used as a
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`threshold voltage (V7-) adjustment.
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`The fourth photomask exposes only the channel re-
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`gions of the N-channel
`transistors to a high-energy
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`boron punch-through implant. This implant increases
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`both source-to-drain breakdown voltage and the thresh-
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`old voltage,
`thus avoiding the short-channel effects
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`which are inherent to nonimplanted, sub-micron N-
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`channel devices. Following the punch-through implant,
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`the fourth photomask is stripped, as is the sacrificial
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`oxide layer. A layer of gate oxide is then grown on all
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`active areas, following which a polysilicon layer is de-
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`posited on top of the gate oxide using conventional
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`means (e.g., chemical vapor deposition). The poly layer
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`is then doped with phosphorus, coated with a layer of
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`tungsten silicide by various possible techniques (e.g.,
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`chemical vapor deposition, sputtering, or evaporation).
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`The fifth photomask patterns the silicide-coated
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`polysilicon layer to form the gates of both P-channel
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`and N-channel transistors. Stripping of the fifth photo-
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`mask is followed by a source/drain oxidation.
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`The sixth photomask is used to expose only the N-
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`channel source and drain regions to a relatively low-
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`dosage phosphorus implant which creates lightly-doped
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`N- regions. Following the stripping of the sixth mask, a
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`layer of silicon dioxide is deposited on the wafer. An
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`anisotropic etch and a subsequent optional isotropic
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`etch of the silicon dioxide layer leave oxide spacers on
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`the sides of each N-channel and P-channel transistor
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`gate.
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`the N-channel
`The seventh photomask exposes
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`source and drain regions to a relatively high-dosage
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`phosphorus or- arsenic implant which creates the heavi-
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`ly-doped N+regions. Following the stripping of the '
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`seventh mask, the wafer is optionally subjected to ele-
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`vated temperature for the purpose of diffusing the N-
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`channel implants.
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`Page 15 of 20
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`3
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`The eighth photomask is used for the high-dosage
`implantation of either boron or boron difluoride, which ~
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`creates heavily doped source and drain regions for the
`P-channel transistors. Following the stripping of the
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`eighth mask, an elevated-temperature drive step is per-
`formed, after which the transistors are fully formed. All
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`structures are then covered by an isolation oxide layer.
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`The ninth photomask is used to define contact vias
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`which will pass through the isolation oxide layer to the
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`poly structures or active area conductive regions be-
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`low. A deposition of an aluminum metal layer follows.
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`The tenth photomask is used to pattern the aluminum
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`layer for circuit interconnects. Using a blanket deposi-
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`tion process, the circuitry is covered with one or more
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`passivation layers.
`’
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`The eleventh photomask defines bonding pad open-
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`ings which will expose bonding pad regions on the
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`aluminum layer below. This completes the conventional
`single-poly, single-metal CMOS process.
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`The business of producing CMOS semiconductor
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`devices is a very competitive, high-volume business.
`Process efficiency and manufacturability, as well as
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`product quality, reliability, and performance are the key
`factors that will determine the economic success or
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`failure of such a venture. Each new generation of 25
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`CMOS devices is expected to be faster and more com-
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`pact than the generation it replaces. Four-fold density
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`increases from one generation to the next have become
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`standard. If this increase in density is achieved with no
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`increase in die size, device geometries must be more or
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`less halved. As geometries shrink, each photolitho-
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`graphic step becomes more costly. The increase and
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`cost may be attributed to a number of factors, including:
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`higher capital costs for precision “state-of—the-art"
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`photolithographic equipment;
`lowered yields and decreased reliability due to defect
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`density increases invariably associated with each photo-
`masking step;
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`an increase in the number of processing steps for each
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`mask level, which slows the fabrication process and
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`requires additional expensive equipment;
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`the requirement for ultra-clean fabrication facilities
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`which are both expensive to construct and expensive to
`operate;
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`greater investment per wafer during fabrication,
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`which increases the cost of scrapping defective devices;
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`and
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`costs associated with the step required subsequent to
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`the masking step, whether it be an implant or an etch.
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`From the aforementioned discussion, it is evident that
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`the elimination of photomasking steps from a CMOS
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`process will have a direct impact on the cost, reliability,
`
`and manufacturability of the product.
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`A novel process is disclosed in the l982 Japanese
`patent issued to Masahide Ogawa (No. 57-17164) for
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`fabricating a CMOS integrated circuit by processing
`
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`N-channel and P-channel devices separately. As with
`
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`the conventional CMOS process, «a single polysilicon
`layer is used to form both N-channel and P-channel
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`gates. However, N-channel devices are formed first,
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`with unetched polysilicon left in the future P-channel
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`regions until N-channel processing is complete. The
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`mask used to subsequently pattern the P-channel de-
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`vices is "also used to blanket and protect the already-
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`formed N-channel devices. This process is herein re-
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`ferred to as the split-polysilicon CMOS process. The
`
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`spilt-polysilicon CMOS process,
`through largely ig-
`nored by semiconductor manufacturers in the U.S. and
`
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`45
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`5
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`10
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`15
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`20
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`30
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`35
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`50
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`65
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`5,021,353
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`4
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`abroad, holds tremendous potential for reducing photo-
`
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`masking steps in a CMOS process.
`
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`A pending U.S. Pat. No. 7/427,639, submitted by
`
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`Tyler A. Lowrey, Randal W. Chance, and Ward D.
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`Parkinson of Micron Technology, Inc. of Boise, Id.
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`details an improved split-polysilicon CMOS process.
`
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`The improved CMOS fabrication process is based on
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`the aforementioned split-polysilicon CMOS process
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`developed in Japan by Mashahide Ogawa. The im-
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`proved process utilizes an unmasked N-channel punch-
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`through implant and unmasked N-channel source/drain
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`implants that are self-aligned to gate electrodes to cre-
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`ate high-perfonnance LDD-type N-channel transistors.
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`These high-performance transistors have both punch-
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`through regions and LDD-type source/drain regions.
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`By utilizing the split-polysilicon CMOS process in com-
`bination with the unmasked implants, the number of
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`masks required to form both N-channel and P-channel
`devices can be reduced from eleven (for the standard
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`CMOS process) to eight (for the improved process).
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`P-channel source and drain regions, although of con-
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`ventional non-LDD design, are offset from the edges of
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`the P-channel gates by undercutting the gates beneath
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`the photoresist during the gate-patterning etch. The
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`gate-patterning photoresist is then used as an offsetting
`implant mask.
`
`
`SUMMARY OF THE INVENTION
`
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`The object of the present invention is to reduce the
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`cost and improve the reliability, performance and
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`manufacturability of CMOS devices by implementing a
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`variation of the improved split-polysilicon CMOS fabri-
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`cation process developed by Mssrs. Lowrey, Chance
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`and Parkinson which provides LDd sources and drains
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`for both N-channel and P-channel transistors with no
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`increase in the number of photomasking steps, and in-
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`corporates self-aligned silicidation of transistor gates,
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`sources and drains. Like the original Micron-developed
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`improved split-polysilicon CMOS process,
`the new
`
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`split-polysilicon silicide process, which is the focus of
`
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`the present invention, also utilizes eight masks to fabri-
`cate both types of transistors. The function of each of
`
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`the eight required photomasks is described below. For
`
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`the sake of simplicity,
`the process will be described
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`
`using P-type silicon as the starting material. If N-type
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`silicon were used, thepprocess steps would be virtually
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`identical, with the exception that dopant types would be
`reversed in some cases.
`
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`The first photomask is used to form the N-well re-
`gions in a conventional manner.
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`The second photomask is used to conventionally
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`define the active areas by patterning a nitride layer.
`The third photomask is used to cover the N-well
`
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`regions in order to effect the boron field isolation im-
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`plant, also in accordance with conventional CMOS
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`technology. Following the stripping of the third mask,
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`LOCOS is used to grow the field oxide regions, and an
`
`
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`
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`unmasked boron implant is used as a transistor threshold
`
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`
`
`enhancement. The use of a masked punch-through im-
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`plant at this point is not required. Following the deposi-
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`tion and doping with phosphorus of a polysilicon layer,
`the process further deviates from convention.
`'
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`The fourth photomask is used to pattern the gates of
`the N-channel transistors and to cover the P-channel
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`regions. An anisotropic dry etch is used to form the
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`N-channel transistor gates, following which the fourth -
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`mask photoresist is stripped. Following an unmasked
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`self-aligned boron punch-through implant, a source/-
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`Page 16 of 20
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`Page 16 of 20
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`all unreacted titanium as well as titanium nitride. This
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`self-aligned siliciding step greating improves the speed
`of both N-channel and P-channel devices.
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`At this point, transistor formation using the improved
`CMOS process is complete.
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`The sixth, seventh, and eighth photomasks are used to
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`complete the circuitry in a conventional manner, and
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`correspond respectively to the ninth, tenth, and elev-
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`enth photomasks utilized for the previously-described
`conventional process.
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`The improved CMOS process provides the following
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`advantages over conventional process technology:
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`It permits a dramatic reduction in the number of
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`photomasking steps required in a modern high density
`CMOS process;
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`It is applicable to both low and high density (sub-
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`micron) integration levels;
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`Use of a masked high-energy boron punchthrough
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`implant for N-channel transistors is not required (a un-
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`masked self-aligned implant after polysilicon deposition
`is used instead);
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`Individual optimization of N-channel and P-channel
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`transistors is made possible;
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`It allows lightly-doped drain (LDD) design for both
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`N-channel and P-channel transistors (the LDD design
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`makes possible a significant reduction in device length
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`without incurring the detrimental “short channel” ef-
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`fects seen with conventional transistor design, in addi-
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`tion to greatly reducing high electric field hot-electron
`effects);
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`Offset distance of source/drain implants are easily
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`changed independently for N-channel and P-channel
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`devices, allowing greater flexibility for device optimiza-
`tion;
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`The N-channel and P-channel transistors can be inde-
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`pendently controlled and optimized for best LDD per-
`formance and reliability (this fact allows maximum
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`shrinkablity for subsequent generation products and
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`reduces retooling for changes in N-channel or P-chan-
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`nel transistors);
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`It is compatible with contemporary IC fabrication
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`equipment, and requires no exotic new equipment;
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`Self-aligned siliciding of all transistor gates, sources
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`and drains is accomplished without adding any masking
`steps; and
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`The reduced number of process steps and reduced
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`mask count
`improves electrical sort yields, reduces
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`manufacturing costs,
`increases productivity, reduces
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`cycle times through fabrication, reduces total process
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`inventory needed for a given run rate, allows more
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`rapid response to process changes in volume quantities,
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`and provides more products having less variation.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`The drawing Figures each show cross-sections of a
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`portion of a semiconductor circuit device which utilizes
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`the present invention.
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`FIG. 1 shows a lightly-doped P-type silicon substrate
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`being implanted with phosphorus to create a well of
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`N-type silicon following the growth of a first layer of
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`pad oxide, deposition of a first silicon -nitride layer,
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`masking of the first silicon nitride layer with a first
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`photoresist mask and etching of the silicon nitride layer;
`FIG. 2 shows the semiconductor device of FIG. 1
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`being subjected to an optional P-type substrate boron
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`adjustment implant following a high temperature step
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`’ which has caused the N-well phosphorus implant to
`diffuse into the substrate, oxidation of silicon in the
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`drain oxidation is performed. A low-dosage unmasked
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`phosphorus implant then creates the lightly-doped N-
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`regions of the N-channel sources and drains. Spacer
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`oxide deposition is followed by an anisotropic dry etch
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`and an optional isotropic etch (in that order), which
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`leave spacers on both sides of the N-channel gates.
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`Spacer formation is followed by a high-dosage un-
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`mas_ked phosphorus or arsenic implant, which creates
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`the heavily-doped N+ regions of the N-channel
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`sources and drains. Doping of the poly layer in the
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`P-channel regions with the aforementioned N-channel
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`implants will have essentially no effect on P-channel
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`transistor performance, since only the gate is doped,
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`with the future source and drain regions remaining
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`untouched. Since the gate poly is doped n-type anyway,
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`there is no electrical impact on P-channel transistors.
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`The fifth photomask is used to pattern the gates of the
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`P-channel transistors and to cover the N-channel re-
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`gions.
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`An anisotropic etch is used to etch the P-channel
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`transistor gates. A low-dosage boron implant may then
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`be optionally performed in the regions not protected by
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`the fifth photomask, thus creating lightly-doped sources
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`and drains for the P-channel devices. Removal of the
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`fifth photomask is followed by the blanket deposition of
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`"a spacer oxide layer, which is anisotropically etched
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`(and optionally subsequently isotropically etched) to
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`create spacers on both sides of the P-channel gates.
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`P-channel spacer formation is followed by a boron or
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`boron-defluoride high-dosage unmasked implant, thus
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`creating heavily-doped sources and drains for the P-
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`channel devices. Since the dosage of the boron-difluo-
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`ride implant is only approximately one-third to one-sev-
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`enth the dosage of the arsenic implants used to create
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`the source/drain regions for the N-channel devices,
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`performance of the N-channel devices remains largely
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`unaffected by the partial counter-doping of the N-chan-
`nel source/drain regions.
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`A second embodiment of the invention allows P-
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`channel transistor gates to be created by an isotropic
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`dry etch with the fifth photomask in place. The fifth
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`photomask patterns the P-channel transistor gates, and
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`the isotropic dry etch produces gates,
`the edges of
`which are purposely undercut (recessed) under the
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`patterning photoresist. After the etch, and with the fifth
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`photomask still in place, a high-dosage boron or boron
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`difluorideimplant is used to create P-channel sources
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`and drains. The undercut P-channel gate offsets the
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`high-dosage P-channel source/drain implant such that
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`implant diffusion related to subsequent
`temperature
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`steps does not result in excessive gate overlap by these
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`implants. Using only a single P-channel source/drain
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`implant eliminates the problem of counter-doping of the
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`N-channel source/drain regions, since all N-channel
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`devices are