1
`
`PATENT OWNER’S
`DEMONSTRATIVE EXHIBIT
`
`Case IPR2016-01246
`
`August 7, 2017
`
`IP Bridge Exhibit 2079
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`PATENT OWNER’S
`DEMONSTRATIVE EXHIBIT
`
`Case IPR2016-01246
`
`August 7, 2017
`
`IP Bridge Exhibit 2079
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`2
`
`Institution Decision, Paper 8, p. 17-18
`
`
`
`3
`
`Institution Decision, Paper 8, pp. 25-26
`
`
`
`4
`
`Institution Decision, Paper 8, p. 26
`
`
`
`5
`
`FIG. 15°
`
`
`
`Substrate (Si)
`Trench Isolation (SiO,)
`Conductor(poly-Si, Al, Au, W,silicide, etc.)
`Gate Electrode/Interconnection(poly-Si)
`Protective Nitride (Si,N, or SiON)
`
`Spacer(SiO,)
`Spacer(Si,N, or SiON)
`Gate Oxide (SiO,)
`Optional Silicide
`Petitioner’s Reply, Paper 21, p. 20
`Optional LDD Source/Drain
`
`
`
`6
`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`6:46-61, FIG. 11. To substitute Nob/e’s and Ogawa’s STI structures for Lee’s
`
`LOCOSisolation, a POSITA would havefirst made raised STI, removing the
`
`polish/etch-stop and pad oxide, and formed the gate stack. EX1057, 979-83. IPB
`
`provides no basis for asserting a POSITA would haveretained the polish/etch-stop
`
`and pad oxide as the gate stack. That assertion makes no sense because,as the
`
`following figures illustrate, removing those features makes trivial the substitution,
`
`TSMCdescribed in its Petitions. EX1057, (€80-83; Paper 2, at 21, 70.
`
`FIG.
`
`11
`
`‘Lee FIG. 11
`
`Modified Lee FIG. 11
`
`
`
`InsteadofLOCOS,raisedSTI113isformedbyanyofthewell-known
`
`
`
`(processesdiscussedabove)7a.Then,as in Lee, gate oxide 115, polysilicon 117,
`
`and silicon nitride/silicon oxynitride layer 118 are successively deposited.
`
`EX1057, 483.
`
`
` Petitioner’s Reply, Paper 21, p. 19
`
`Petitioner’s Reply, Paper 21, p. 19
`
`
`
`
`
`7
`
`
`
` SWUS
`
`
`LLL DUYVNs,7
`
`Exhibit 1002, Lee, Fig. 4
`
`
`
`8
`
`
`
`Insufficient diffusion
`
`inadequately controlled diffusion
`
`Excessive diffusion
`
`
`
`is Inversion channel will not form
`in regions indicated above.
`Device will be non-functional.
`
`Given that there are millions of transistors
`on a Si IC device, individual transistors
`may work, but not the SiIC in its entirety.
`Device will be non-functional.
`
`Channel length willbe
`too short (punch-througheffect).
`Device will be non-functional.
`
`[1] Double arrows representvariationin diffusion, Al piusion: this quantity is inherently long because Lpisysion iS long.
`Patent Owner’s Sur-Reply, Paper 37, p. 15
`
`
`
`9
`
`(a) Lee doping sequence:
`First deep, then ©°9 ow implant.
`
`Gate stack depostion and formation of 3 SWs:
`
`
`
`Deep implant:
`
`Hyddb bedded dt
`
`=
`
`(b) ’174 doping sequence:
`First soa) ow, then deep implant.
`
`Gate stack deposition:
`
`Shallow implant:
`
`beddddddddddd
`|] |
`|
`|
`
`3rd SW removalfollowed by s!'o!low Imm ent:
`
`SW formation followed by deep implant:
`
`Peed bedded dt
`
`}
`{ Advantage: (1) Minimal diffusion required, (2)
`' Minimal variations, (3) Shallow junctions. > }
`{Suitable for 250-350 nm nodes used with STI.
`J
`
`Patent Owner’s Sur-Reply, Paper 37, p. 18
`
`Wyyeeeeeea eee
`
`em)ponsee
`
`
`=1
`
`1) f
`
`
`
`(1) Undoped region below SW is problematic
`
`Post-implantation annealing:
`
`ada
`
`a
`Ewes,
`rrrnenernenaeeereneeeennnennnnenne
`(2)
`' Problem:
`(1) Excessive diffusion required,
`| Inherent process variations, (3) Deeper junctions.
`> Unsuitable for 250-350 nm nodes used with svi.}
`
`
`
`10
`
`Segawa/’174 Patent
`
`Patent Owner’s Response, Paper 14, p. 18
`Exhibit 1001, ‘174 Patent, Fig. 15(d)
`
`
`
`11
`
`Segawa (‘174 Patent)
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 17;
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 19
`Patent Owner’s Response, Paper 14, p. 15
`Exhibit 1001, ‘174 Patent, Fig. 15(f)
`
`
`
`Segawa/‘174 Patent
`
`12
`
`Patent Owner’s Response, Paper 14, p. 49
`Exhibit 1001, ‘174 Patent, Fig. 17
`
`
`
`13
`
`Patent Owner’s Sur-Reply, Paper 37, p. 21
`Exhibit 1002, Lee, Fig. 6 (Modified)
`
`
`
`14
`
`Lee
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 21;
`Patent Owner’s Response, Paper 14, p. 21
`Exhibit 1002, Lee, Fig. 1
`
`
`
`15
`
`Lee
`
`Patent Owner’s Sur-Reply, Paper 37, p. 12
`Exhibit 1002, Lee, Fig. 5
`
`
`
`16
`
`Lee
`
`Patent Owner’s Sur-Reply, Paper 37, p. 13
`Exhibit 1002, Lee, Fig. 6
`
`
`
`17
`
`Lee
`
`Patent Owner’s Response, Paper 14, pp. 25, 45, 51
`Exhibit 1002, Lee, Fig. 11
`
`
`
`18
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 67
`Exhibit 1002, Lee, Fig. 12
`
`
`
`19
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 46
`Exhibit 1002, Lee, Fig. 12
`
`
`
`20
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 53
`Exhibit 1002, Lee, Fig. 12
`
`
`
`21
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 26
`Exhibit 1002, Lee, Fig. 13
`
`
`
`22
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 80
`Exhibit 1002, Lee, Fig. 14
`
`
`
`23
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 82
`Exhibit 1002, Lee, Fig. 15
`
`
`
`24
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 26
`Exhibit 1002, Lee, Fig. 15
`
`
`
`25
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 52
`Exhibit 1002, Lee, Fig. 15
`
`
`
`26
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 71
`Exhibit 1002, Lee, Fig. 15
`
`
`
`27
`
`Lee
`
`Patent Owner’s Response, Paper 14, p. 79
`Exhibit 1002, Lee, Fig. 15
`
`
`
`28
`
`Noble
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 28
`Patent Owner’s Response, Paper 14, pp. 45, 55, 105
`Exhibit 1015, Noble, Fig. 9
`
`
`
`29
`
`Noble
`
`Patent Owner’s Response, Paper 14, p. 55
`Exhibit 1015, Noble, Fig. 10
`
`
`
`30
`
`Noble
`
`Patent Owner’s Response, Paper 14, p. 56
`Exhibit 1015, Noble, Fig. 11
`
`
`
`31
`
`Noble
`
`Patent Owner’s Response, Paper 14, p. 47
`Exhibit 1015, Noble, Fig. 11
`
`
`
`32
`
`Noble
`
`Patent Owner’s Response, Paper 14, pp. 37, 65
`Exhibit 1015, Noble, Fig. 11
`
`
`
`33
`
`Patent Owner’s Response, Paper 14, p. 114
`Exhibit 1015, Noble, Fig. 11
`
`
`
`34
`
`Ogawa
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 43
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 44
`Exhibit 1010, Ogawa, Figs. 4(a) and 4(b)
`
`
`
`35
`
`Ogawa
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 44
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 45
`Exhibit 1010, Ogawa, Fig. 4(c)
`
`
`
`Ogawa
`
`36
`
`Patent Owner’s Response, Paper 14, p. 62
`Exhibit 1010, Ogawa, Figs. 5(a)-(c)
`
`
`
`Ogawa
`
`37
`
`Patent Owner’s Response, Paper 14, p. 109
`Exhibit 1010, Ogawa, Figs. 5(a)-(c)
`
`
`
`38
`
`Ogawa
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 49
`Exhibit 1010, Ogawa, Fig. 5(b)
`
`
`
`39
`
`Ogawa
`
`Patent Owner’s Response, Paper 14, p. 66
`Exhibit 1010, Ogawa, Fig. 5(b)
`
`
`
`40
`
`Ogawa
`
`Patent Owner’s Response, Paper 14, p. 76
`Exhibit 1010, Ogawa, Fig. 5(b)
`
`
`
`41
`
`Patent Owner’s Response, Paper 14, p. 113
`Exhibit 1010, Ogawa, Fig. 5(b)
`
`
`
`42
`
`Ogawa
`
`Patent Owner’s Response, Paper 14, pp. 60, 107
`Exhibit 1010, Ogawa, Fig. 5(c)
`
`
`
`43
`
`Ogawa
`
`Patent Owner’s Response, Paper 14, p. 117
`Exhibit 1010, Ogawa, Fig. 5(c)
`
`
`
`44
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 29
`Patent Owner’s Sur-Reply, Paper 37, pp. 25, 37
`Exhibit 1017, Lowrey, Fig. 1
`
`
`
`45
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 30
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 2
`
`
`
`46
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 31
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 3
`
`
`
`47
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, pp. 32, 35
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`48
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 96
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`49
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 39
`Patent Owner’s Response, Paper 14, p. 101
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`50
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 39
`Patent Owner’s Response, Paper 14, p. 101
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`51
`
`Lowrey
`
`Patent Owner’s Sur-Reply, Paper 37, p. 27
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`52
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, pp. 33, 36
`Patent Owner’s Response, Paper 14, pp. 28, 31
`Exhibit 1017, Lowrey, Fig. 5
`
`
`
`53
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 40
`Exhibit 1017, Lowrey, Fig. 5
`
`
`
`54
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 97
`Exhibit 1017, Lowrey, Fig. 5
`
`
`
`55
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 98
`Exhibit 1017, Lowrey, Fig. 7
`
`
`
`56
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 29
`Exhibit 1017, Lowrey, Fig. 7
`
`
`
`57
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 30
`Exhibit 1017, Lowrey, Fig. 8
`
`
`
`58
`
`Patent Owner’s Response, Paper 14, p. 113
`Exhibit 1017, Lowrey, Fig. 8
`
`
`
`59
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 99
`Exhibit 1017, Lowrey, Fig. 8
`
`
`
`60
`
`Petitioner’s Reply, Paper 21, p. 21, 23
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`
`
`
`61
`
`Petitioner’s Reply, Paper 21, p. 21
`Patent Owner’s Sur-Reply, Paper 37, p. 25, 26
`
`
`
`62
`
`Petitioner’s Reply, Paper 21, p. 21, 23
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`
`
`
`
`
`ee
`PCTS
`
`
`
`
`
`
`
`63
`
`
`
`
`
`
`
`
`Patent Owner’s Sur-Reply, Paper 37, p. 26
`
`ener
`ET PEL ETAT S EL ES
`
`
`MMA
`
`
`
`
`
`64
`
`Petitioner’s Reply, Paper 21, p. 24
`Patent Owner’s Sur-Reply, Paper 37, p. 26
`
`
`
`
`
`65
`
`Lowrey with Noble/Ogawa:
`
`
`PolySi
`} 802Ved
`
`
`Leakage current
`~path>—\.
`nN
`
`
`Channel stopper
`(p-type Aytal
`
`Corner/step > Non-uniformity > Higher electric fields
`—> Greater leakage current
`
`Patent Owner’s Sur-Reply, Paper 37, p. 29
`
`
`
`66
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
`
`
`
`67
`
`Pad oxide (SiO>)
`
`Nitride (Si3N,4)
`
`Photo-resist
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31
`
`
`
`68
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
`
`69
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
`
` é
`ioLE=yyi,
`
`/ xkeanelevels
`; Ageeesaseeoa/
`
`
`
`
`*
`
`70
`
`
`
`Patent Owner’s Sur-Reply, Paper 37, p. 33
`
`
`
`
`
`71
`
`yes in height/level
`
`
`
`Nitride Removal
`
`Patent Owner’s Sur-Reply, Paper 37, p. 34
`
`
`
`72
`
`for microclectronic circuits, pri-
`Silicon is the dominant material
`marily because of the ease with which it oxidizes to form insulating barriers
`for the subsequent
`implanting of tiny amounts of dopants into selected
`regions to achieve the requisite electrical properties. The silicon dioxide
`insulator and other dielectric films that are commonly encountered such as
`silicon nitride films are patterned by a process known as photolithography.
`Photolithography is probably the key process in microelectronic fabrication
`technology, becauseit is repeated 5 — 12 times before the three-dimensional
`circuit geometries necessary for a completed metal oxide semiconductor
`(MOS) or bipolar device are achieved. Figure 4 is an outline of the
`manufacturing sequence of a large-scale integrated circuit and illustrates the
`importance of understanding the lithographic technology used to delineate
`the patterns of thin-film dielectrics and conductors. The structure of an
`integrated circuit is complex both in the topography of its surface and in its
`internal composition. Each element of such a device has an intricate three-
`dimensional architecture that must be reproduced exactly in every circuit.
`The structure is made up of many layers, each of which is a detailed pat-
`tern. Some of the layers lie within the silicon wafer and others are stacked
`Patent Owner’s Response, Paper 14, p. 13
`on the top. The manufacturing process consists in forming this sequence of
`Exhibit 2013, p. 5
`layers precisely in accordance with the plan of the circuit designer.
`
`
`
`73
`
`This photolithography process is reneated (to more than 10 cimes) before
`
`the three-dimensional circuit geometries necessary for a completed metal oxide
`
`semiconductor (MOS) or bipolar device are achieved. The structure of an
`
`integrated circuit is complex, both in the topography of its surface and in
`its internal composition. Each element of this device has an intricate three-
`
`dimensional structure that must be reproduced exactly in every circuit. The
`
`Structure is made up of many layers, each of which is a detailed pattern. Some
`
`of the layers lie within the silicon wafer and others are stacked on the top.
`
`The process is described in detail in the book of L.F. THOMPSON, C.G. WILLSON
`
`and M.J. BOWDEN “Introduction to Microlithography", American Chemical Society
`
`Symposium Series 219, Amer.Chem.Soc., Washington D.C., 1983.
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2014, p. 4
`
`
`
`74
`
`Since semiconductor devices are becoming more
`complex in structure and materials, and since the CMP
`planarization process is dependent on structure and
`materials, apparatus and techniques that permit
`the
`59 fabrication engineer to control and design the CMP
`process would be highly desirable.
`Generally, a change in one phase of the integrated
`fabrication process usually impacts other phases. Since
`integrated circuit fabrication processes are highly com-
`$5 plex and require sophisticated equipment, developments
`of entirely new processes and materials can be quite
`costly. Thus new apparatus and methods for control of
`the CMP process that can be incorporatedinto current
`fabrication technology would be highly desirable be-
`60 Cause expensive modification of equipment and pro-
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2015, 2:52-61
`cesses can be avoided.
`
`
`
`75
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2016, 2:19-24
`
`5
`
`2
`aspect ratios; thatis, they become deeper and narrower.
`Conventional deposition techniques, e.g. sputtering,
`have difficulty coating such deep, narrow recesses,
`because the atoms tend to contact one of the walls be-
`fore reaching the bottom of the recess. Thus, with re-
`spect to diffusion barriers, the use of conventional pro-
`duction techniques, such as sputtering, leads to a de-
`crease in the thickness ofthe diffusion barrier at the base
`of a contactas the aspect ratio increases. As the thick-
`10 ness of the diffusion barrier decreases, the ability of the
`diffusion barrier to withstand thermal energy intro-
`duced in subsequent processing decreases, and thereli-
`ability of the device degrades. Thus there has been an
`impetus in the industry toward new barrier technology
`15 that will deposit an adequate barrier in high aspectratio
`contacts, which impetus has tended toward the devel-
`opment of equipment and materials not presently used
`in semiconductor device fabrication. Generally, a
`ad change in one phase ofthe fabrication process mae
`impacts other phases. Sincesemiconductor device fabri-
`cation processes are highly complex and require sophis-
`ticated equipment, developments or entirely new o
`and materials can be quite costly. Thus a
`diffusion barrier that is more effective and yet can be
`incorporated into currentfabrication technology would
`be highly desirable because expensive modification of
`equipmentand processes can be avoided.
`
`2 Ww
`
`
`
`76
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2017, 6:23-31
`
`5
`
`6
`above) using diffusion or ion implantation techniquesin
`order to generate p-n junctions which form active semi-
`conductor devices such as diodes or transistors.
`Finally, various types of processes (called “metalliza-
`tion”) can be used to produce the interconnecting wir-
`ing pattern between the various circuit elements which
`form the integrated circuit. Wiring patterns can be
`formed on the wafer using flash evaporation, filament
`evaporation, ¢lectron-beam evaporation, planar and
`10 cylindrical sputtering, or induction evaporation meth-
`ods.
`3. Etching-Masking Processes
`in selective
`The etching-masking processes result
`removal or addition of the deposited or grown layers of
`15 semiconductive or passivation materials in accordance
`with the patterned geometry which defines the inte-
`grated circuit clements. The etching-masking steps can
`be accomplished in a variety of ways, depending upon
`the particular type of material that is to be masked or
`20 etched. Materials commonly used in the etching-mask-
`ing steps are silicon dioxide, doped silicon dioxide,
`polysilicon, silicon nitride, metals and polyimide.
`pre liga highly complex imaging, deposi
`growth,
`etching-masking processes 1s
`25 transformation of each substrate into a large number of
`integrated circuits which may contain literally tens or
`Saf osovern algege eoror
`Processes are completed, each wafer
`scribed and diced so as to separate it into individual
`30 integrated circuits or chips, to which wire leads are then
`bonded prior to final encapsulation and packaging.
`
`
`
`77
`
`1
`
`INTEGRATED CIRCUIT MICRO-FABRICATION
`USING DRY LITHOGRAPHIC PROCESSES
`
`The United States Government has rights in this 5
`invention pursuant to the Department of Air Force
`Contract No. F19628-85-C-0002.
`This application is a continuation of application Ser.
`No. 07/514,394, filed Apr. 27, 1990, now abandoned
`which is a continuation of application Ser. No. 10
`07/149,426, filed Jan. 29, 1988, now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`This invention generally relates to micro-fabrication
`of integrated circuits and, particularly, to an improved !5
`process and apparatus for pattern formation on semi-
`conductor wafers to form such circuits.
`Within the semiconductor industry, production of
`electronic circuits by very
`scale integration
`(“VLSI”) techniques is constrained by a variety of fac- 2°
`tors which limit yield and inhibit process flexibility.
`These detrimental] factors include, for example, the
`exposure of wafers to contaminants and/or oxidation
`during fabrication. Such processing constraints ad- ,
`versely affect mass production ofintegrated circuits. In 79
`addition, conventional processes are slow and inordi-
`nately expensive for the fabrication of low-volume
`products, thus posing an impediment to new device and
`circuit designs.
`30
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2018, 1:18-29
`
`
`
`78
`
`2
`mask. A layer of metal or other suitable conductor is
`then deposited onto portions of the exposed areas of the
`semiconductor wafer to form the desired interconnec-
`tions between components on the wafer. Though there
`5 are many fabrication technologies, fabrication tech-
`niques, and integrated circuit materials, fabricating the
`design for the integrated circuit through one or more
`masks is used consistently.
`10 Depending on the fabrication technologies and tech-
`niques, and the materials used, different configuration
`constraints apply. These constraints are commonly re-
`ferred to as “geometric design rules” or “design rules.”
`Design rules include, for example, specifications for
`15 minimum spacing between transistors and minimum
`separation between conductors to prevent shorting,
`specifications for minimum metal width, and specifica-
`tions for maximum metal heights and slopes of walls
`which form metal junctions.
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2019, 2:9-19
`
`
`
`79
`
`Patent Owner’s Response, Paper 14, p. 34
`Adapted from Exhibit 2022, Bryant, p. 413
`
`
`
`80
`
`Patent Owner’s Response, Paper 14, pp. 63, 77
`
`
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