`
`
`
`Patent Owner’s Response, Paper 14, p. 119
`
`
`
`82
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 30
`
`
`
`Noble/Ogawa
`
`83
`
`Gate electrode and gate
`dielectric extend across
`
`Patent Owner’s Response, Paper 14, p. 111
`
`lly
`
`'
`am; me
`
`~-* interconnect
`gate stack
`stack
`
`GR conductive wiring level (metalsilicide)
`
`Only the wiring
`layer goes across
`
`'
`
`SeWolefOeawa
`
`interconnect
`stack
`
`Noble/Ogawa
`gate stack
`
`|__| Isolation oxide (Si02)_ |) Gate conductor (poly-silicon)
`PO Gate dielectric
`
`[
`
`Si substrate
`
`
`
`
`Top view
`B‘
`
`Inter-
`connect
`
`
`
`
`
`
`Gate width
`direction
`
`Arcpeas—o----:
`
`--A
`
`Silicon substrate
`
`AA crosssectional view
`
`
`
`Noble
`
`BB cross sectional view
`
`84
`
`st
`
`Patent Owner’s Response, Paper 14, p. 54
`
`gate stack
`
`
`
`[| Isolation oxide [] Gate conductor
`[ Gate dielectric [4 Conductive wiring
`
`
`
`
`1st
`edge
`
`
`
`Si substrate
`
`
`
`edge
`
`
`
`
`
`85
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 38
`
`
`
`86
`
`Process sequence forming the Noble gate stack and interconnect:
`
`Gate stack deposition / growth:
`[NGote conductor (eg. potyi
`Gate dielectric (e.g. SiO>)
`
`Silicon substrate
`
`Trench etching:
`
`Silicon substrate
`
`Oxide deposition (trench re-fill):
`
`
`
`Silicon substrate
`
`Planarization (e.g. by CMP):
`
`Silicon substrate
`
`Noble gate and interconnection:
`
`Silicon substrate
`
`Highly conductive layer (e.g. metal)
`Gate conductor(e.g. poly-Si)
`Gate dielectric (e.g. SiOz)
`
`Patent Owner’s Response, Paper 14, p. 74
`
`
`
`87
`
`Cross section along gate length and width direction:
`
`Interconnection
`(wiring layer)
`
`Gate conductor
`
`
`
`Silicon substrate
`
`Patent Owner’s Response, Paper 14, pp. 58, 76
`
`
`
`
`
`88
`
`Cross section along gate length direction:
`
`Interconnection
`
`Gate stack
`
`L
`
`Silicon substrate
`
`Patent Owner’s Response, Paper 14, p. 75
`
`
`
`
`
`89
`
`Anisotropic etching:
`
`Y Second sidewall
`
`
`
`Silicon substrate
`
`Patent Owner’s Response, Paper 14, p. 77
`
`
`
`90
`
`Patent Owner’s Response, Paper 14, p. 78
`
`
`
`91
`
`&
`
`Light source
`
`ff Mask
`
`Lens to reduce image
`
`
`aaae
`aEiio heTae
`
`
`
`Seeeenteeeneree Die being exposed on wafer
`
`
`Seee
`
`
`
`
`Patent Owner’s Sur-Reply, Paper 37, p. 35
`
`
`
`
`
`92
`
`Gate 1
`
`hh
`Supply voltage
`
`p-channel
`
`Vin Vout>The transistors
`
`:
`are in an electrical
`er:
`wdlienndl
`series circuit
`
`Vdd
`
`
`
`Gate 2
`
`Ground
`
`Ff
`
`Patent Owner’s Sur-Reply, Paper 37, p. 38
`
`
`
`93
`
`Lee
`
`a L
`
`ee
`
`Nowthat formation of s nested double or triple layer 45
`spacer has been described. a variety of applications of
`the inventive structure together with alternative em-
`bodiments and their advantages will be described.
`FIGS. $-7 ilusirate howthe inventive concept may
`now be utilized to form a lightly-doped drain structure. 50
`
`that gate 18 Nanked by spacers 19, 21, and 23 effectively 60
`mask portions 28 and 30 of substrate 11 from implanta-
`tion species 31. (If layer 19 has not been etched, it may
`serve to protect surface 26 during the implantation step.
`eee
`
`ee 27. In cach case spacers 21, 23 (and
`
`Exhibit 1002, Lee, 3:49-4:33
`
`
`
`94
`
`Exhibit 1002, Lee, 3:49-4:33 (continued from previous page)
`
`
`
`Lowrey
`
`Lowrey
`
`2
`arsenic or phosphorus to create the N-wells. The N-
`well regions are then oxidized using a first conventional
`LOCOS (LOCal Oxidation of Silicon) step to create a
`silicon oxide layer to protect them from an optional
`boron implant which adjusts the concentration of the
`P-type sabetrate for the N-channel devices. During the
`LOCOSprocess, the pad oxide serves as a stress relief
`layer. Alternatively, an oxide deposition or oxide
`growth step could replace the first LOCOSstep,elimi-
`nating the need for the first pad oxide layer andthefirst
`nitride layer. A subsequent high-temperaturedrive step
`is used to achieve the desired N-well junction depth.
`Following removal of the oxide layer, a second layer of
`pad oxide is grown over the entire wafer. A second
`silicon nitride layer is then deposited on top of the pad
`oxide layer.
`
`95
`
`Exhibit 1017, Lowrey, 2:1-6
`
`
`
`96
`
`Lowrey
`
`a L
`
`owrey
`
`22 at the edge of masking layer 21 during the oxide
`growthstep.
`i
`ippi
`ili
`nitride layer 13, the wafer is exposed to an optional
`boron adjustment implant which optimizes the concen-
`$ tration of P-type charge carriers in the substrate regions
`outside the N-well where N-channel devices will be
`created. Silicon dioxide masking layer 21 protects the
`N-well region from this boron adjustment
`implant.
`Next, the phosphorus atoms implanted in the N-well
`10 regions 15 and the boron atoms outside the N-well from
`the optional adjustment implant are driven into the
`substrate during a high-tempcrature step.
`
`Exhibit 1017, Lowrey, 8:2-12
`
`
`
`97
`
`Lowrey
`
`Lowrey
`
`mini-spacer oxide layer 62 on the edges of the N-chan-
`nel transistor gates 56.
`Referring now to FIG. 7, all circuitry is blanketed
`with a first spacer oxide layer 71 by one of various
`techniques (¢.g., chemical vapor deposition).
`Referring now to FIG.8, first spacer oxide layer 71
`and mini-spacer oxide layer 62 are etched with a first
`anisotropic etch, then optionally etched once again with
`a first isotropic etch to formafirst set of sidewall spac-
`ers 81 for N-channel transistor gates 56, N-channel
`interconnects 57 and the portion of polysilicon layer 53
`which blankets the P-channel regions. The anisotropic
`etch is used to remove mostof the spacer oxide layers,
`but not to the point where the substrate is cleared. The
`task of clearing the substrate is left to the wet etch,
`which can be made far more selective to silicon dioxide
`than to the substrate, thus minimizing silicon crystal
`damage on the substrate surface. A high-dosage arsenic
`or phosphorus implant then creates self-aligned heavily
`doped n-type source/drain regions 82 for N-channel
`devices. The high-dosage implantis self-aligned to the
`edges of the N-channeltransistor gates 56.
`
`Exhibit 1017, Lowrey, 9:6-12
`
`
`
`98
`
`Ogawa
`Se
`Ogawa
`duce a semiconductor device having a high quality.
`The second embodiment, whichis an extension of the
`previous embodiment, is a method for production of a
`semiconductor device in accordance with the first em-
`bodiment, wherein the polycrystalline silicon (Si) layer,
`which functions to absorb thermal strains, is further 35
`employed for production of electrodes for gates and/or
`some of the metal wiring. This simplifies the production
`steps thereof. This embodiment will be described, refer-
`ring to FIGS. 5(a), 5(5) and Kc).
`
`30
`
`Exhibit 1010, Ogawa, 7:31-39
`
`
`
`99
`
`Noble
`
`a N
`
`oble
`
`single masking step defines the cdge between the trench and
`gate stack and provides perfect alignment therebetween.
`Thus, the gate is bounded by a raised trench on two opposite
`sides. However, since the gate dielectric and gate conductor
`were formed as blanket layers before the trench was etched,
`there is no corner sharpening, no gate diclectric thinning,
`and no gale wrap around.
`
`Exhibit 1015, Noble, 4:22-26
`
`
`
`100
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 59:9-16
`
`
`
`101
`
`131. Lee’s “L-shaped” spacers (Exhibit 1002, 3:8-21) are formed by
`
`etching away layers 119 and 121 shown in Fig. 13. Layers 115, 117 and 118 are
`
`“typically formed during initial steps of semiconductor fabrication.” Exhibit 1002,
`
`6:53-56. The purpose of the “L-shaped”spacers is to allow for the specific method
`
`used by Lee to dope the source/drain regions.
`
`Exhibit 2012, Schubert Declaration, ¶131
`
`
`
`102
`
`Exhibit 2012, Schubert Declaration, ¶131 (continued from previous slide)
`
`
`
`103
`
`Exhibit 2012, Schubert Declaration, ¶131 (continued from previous slide)
`
`
`
`104
`
`152. Different
`
`from Lee, Noble uses
`
`a diffusion process
`
`to fot
`
`ultrashallow S/D junctionsafter the spacers are formed.
`
`In this regard, Noble states:
`
`Then, after
`
`spacers 152 are formed (FIG.
`
`12),
`
`intrinsic
`
`polysilicon (or intrinsic amorphous silicon)
`
`is deposited or
`
`selective silicon is growth for raised source/drain 154 as shown
`
`in FIG. 13. Dopant for the raised source/drain is implanted at
`
`low energy so as to avoid damage to the single crystal silicon
`
`below. Then the dopantis diffused from the polysilicon to form
`
`[source/drain] ultrashallow junctions 156 without damage.
`
`Exhibit 1015, 6:17-24 (emphasis added). Based on these differences, a POSITA
`Exhibit 2012, Schubert Declaration, ¶152
`
`implementing Noble’s transistor would not be motivated to implement the spacers
`
`
`
`105
`
`158. This configuration is achieved because Noble begins the fabrication
`
`process by first
`
`laying down layers 14 and 116 and then boring (or etching)
`
`through these layers to form a trench that is then filled with oxide material. The
`
`opening formed through layers 14 and 116 is bordered by these twolayers.
`
`Exhibit 2012, Schubert Declaration, ¶158
`
`
`
`106
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 84:14-18
`
`
`
`107
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 84:19-85:18
`
`
`
`108
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 85:19-86:2
`
`
`
`109
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 86:3-13
`
`
`
`110
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 87:14-88:3
`
`
`
`111
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 88:4-15
`
`
`
`112
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 89:2-13
`
`
`
`113
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 89:14-90:8
`
`
`
`114
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 124:12-125:7
`
`
`
`115
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 125:8-20
`
`
`
`116
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 126:11-17
`
`
`
`117
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 126:18-127:5
`
`
`
`118
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 128:2-15
`
`
`
`119
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 128:16-22
`
`
`
`120
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 129:1-7
`
`
`
`121
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 129:8-17
`
`
`
`122
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 131:14-19
`
`
`
`123
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 132:12-133:2
`
`
`
`124
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 133:2-15
`
`
`
`125
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 133:16-134:3
`
`
`
`126
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 136:1-11
`
`
`
`127
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 148:20-149:8
`
`
`
`128
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 200:21-201:5
`
`
`
`129
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 201:6-19
`
`
`
`130
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 201:20-202:9
`
`
`
`131
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 202:15-21
`
`
`
`132
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 203:14-204:3
`
`
`
`133
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 204:4-11
`
`
`
`134
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 204:12-19
`
`
`
`135
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 207:12-208:15
`
`
`
`136
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 208:16-209:7
`
`
`
`137
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 209:8-20
`
`
`
`138
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 209:21-210:10
`
`
`
`139
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 212:14-213:6
`
`
`
`140
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 272:11-21
`
`
`
`141
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 227:2-7
`
`
`
`142
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 275:6-17
`
`
`
`143
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 275:18-276:3
`
`
`
`144
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 276:4-12
`
`
`
`145
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 276:17-277:2
`
`
`
`146
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 277:17-278:4
`
`
`
`147
`
`Unlike /nnogenetics, TSMC devotes dozensof pagesto explaining
`
`
`
`
`
`‘bothhowandwhyaPOSITAwouldhavemodifiedthecombinedreferences._
`
`
`
`
`
`
`
`Paper2,at21,70;Paper 2 (IPR2016-01247), at 21, 62. TSMCalso explained why
`
`a POSITA would have made those modifications(1.e., to facilitate scaling of the
`
`Lee and Lowrey devices), and why a POSITA would have reasonably expected to
`
`succeed. Paper 2, at 5-7, 21-30, 70-76; Paper 2 (IPR2016-01247), at 5-7, 21-30,
`
`62-68; EX1004, 982, 198; EX1024, 993, 173.
`
`Petitioner’s Reply, Paper 21, pp. 27-28
`
`
`
`
`
`148
`
`and sources and drains(58)(id., 8:3—7, Fig. 5(c)). (Ex. 1004, €80.) Ogawa’s
`
`Figure 5(c), a representativeillustration, appears below with color and annotations.
`
`Fig.5(c)
`
`
`
`52—Buried Oxide (SiO,)
`51—Substrate (Si)
`55—Polysilicon Layer
`54—Gate Oxide (SiO,)
`57{sic]—Gate Electrode/interconnect (silicide) 5S8—Source/Drain
`$9—Interior-Layer Insulating Layer
`60—Upper Layer Wiring
`
`B.=‘The Lee-Noble combination renders claims 1-3, 5—7, 9-12, and
`14-18 obvious
`
`Lee teaches every limitation ofthe challenged claims except trenchisolation.
`
`A POSITA would have understood that Nob/e’s STI was a known substitute for
`
`Lee’s LOCOSisolation. (Ex. 1004, 982; see also Ex. 1009, 1:31-2:24; Ex. 1011,
`
`4:8-16; Ex. 1012, 3:3-10; Ex. 1013, 5:56-67; Ex. 1014, 22:49-52; Ex. 1015,Title,
`
`1:7-10, 2:53-57, 4:14-23, Figs. 12, 13.) The combined teachings discussed in this
`
`section refer to the teachings ofLee, with its LOCOSisolation replaced by Noble's
`
`STI.
`
`IPR2016-01246 Petition, Paper 2, p. 21
`
`
`
`149
`
`C.
`
`~The Lee-Ogawa combination renders claims 1-3, 5—7, 9-12, and
`14-18 obvious
`
`As demonstrated abovein Section V.B., Lee teaches every limitation ofthe
`
`challenged claims except trench isolation. A POSITA would have understood that
`
`Ogawa’strenchisolation was a known substitute for Lee’s LOCOSisolation. (Ex.
`
`1004, 9198; see also Ex. 1009, 1:31-2:24; Ex. 1011, 4:8-16; Ex. 1012, 3:3-10; Ex.
`
`1013, 5:56-67; Ex. 1014, 22:49-52; Ex. 1015, Title, 1:7—10, 2:53-57, 4:14-23,
`
`Figs. 12, 13.) The combined teachings discussed in this section refer to the
`
`teachings of Lee, with its LOCOSisolation replaced by Ogawa’s trenchisolation.
`
`1.
`
`A POSITA would have combined the teachings of Lee and
`Ogawa
`
`The same reasons that would have compelled a POSITAto replace Lee’s
`
`LOCOSwith Noble’s STI also would have compelled a POSITAto replace Lee’s
`
`LOCOSwith Ogawa’s trenchisolation. (Ex. 1004, 4199; see also §§IL.B, V.A.3,
`
`V.B.1.)
`
`a.
`
`Admitted prior art teaches replacing LOCOS with
`knowntrench isolation
`
`The °174 patent shows trenchisolation, including trench isolation with a top
`
`surface higher than the surface of the semiconductorsubstrate, as prior art. (See
`
`supra §V.B.1.a.)
`
`IPR2016-01246 Petition, Paper 2, p. 70
`
`
`
`150
`
`Unlike /nnogenetics, TSMC devotes dozens of pages to explaining
`
`
`
`
`
`‘bothhowandwhyaPOSITAwouldhavemodifiedthecombinedreferences.—
`
`
`
`
`
`Paper2, at 21, 70;Paper2(IPR2016-01247),at21,62.TSMCalso explained why
`
`a POSITA would have madethose modifications(i.e., to facilitate scaling of the
`
`Lee and Lowrey devices), and why a POSITA would have reasonably expected to
`
`succeed. Paper 2, at 5-7, 21-30, 70-76; Paper 2 (IPR2016-01247), at 5-7, 21-30,
`
`62-68; EX1004, 482, 198; EX1024, 993, 173.
`
`Petitioner’s Reply, Paper 21, pp. 27-28
`
`
`
`
`
`151
`
`Fig.5(c)
`
`B.=The Lowrey-Nobdle combination renders claims1, 4, 5, 8—12, 14,
`and 16 obvious
`
`Lowrey teaches every limitation ofthe challenged claims except trench
`
`isolation. A POSITA would have understood that Nob/e’s trench isolation was a
`
`known substitute for Lowrey’s LOCOSisolation. (Ex. 1004, €80; see also Ex.
`
`1009, 1:31-2:24; Ex. 1011, 4:8-16; Ex. 1012, 3:3-10; Ex. 1013, 5:56-67; Ex.
`
`1014, 22:49-52; Ex. 1015, Title, 1:7—10, 2:53-5S7, 4:14-23, Figs. 12, 13.) The
`
`combined teachingsdiscussed in this section refer to the teachings of Lowrey, with
`
`its LOCOSisolation replaced by Noble's STI.
`
`i,
`
`A POSITA would have foundit obvious and even desirable
`to have combined the teachings of Lowrey and Noble
`
`Manyreasons would have compelled a POSITA to replace Lowrey’s
`
`IPR2016-01247 Petition, Paper 2, p. 21
`
`LOCOSwith Noble’s STI. (Ex. 1004, €§80-94.) LOCOS was cheaper and
`
`simpler at the time of Lowrey (February 1990), and the bird’s beak was not a major
`
`
`
`152
`
`
`
`
` :
`Be7Sh -
`
`
`
`
`
`
`
`
`
`FIG. Cee
`
`A POSITA would have understood that the Lowrey-Noble combination
`
`teaches “the source/drain regions include low-concentration source/drain regions
`
`and high-concentration source/drain region,and the first silicide layers are formed
`
`on the high-concentration source/drain regions.” (Ex. 1004, (§157-62; see also
`
`supra §V.B.1.)
`
`C.
`
`The Lowrey-Ogawa combination renders claims 1, 4, 5, 8-12, 14,
`and 16 obvious
`
`As explained in Section V.B, Lowrey teaches every limitation ofthe
`
`challenged claims excepttrench isolation. A POSITA would have understood that
`
`Ogawa’strench isolation was a known substitute for Lowrey’s LOCOSisolation..
`
`(Ex. 1004, 9163; see also Ex. 1009, 1:31-2:24; Ex. 1011, 4:8-16; Ex. 1012, 3:3-
`
`10; Ex. 1013, 5:56-67; Ex. 1014, 22:49-52; Ex. 1015, Title, 1:7-10, 2:53-57,
`
`4:14-23, Figs. 12, 13.) The combined teachings discussed in this section refer to
`
`IPR2016-01247 Petition, Paper 2, p. 62
`
`the teachings ofLowrey, with its LOCOSisolation replaced by Ogawa’s trench
`
`isolation.
`
`
`
`PSLEaSECSERSGEESSGSSS5
`
`7]
`
`
`
`
`
`
`
`153
`
`Petitioner’s Reply, Paper 21, pp. 21-22
`
`
`
`
`
`154
`
`107. At this point of Lowrey’s illustrated embodiment, the isolation regions
`
`start to form. Thefirst step is to prepare a channelstop region 41 after removing
`
`the exposed portions of the second nitride layer 32. (Lowrey at 8:21—30, FIG.4.)
`
`That is followed by forming the LOCOSisolation. (Lowrey at 8:31-35, FIG.5.)
`
`To integrate STI, a person of ordinary skill in the art would have immediately
`
`recognized STI formation can be donehere in the alternative.
`
`I note, for example,
`
`that in FIG. 3 of Lowrey a pad oxide andnitride layer are already present. The
`
`well-known STI processesI described in Section VII.A begin the same way. For
`
`example, Noble’s FIG. 9 and Ogawa’s Fig. 4(c) are formed the same way, although
`Exhibit 1057, Declaration of Dr. Banerjee, ¶107
`
`
`
`155
`
`they use a polysilicon polish/etch stop layer insteadofa nitride polish/etch stop
`
`layer. As I explained in Section VII.A, both polysilicon andsilicon nitride were
`
`well-known options available to a person of ordinary skill in the art, and either
`
`could be used (as could any numberofother materials). In other words, a person
`
`of ordinary skill in the art would have immediately recognized that FIG. 3 of
`
`Lowrey is suitable for a trench etch. A person ofordinary skill in the art would
`
`have also recognized that the channel stop implant should be performedafter the
`
`trench is defined.'' This modification to the Lowrey processis illustrated below.
`
`
`
`''T do not agree with Dr. Schubert that non-uniformity at the bottom ofthe trench
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`would enhance leakage currents. Lowrey itself discloses a non-planar LOCOS
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`Exhibit 1057, Declaration of Dr. Banerjee, ¶107
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`isolation with non-uniformity at the bottom ofthe isolation region. Using STI with
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`non-uniformity at the bottom of the trench would be no different and would not
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`
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`156
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`384. Layer 62 is made of “oxide” (e.g. thermal oxidation) and layer 71 is
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`also made of “oxide” (e.g. chemical vapor deposition), where “oxide” refers to
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`silicon dioxide or SiO». That is, both layers, 62 and 71, are made of the same
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`material, “oxide”. Subsequently, the two layers are subjected to an anisotropic etch
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`to form a single sidewall spacer 81:
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`Referring now to FIG. 8, first spacer oxide layer 71 and
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`mini-spacer oxide layer 62 are etched with a first anisotropic
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`etch, then optionally etched once again with a first isotropic
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`etch to form a first set of sidewall spacers 81 for N-channel
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`transistor gates 56, N-channel interconnects 57 and the portion
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`of polysilicon layer 53 which blankets the P-channelregions.”
`Exhibit 2012, Declaration of Dr. Schubert, ¶384
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`Exhibit 1017, 9:6-12.
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`
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`157
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`Petitioner’s Motion to Exclude Evidence, Paper 29, p. 11
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`
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`158
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`Petitioner’s Objections to Evidence, Paper 13, p. 7
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`
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`159
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`Petitioner’s Objections to Evidence, Paper 16, p. 6
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`