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`Highly Manufacturable Process Technology for
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`Reliable 256 Mbit and 1 Gbit DRAMs
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`H.K. Kang, K.H. Kim, Y.G. Shin, IS. Park, K.M. Ko, C.G. Kim, K.Y. Oh, S.E. Kim, C.G. Hong, K.W. Kwon,
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`J.Y. Yoo, Y.G. Kim, C.G. Lee, W.S. Paick, D.I. Suh, C.J. Park, S.I. Lee, S.T. Ahn, C.G. Hwang, and M.Y. Lee
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`Semiconductor R&D Center, Samsung Electronics Co., LTD.
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`San #24, Nongseo-Lee, Kiheung-Eup, Yongin-Gun, Kyungki-Do, 449-900, Korea
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`Abstract
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`TazOs dielectric on poly-Si cylinder capacitors, Chemical-
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`Mechanical Polishing (CMP) planarization, pure W bit-line,
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`and Al reflow were integrated into a highly manufacturable
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`DRAMprocesstechnology. This technology provided larger
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`process margin, higher reliability, and better design
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`flexibility.
`In addition, the critical steps of the new process
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`has been reduced by 25% of those of the conventional
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`process. The manufacturability of the technology has been
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`proven by applying it to 16Mbit density DRAMswith 256
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`Mbit design rule (0.28 jum).
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`Introduction
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`As the DRAM generation goes 256 Mbit and beyond,
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`the DRAM fabrication process has become more and more
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`complicated. This will cause the production cost of the high
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`density DRAMs unacceptably high and will significantly
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`degrade the device reliability. Thus, it is essential to develop
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`a process technology that is simple and yet ensures high
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`performance andhighreliability.
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`We have developed a highly manufacturable process
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`technology for 256 Mbit DRAMs and beyond. Process was
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`simplified by employing a simple cell structure and
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`metallizations with less complexity. Photolithography
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`margin was significantly improved by realizing a better level
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`of planarization. The main features of this process are TagOs
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`dielectric on poly-Si cylinder capacitors, CMP planarization,
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`pure W bit-line, and Al reflow. This technology provided
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`larger process margin, higher reliability, and better design
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`flexibility.
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`Cell Architecture
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`Fig. 1 shows a schematic diagram of the DRAM cell we
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`have implemented. Modified LOCOSisolation, W-polycide
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`(WSio/poly-Si) word-line, and W bit-line were used. Fig. 2
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`showsthe cross-sectional SEM micrograph of the memory
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`cell.
`The KrF eximer laser lithography was used for
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`with 0.28 jm design rule.
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`Unit Processes and Their Applications
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`A, Ta205 Capacitor
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`A CVD Taz2Qs dielectric film of 8.5 nm thickness was
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`treatment and dry-Oz annealing. Thermally robust Ta20s5
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`capacitor was realized by forming the TiN/Poly-Si bilayer
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`plate electrode [1]. Fig. 3 shows the capacitance and leakage
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`characteristic as a function of the applied voltage. The oxide
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`equivalent thickness (Toxeq) of 3.5 nm and the capacitance of
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`30 fF/cell was obtained. Low leakage current level was
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`maintained even after high temperature thermal cyclesof the
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`B. Low Temperature ILD
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`03-TEOS USG/low temperature planarization replaced
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`BPSG/reflow ILD (Inter-Layer Dielectric) to reduce the
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`thermal budget, which improves device isolation and short
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`channel properties of transistors. CMP achieved a perfect
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`planarization of ILD between word-lines and bit-lines.
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`helped patterning bit-lines without using multilayer
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`photoresist, resulting low defect density. Fig. 4 shows W
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`lines patterned on the polished ILD. Carbon from the organic
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`precursor of USG and mobile ions from the CMP chemistry
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`could be potential contaminants. Threshold voltage of
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`transistors, however, was not changed by replacing the
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`BPSG/reflow ILD process with organic USG/CMP. Gate
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`oxide integrity measured by TDDB did not also make much
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`difference between the two groups(Fig. 5).
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`C. W Bit-Line
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`After openingbit-line contacts, about 30 nm thick Ti was
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`deposited and rapid thermal annealed to form TiSiz on the
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`0-7803-2111-1 $4.00 © 1994 IEEE
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`26.4.1
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`Page 1 of 4
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`TEDM94-635
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`TSMC Exhibit 1053
`TSMCv. IP Bridge
`IPR2016-01246
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`Page 1 of 4
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`TSMC Exhibit 1053
`TSMC v. IP Bridge
`IPR2016-01246
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`exposed Si surface. The remained Ti, which was notreacted
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`with Si, was stripped by wet-etch. Then TiN was deposited
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`to a thickness of 30 nm by reactive sputtering. The TiN
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`functions as a barrier metal, that prevents W from reacting
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`with underlayer, and as a glue layer between W andoxide as
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`well. Finally, about 80 nm of W was deposited by CVD and
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`patterned by RIE,
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`The W bit-line widely extended the design flexibility in
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`the core and periphery areas compared to the conventional W-
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`polycide bit-line. This is because the W bit-line has a low
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`sheet resistance and a feasibility of forming contacts to both
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`N+ and P+ diffusion. As shown in Fig, 6(a), a thinner W
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`bit-line has about one-quarter of sheet resistance ofthe thicker
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`W-polycide. By the TiSiz salicidation on the active area and
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`on the poly-Si landing pads before W bit-line deposition,all
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`the bit-line contacts became low resistance metal-to-metal
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`contacts. As a result, bit-line contacts have much lower
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`resistance than that of W-polycide (Fig. 6 (b)-(d)).
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`D. Reflowed Al
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`Fig. 7 showsthe first level interconnection with contact
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`holes filled by Al reflow. Ti/TiN was used as the barrier
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`metal. Overhang-free, conformal deposition profile at the
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`contacts enhanced electromigration and stressmigration
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`resistance [2} compared to the conventional Al deposition.
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`Fig. 8 compares the surface roughness of non-reflowed and
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`reflowed Al after forming gas anneal. High density of
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`hillocks are observed on the non-reflowed surface, while
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`almost none on the reflowed surface.
`It eliminated short-
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`circuit failures between the first and the second metallines.
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`CMOS Transistor Performance
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`LDDstructure was used for both N- and P-channel MOS
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`transistors. Transistors show satisfactory characteristics as
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`summarized in Fig. 9. Thanks to the low thermal budget (65
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`minutes at 850°C equivalent) achieved by employing a low
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`temperature ILD,the threshold voltage P-channeltransistors
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`vary less than 0.1 volt in the range of 0.3-3.0 j:m gate length
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`(Fig. 10).
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`DRAM Performance
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`Fully working 16 Mbit DRAM with 256 Mbit density
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`was obtained by applying this technology. Fig. 11 shows
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`the measured output wave forms of the fabricated 16 Mbit
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`DRAM.Thetypical RAS access timeis 48 ns.
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`Discussion
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`Table 1 compares the new process proposed in this paper
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`with a conventional process.
`is well known that
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`deposition and dry-etch processes are the major sources of
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`process induced particles and thus determine the device yield.
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`As shown in Fig. 12, the numberof deposition and dry-etch
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`steps of the new process is 75% of those of the conventional
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`process.
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`This technology can be scaled to the 1 Gbit DRAM
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`generation with minor modifications, such as replacing
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`LOCOSwith trench isolation and adding hemisphcrical-
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`grained poly-Si on cylinder capacitors.
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`References
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`[1] K.W. Kwonet al., Tech. Dig. of IEDM,1993, p.53.
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`(2] C.S. Park et al., Proc. of VMIC, 1991, p.326.
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`==) GetO1a
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`Fig. 2 Cross-sectional SEM micrograph of the DRAM cell.
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`26.4.2
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`636-1EDM 94
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`Page 2 of 4
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`3
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`1.5
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`05
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`Voltage (V)
`Voltage (V}
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`Fig. 3 (a) Capacitance and (b) leakage characteristics of Ta,Os single cylinder capacitor as a function of applied
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`voltage. Net capacitor area is about 3.2 ym7cell.
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`8
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`t A BPSG/REFLOW
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`@ USG/CMP
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`1E-9 =
`Failure(%) 3 1
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`aw
`9 WS, ‘poly-Si
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`g
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`2 2
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`k
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`10 100
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`Stress time(sec)
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`Fig. 4 Tungstenbit-line patterned on a polished USG=Fig. 5 Comparison of the gate oxide TDDB
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`surface. Bit-lines were RIE etched with a single layer|characteristics of (a) BPSG-flowed and (b) USG
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`photoresist mask.
`polished samples. Gate oxide thickness is 8 nm.
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`Stress current density is about 50 mA/cny’.
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`1000
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`contact sizeu0.9x0.3 pm*®
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`contact sizea0.3x0.3 pm®
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`contact size=0.3x0.3 pm”
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`«60
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`°
`Bit-line'Gate
`Bit-line/Landing Pad
`Bit-line/N+
`Sheet Resistance
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`40
`1000
`10000
`«B00 1000
`200 «400
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`Contact Resistance{ohm/ent)
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`Resistance(ohm/cm2)
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`(c)
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`Fig. 6 Comparisons of W and W-polycide: (a) bit-line sheet resistance, (b) bit-line/tungsten policide gate, (c) bit-
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`line/N+ substrate, and (d) bit-lineflanding pad contact resistace. Thickness of tungsten is 80nm while tungsten
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`silicide/poly Si is 150/SOnm.
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`26.4.3
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`IEDM 94-637
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`500
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`Length ( um }
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`:
`Fig. 8 Comparison of the hillock density on (a) non-reflowed and
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`Fig. 7 Cross-sectional SEM of an Alalloy line—_(4) reflowed Alalloy surfaces. Surface roughness was measured
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`formed by thereflow process.
`by surface profiler after forming gas anneal at 450°C for 30 min.
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`Gate Length(um)
`Vgs(V)
`Vds(V)
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`10 Variation of
`Fig. 9 (a) Ids-Vds and (b) Ids-Vgs characteristics of N-channel (W=10um, Fig.
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`threshold voltage of P-channel
`L=0.4um) and P-channel (W=10um, L=0.4um) MOStransistors. Vgs was varied
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`MOStransistors as a function of
`from 0 to 2.5V for Ids-Vds curve. Vds =0.1V for Ids-Vgs curve.
`gate length.
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`Table 1. Comparison of process steps between a
`conventional process and the new process.
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`aeorerionihaces]Neve
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`esee
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`eseeor)
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`Wasa _ARetow
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`|lds|(mA)
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`re
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`Fig. 11 Measured output wave forms of the 16M
`DRAM.
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`deposition
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`Numberof Steps
`Fig. 12 Number of deposition and dry-etch steps of a conventional process and the new process.
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`26.4.4
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`638-IEDM 94
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`Page 4 of 4
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`Page 4 of 4
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