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`ISOLATION TECHNOLOGY FOR VLSI DEVICES
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`Kei KUROSAWA, Tadashi SHIBATA and Hisakazu IIZUKA
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`Toshiba Research and Development Center,
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`Toshiba Corporation, Kawasaki, Japan
`is described in detail and the electrical
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`characteristics of test devices fabricated
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`by BOX are discussed.
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`ABSTRUCT
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`A new field isolation technology ide-
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`al for VLSI devices has been developed
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`incorporating a unique two step oxide-
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`burying process. This technology is com-
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`pletely free from bird's beak formation
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`which is particularly important for in-
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`creasing the packing density.
`A near-
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`perfect planar surface structure is also
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`obtained.
`MOS devices fabricated by the
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`new technology showed no thershold voltage
`increase due to the narrow channel effect
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`for channel widths down to submicron
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`region.
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`INTRODUCTION
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`BOX TECHNOLOGY
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`The fabrication process of BOX is
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`schematically outlined in Fig. 2.
`The
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`active device areas on silicon wafer (P-
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`type, 50 Ycm) were covered with aluminum
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`patterns,
`followed by the etching of sili-
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`con substrates in the field region. Reac-
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`tive ion etching (RIE) employing CF, gas
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`(21 cc/min) was used for the silicon etch-
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`ing. Borons were implanted using the
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`aluminum patterns as. masks.
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`These grooves were completely filled
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`up with SiO, using the following two step
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`oxide-burying technique.
`In the first
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`oxide burying step, plasma-deposited Si0>
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`was roughly filled into the engraved field
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`region by the lift-off technique,
`leaving
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`V-shaped grooves in the periphery.
`In the
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`lift-off technique, we used the preferen-
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`tial etching characteristics of plasma
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`deposited SiO.
`to buffered HF solution
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`occuring at steep side walls.
`The SEM
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`picture in Fig.
`2 demonstrates the prefer-
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`ential etching of plasma deposited SiO,
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`which occured at edges of the active
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`region.
`As is clearly seen in the pic-
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`ture,
`the SiO.
`is completely removed from
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`the steep side walls.
`Then the SiO, on
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`top of aluminum mask was lifted-off by
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`etching the aluminum mask.
`The boiling
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`in H202 + HzS0O,
`(1:3) solution was employ-
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`ed for the etching of aluminum.
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`The remaining V shaped grooves were
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`For
`buried with SiO,
`in the second step.
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`burying SiO,
`into the V-grooves, surface
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`levelling technique using spin-coated re-
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`sist was utilized after the deposition of
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`CVD SiO...
`The resist and CVD SiO.
`layers
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`were simultaneously etched by RIE with
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`equal etching rates for resist and SiO:.
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`the
`After smoothing the oxide surfaces,
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`remaining oxide on the active device re-
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`gion was removed by solution etching.
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`After oxide-burying processes were
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`completed,
`test devices were fabricated
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`using a conventional n-channel MOS tech-
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`nology.
`For comparision,
`test devices
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`were also fabricated by conventional LOCOS
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`process using the same set of masks.
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`The field isolation of device on sil-
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`icon substrate is one of the most
`impor-
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`tant process steps in the fabrication of
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`integrated circuits.
`The widely-known
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`LOCOS process(1) which uses silicon ni-
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`tride as masks for selective oxidation has
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`revealed several disadvantages as a proc~-
`ess for future VLSI fabrication.
`The lat-
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`eral oxidation under the nitride masks, for
`instance, creates so-called brid's beak, (2)
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`resulting in a considerable reduction of
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`packing density. Process-induced crystal-
`line defects (3) and gate oxide failures
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`due to "white ribbon", (4) both of which
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`are associated with the LOCOS process,
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`represent a difficult barrier for the de-
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`velopment of VLSI devices.
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`The purpose of this paper is to pre-
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`sent
`the newly developed field isolation
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`technology which overcomes these diffi-
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`culties.
`Since isolation is achieved by
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`burying oxide into etched grooves formed
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`in silicon substrates,
`the technology is
`called "BOX", (5)
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`the grooves in
`In the BOX process,
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`the field region is completely filled up
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`with SiO, using a two step oxide buring
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`process.
`Since silicon substrates are not
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`oxidized to form field oxide,
`the bird's
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`beak length is exactly zero. This is par-
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`ticularly important for the density im-
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`provements of VLSI.
`The BOX structure is
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`further characterized by its near-perfect
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`planar surface which is also essential for
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`fine patterning and high-reliability met-
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`allization.
`In this paper,
`the BOX process
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`16.4
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`CH1708-7/81/0000-0384 $00.75 © 1981 IEEE
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`384 — IEDM81
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`Page 1 of 4
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`TSMC Exhibit 1052
`TSMCv. IP Bridge
`IPR2016-01246
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`Page 1 of 4
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`TSMC Exhibit 1052
`TSMC v. IP Bridge
`IPR2016-01246
`
`
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`RESULTS AND DISCUSSION
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`SUMMARY
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`The new field isolation technology,
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`BOX has been described. This process is
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`completely free from bird's beak formation,
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`which is essential for high device density.
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`According to the simple estimation of dy-
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`namic memory cell density,‘7) BOX achieves
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`an 80% density improvement as compared to
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`the LOCOS under 1.0 um layout rules. Near-
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`planar topography is also obtained. This
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`is very important for fine patterning and
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`high reliability of metallization.
`Fur-
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`thermore,
`transistors fabricated by BOX
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`show no threshold voltage increase for
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`channel widths even below 1 um.
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`ACKNOWLEDGMENT
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`The authors would like to thank
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`T. Moriya, R. Hazuki and K. Taniguchi for
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`their helpful suggestions.
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`REFERENCE
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`(1) J. A. Appels and M. M. Paffen, Philips.
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`Res. Rep., 26 157 (1971)
`:
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`(2) E. Bassous, H. N. Yu and V. Maniscalco,
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`J. Electrochem. Soc., 123, 1729 (1976).
`
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`(3) K. Shibata and K. Taniguchi, J. Elec-
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`trochem. Soc., 127 1383 (1980).
`
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`(4) E. Kooi, J. G. Van Lierop and
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`J. A. Appels, J. Electrochem. Soc.,
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`123, 1117 (1976).
`
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`Iizuka,
`(5) K. Kurosawa, T. Shibata and H.
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`39th Device Research Conference, Santa
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`
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`Barbara, June (1981).
`
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`
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`(6) K. Kurosawa, Y. Horiike, H. Okano and
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`
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`K. Okumura, Proceedings of the 2nd
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`
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`Simposium on Dry Processes cosponsored
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`
`
`by The IEE of Japan, P43 (1980).
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`(7) T. Shibata, H. Lizuka and S. Kohyama,
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`Int. Electron Devices Meeting, Dig.
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`Tech. Paper, PP177-180 (1978).
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`Figure 3 shows the current-voltage
`characteristics of test transistors fabri-
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`cated by LOCOS and BOX. Cross sectional
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`views of the transistors along the channel
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`width direction are also shown by SEM pic-
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`tures.
`As is clearly seen in the figure,
`a submicron transistor with a channel
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`width exactly equal
`to the mask dimension
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`(0.9 um)
`is realized by BOX technology.
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`While the transistors fabricated by LOCOS
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`have collapsed due to the bird's beak when
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`the channel width are smaller than 1 um on
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`the mask.
`In the optimized LOCOS the
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`bird's beak length is minimized to about
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`0.5 um.
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`Figure 4 shows the threshold voltage
`as a function of the channel width defined
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`by mask.
`The threshold voltage of LOCOS
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`samples increases significantly when the
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`channel width is reduced below 2 um. This
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`threshold increase is a result of the nar-
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`row channel effect which is further en-
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`hanced by the bird's beak and the lateral
`diffusion of field borons.
`On the other-
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`in the case of BOX sample, the
`hand,
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`threshold voltage is almost constant for
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`channel widths down to submicorn region.
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`Figure 5 shows reverse current-volt-
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`age characteristics of p-n junction diode.
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`It is clearly seen in the figure that the
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`reverse current level of the BOX sample is
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`as low as that of the LOCOS sample.
`In
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`LOCOS sample,
`the degradation in reverse
`characteristics is often observed caused
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`by the crystalline defects induced in the
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`periphery of field oxide.
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`Figure 6 shows the field boron dose
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`dependence of the field inversion voltage.
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`It indicates that about one order of mag-
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`nitude larger dose is required for LOCOS
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`since the implanted borons are lost into
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`field oxide during field oxidation.
`One of the difficulties associated
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`with the BOX structure is a parasitic
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`channel formation occuring at the side
`walls of silicon. This results in a chan-
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`leakage current of the order of ~10-*A.
`nel
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`One example of the degraded subthreshold
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`characteristics is demonstrated in Fig. 7.
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`The leakage current appears as a hump su-
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`perimposed on the subthreshold character-
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`istics of the transistor. As is clearly
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`seen in the figure,
`this effect has been
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`successfully eliminated by the side wall
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`boron implantation.
`The boron implanta-
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`tion to the side walls near perpendicular
`to the wafer surface has been carried out
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`in the following way. Borons of ~10'* cm-?
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`implanted to the field region prior to the
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`formation of grooves in silicon substrates.
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`The lateral penetration of implanted bo-
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`rons due to the ion straggle introduced
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`enough amount of impurities in the sub-
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`strate under the aluminum mask which pre-
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`vented the paracitic channel formation at
`the side walls.
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`16.4
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`IEDM 81 — 385
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`Page 2 of 4
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`Page 2 of 4
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`Aluminum
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`Si02
`Implanted
`Region
`Si Wafer
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`Fig. 2.
`Aluminum @
`Field Sig
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`LOCOS
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`Ist Oxide Burying Step
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`Plasma- deposited
`Si0o
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`Plasma Si02 —
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`(After Buffered HF Etching)
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`V Grooves
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`2nd Oxide Burying Step
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`Resist
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`CVD SiOz
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`The SEM picture which explains
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`the lst oxide-burying step.
`The
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`plasma-deposited SiO, on steep
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`side walls is preferentially
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`etched by buffered HF solution.
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`Fig. 1. Fabrication process steps of BOX.
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`BOX
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`Fig. 3. Current-voltage characteristics of transistors fabricated by LOCOS and BOX.
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`In the case of LOCOS,
`the active device area has disappeared due to the bird's
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`beak, while BOX realizes a transistor with identical dimensions to the mask.
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`386 — IEDM81
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`Page 3 of 4
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`16.4
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`Page 3 of 4
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`7
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`e/
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`A]
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`sie -WALL
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`IMPLANTED
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`Diode size ; 200x500 ( pm?)
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`Reverse Bias Voltage
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`(Volt)
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`(Amp.)
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`ReverseCurrent
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`DRAINCURRENT
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`SOURCE
`SIDE WALL
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`OS
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`1.0
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`GATE VOLTAGE (V)
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`1.5
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`Reverse current-voltage charac-
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`teristics of p-n junction diode.
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`Page 4 of 4
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`Fig. 7.
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`Subthreshold characteristics of a
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`transistor with W/L=20 um/3 um.
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`(Vsub=0V, Vp=5 V.) Parasitic
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`channel formation occuring at the
`side-walls of silicon results in
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`a increased leakage current of
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`the order of 10°°A.
`The side-wall
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`boron implantation successfully
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`eliminated the leakage current.
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`16.4
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`IEDM 81 — 387
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` LOCOS
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`100
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`
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`>ao £‘
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`Ss 10>
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`2°aawo
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`oQ=E
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`“Beas ~us
`pinasics
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`BOX
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`CHANNEL LENGTH =4 4m
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`BV
`Vo =
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`Vsue? OV
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`1
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`2
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`3
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`4
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`20
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`|
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`10%
`10%
`Field Boron Dose
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`(cm)
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`14
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`05
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`0
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`O
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`= 1.0
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`oa23> Z
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`z 2
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`2=E
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`Field inversion voltage as a
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`function of field boron dose.
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`length of the field tran-
`Channel
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`sistors is 20 um.
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`NON SIDE-
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`Channel Width Defined by Mask
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`(pm)
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`Fig. 6.
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`) (
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`A
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`Fig. 4.
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`Threshold voltage as a function of
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`channel width defined by the mask.
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`Negligible narrow channel effects
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`are seen in BOX samples.
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`Page 4 of 4
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