`SILICON PROCESSING
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`FOR
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`THE VLSI ERA
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`VOLUME2:
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`PROCESS INTEGRATION
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`STANLEY WOLF Ph.D.
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`Professor, Departmentof Electrical Engineering
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`California State University, Long Beach
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`Long Beach,California
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`LATTICE PRESS
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`_ Sunset Beach, California
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`Page1 of 33
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`TSMCExhibit 1046
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`IPR2016-01246
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`TSMC Exhibit 1046
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`DISCLAIMER
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`This publication is based on sourcesand information believed to be reliable, but the
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`authors and Lattice Press disclaim any warrantyorliability based on orrelating to the
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`contents of this publication.
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`Published by:
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`Lattice Press,
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`Post Office Box 340
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`Sunset Beach, California 90742, U.S.A.
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`Cover design by Roy Montibon, Visionary Art Resources, Inc., Santa Ana, CA.
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`Copyright © 1990 by Lattice Press.
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`All rights reserved. No part of this book may be reproducedor transmitted in any form
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`or by any means,electronic or mechanical, including photocopying, recording or by any
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`information storage andretrieval system without written permission from the publisher,
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`except for the inclusion of brief quotations in a review.
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`Library of Congress Cataloging in Publication Data
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`Wolf, Stanley
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`Silicon Processing for the VLSI Era
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`Volume 1: Process Integration
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`Includes Index
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`1. Integrated circuits-Very large scale
`
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`integration. 2. Silicon.
`I. Title
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`86-08 1923
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`ISBN 0-961672-4-5
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`987 6
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`PRINTED IN THE UNITED STATES OF AMERICA
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`Page2 of 33
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`Page 2 of 33
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`

`

`CONTENTS
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`PREFACE
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`1
`- PROCESS INTEGRATION FOR
`CHAP.
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`VLSI AND ULSI
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`1
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`1.1 PROCESS INTEGRATION
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`5
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`1.1.1 Process Sequence Usedto Fabricate an
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`5
`Integrated-Circuit MOS Capacitor,
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`1.1.2 Specifying a Process Sequence, 6
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`1.1.3 Levels of Process Integration Tasks, 7
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`1.2
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` PROCESS-DEVELOPMENT AND
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`PROCESS-INTEGRATION ISSUES
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`8
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`REFERENCES
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`11
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`CHAP. 2 - ISOLATION TECHNOLOGIES FOR
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`INTEGRATED CIRCUITS
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`12
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`2.1 BASIC ISOLATION PROCESSES FOR BIPOLAR ICs
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`13
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`13
`2.1.1 Junction Isolation,
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`2.1.1.1 Junction Isolation in the SBC Process
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`2.1.1.2 Collector-Diffusion Isolation
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`2.2 BASIC ISOLATION PROCESS FOR MOS ICs
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`(LOCOS ISOLATION)
`17
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`2.2.1 Punchthrough Prevention between Adjacent Devices in MOS
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`Circuits, 20
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`2.2.2 Details of the Semirecessed Oxide LOCOS Process, 20
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`2.2.2.1 Pad-Oxide Layer.
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`2.2.2.2 CVD of Silicon Nitride Layer.
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`2.2.2.3 Mask and Etch Pad-Oxide/Nitride Layer to Define Active
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`Regions.
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`Page 3 of 33
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`Page 3 of 33
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`Viii
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`CONTENTS
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`2.2.2.4 Channel-Stop Implant.
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`2.2.2.5 Problems Arising from the Channel-Stop Implants.
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`2.2.2.6 Grow Field Oxide.
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`2.2.2.7 Strip the Masking Nitride/Pad-Oxide Layer.
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`2.2.2.8 Regrow Sacrificial Pad Oxide and Strip (Kooi Effect).
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`2.2.3 Limitations of Conventional Semi-Recessed Oxide LOCOSfor
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`Small-Geometry ICs, 27
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`2.3 FULLY RECESSED OXIDE LOCOS PROCESSES
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`28
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`2.3.1 Modeling the LOCOS Process, 31
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`2.4 ADVANCED SEMIRECESSED OXIDE LOCOS ISOLATION
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`31
`PROCESSES
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`31
`2.4.1 Etched-Back LOCOS,
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`2.4.2 Polybuffered LOCOS, 32
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`2.4.3 SILO (Sealed-Interface Local Oxidation), 33
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`2.4.4 Laterally Sealed LOCOSIsolation, 35
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`2.4.5 Bird's Beak Suppression in LOCOS by Mask-Stack Engineering, 38
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`2.4.6 Planarized SILO with High-Energy Channel-Stop Implant, 38
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`2.5 ADVANCED FULLY RECESSED OXIDE LOCOS
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`PROCESSES
`39
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`ISOLATION
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`(Sidewall-MaskedIsolation Technique), 39
`2.5.1 SWAMI
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`2.5.2 SPOT (Self-Aligned Planar-Oxidation Technology),
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`2.5.3 FUROX (Fully Recessed Oxide), 41
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`2.5.4 OSELOII, 43
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`41
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`2.6 NON-LOCOS ISOLATION TECHNOLOGIESI:
`(TRENCH ETCH AND REFILL)
`45
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`2.6.1 Shallow Trench and Refill Isolation, 45
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`2.6.1.1 BOX Isolation.
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`2.6.1.2 Modifications to Improve BOX Isolation.
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`2.6.2 Moderate-Depth Trench and Refill Isolation, 48
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`2.6.2.1 U-GrooveIsolation.
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`2.6.2.2 Toshiba Moderate-Depth Trench Isolation for CMOS.
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`2.6.3 Deep, Narrow Trench and Refill, 51
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`2.6.3.1 Reactive Ion Etching of the Substrate.
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`2.6.3.2 Refilling the Trench.
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`2.6.3.3 Planarization after Refill.
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`—
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`Page4 of 33
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`Page 4 of 33
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`

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`CONTENTS
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`—
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`ix
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`2.7
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`NON-LOCOS ISOLATION TECHNOLOGIES, II: SELECTIVE
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`EPITAXIAL GROWTH (SEG)
`58
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`2.7.1 Refill by SEG of Windows Cut into Surface Oxide, 59
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`2.7.2 Simultaneous Single-Crystal/Poly Deposition (SSPD), 60
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`2.7.3 Etching of Silicon Trenches and Refilling with SEG to Form Active
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`Device Regions, 61
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`61
`2.7.4 Selective-Epitaxial-Layer Field Oxidation (SELFOX),
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`2.7.5 SEG Refill of Trenches (as an Alternative to Poly Refill), 62
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`2.7.6 Epitaxial Lateral Overgrowth (ELO), 62
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`2.8
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`MISCELLANEOUS NON-LOCOS
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`ISOLATION TECHNOLOGIES
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`63
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`2.8.1 Field-Shield Isolation, 63
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`2.8.2 Buried Insulator between Source/Drain Polysilicon (BIPS),
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`64
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`2.9
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`SUMMARY: CANDIDATE ISOLATION TECHNOLOGIES FOR
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`SUBMICRON DEVICES
`65
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`2.9.1 Basic Requirements of VLSI and ULSI Isolation Technologies, 65
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`2.9.2 The Need for Planarity, 65
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`2.9.3 Howthe Various Isolation Technologies Meet the Requirements, 66
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`2.10 SILICON-ON-INSULATOR (SOI)
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`TECHNOLOGIES
`66
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`ISOLATION
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`2.10.1 Dielectric Isolation, 67
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`2.10.2 Wafer Bonding, 70
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`2.10.3 Silicon-on-Sapphire (SOS), 72
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`2.10.4 Separation by Implanted Oxygen (SIMOX), 72
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`2.10.5 Zone-Melting Recrystallization (ZMR), 75
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`2.10.6 Full Isolation by Porous Oxidized Silicon (FIPOS), 76
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`2.10.7 Novel SOI CMOS Processeswith Selective Oxidation and Selective
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`Epitaxial Growth, 77
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`REFERENCES
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`79
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`Page 5 of 33
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`Page 5 of 33
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`

`

`X
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`CONTENTS
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`CHAP. 3 - CONTACT TECHNOLOGY AND
`
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`LOCAL INTERCONNECTS FOR VLSI
`
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`84
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`3.1 THE ROLE OF CONTACT STRUCTURES IN DEVICE AND
`
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`CIRCUIT BEHAVIOR
`84
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`3.1.1 Contact Structures in Planar MOSFETsandBipolar Transistors, 85
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`3.2 THEORY OF METAL-SEMICONDUCTOR CONTACTS’~
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`87
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`3.3.
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`EXTRACTING VALUES OF SPECIFIC CONTACT RESISTIVITY
`
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`
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`FROM MEASUREMENTS
`91
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`3.3.1 Extraction of the Specific Contact Resistivity from an Ideal Contact
`
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`Structure, 92
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`3.3.2 Current Flow in Actual Contact Structures, 93
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`3.3.3 Contact Structures Used to Extract pc, 94
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`3.3.4 Procedure for Accurately Extracting pc from
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`CBKRTest Structures, 97
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`3.3.5 Reported Values of pc for Various Contact Structures, 100
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`3.3.6 Use of a Simple Contact-Chain Structure to Monitor Contact
`
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`Resistance, 101
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`3.4 THE EVOLUTION OF CONVENTIONAL METAL-TO-SILICON
`
`
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`CONTACTS
`101
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`3.4.1. The Basic Process Sequence of Conventional Ohmic-Contact
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`Structuresto Silicon, 102
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`3.4.2 Additional Details Concerning the Processing Steps, 103
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`3.4.2.1 Formation of the Heavily Doped Regionsin the Silicon.
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`3.4.2.2 Formation of Contact Openings (Etching).
`
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`3.4.2.3 Sidewall Contouring of the Contact Holes by Reflow.
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`3.4.2.4 Sidewall Contouring by Etching.
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`3.4.2.5 Deposition.
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`3.4.2.6 Metal Deposition and Patterning.
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`3.4.2.7 Sintering the Contacts.
`
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`3.4.3 Aluminum-Silicon Contact Characteristics, 111
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`3.4.3.1 The Kinetics of the Al-Si Interface During Sintering.
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`3.4.4 Use of Aluminum-Silicon Alloys to Reduce Junction Spiking, 116
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`3.4.5 Platinum Silicide-to-Silicon Contacts, 117
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`3.4.5.1 Process Sequence Used to Form PtSi-Si Contacts.
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`3.4.5.2 Limitations of the PtSi-Si Contact Structure.
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`Page 6 of 33
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`Page 6 of 33
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`CONTENTS
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`xi
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`3.5 DIFFUSION BARRIERS
`
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`121
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`3.5.1 Theory of Diffusion Barrier Layers, 121
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`3.5.2 Materials Used as Diffusion Barriers, 124
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`3.5.2.1 Sputter-Deposited Titanium-Tungsten (Stuffed Barrier).
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`3.5.2.2 Polysilicon (Sacrificial Barrier).
`
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`3.5.2.3 Titanium (Sacrificial Barrier).
`
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`3.5.2.4 Titanium Nitride (Passive Barrier).
`
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`3.5.2.5 CVD Tungsten.
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`3.5.2.6 Experimental Diffusion Barrier Materials.
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`3.6 MULTILAYERED OHMIC-CONTACT STRUCTURES TO
`
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`SILICON
`131
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`3.6.1 Al-Ti:W-PtSi-Si Contacts, 132
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`3.6.2 AI-TiN-Ti-Si Contacts, 132
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`3.6.3 Mo-Ti:W-Si and Mo-Ti-Si Contacts,
`
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`134
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`3.7
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`SCHOTTKY-BARRIER CONTACTS
`
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`134
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`3.8 THE IMPACT OF THE INTRINSIC SERIES RESISTANCE ON
`
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`MOS TRANSISTOR PERFORMANCE~~137
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`3.8.1 The Impact of Rg on MOSFET Performance, 137
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`3.8.2 Estimates of Rsh, Rsp, Rac, and Reo; 138
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`3.8.3 Impact of Rs on Device Characteristics, 142
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`3.8.4 Summary of the Impact of Intrinsic Series- Resistance Effects on
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`MOSFETPerformance, 142
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`3.9 ALTERNATIVE (SELF-ALIGNED) CONTACT STRUCTURES
`
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`FOR ULSI MOS DEVICES
`143
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`3.9.1 Self-Aligned Silicide Contacts, 144
`
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`3.9.1.1 Self-Aligned Titanium Silicide Contacts.
`
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`3.9.1.2 Self-Aligned Cobalt Silicide Contacts.
`
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`3.9.1.3 Measuring r¢ of Self-Aligned Silicide Contacts.
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`3.9.2 Buried-Oxide MOS Contact Structure (BOMOS), 153
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`3.10 FORMATION OF SHALLOW JUNCTIONS AND THEIR IMPACT
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`ON CONTACT FABRICATION
`154
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`10.1 Conventional Shallow-Junction Formation, 154
`
`3.
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`3.10.2 Alternative Approaches to Forming Shallow Junctions, 155
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`3.10.3 Impact of Shallow Junctions on Contact Formation, 160
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`xii
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`CONTENTS
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`3.11 BURIED CONTACTS AND LOCAL INTERCONNECTS_160
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`3.11.1 Butted Contacts and Buried Contacts, 160
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`3.11.2 Local Interconnects, 162
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`3.11.2.1 Selectively Formed TiSiz2.
`
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`3.11.2.2 Ti:W over CoSiz2.
`
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`3.11.2.3. TiN Formed over TiSi2.
`
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`3.11.2.4 Dual-Doped Polysilicon LI with Diffused Source/Drain
`
`
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`
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`Junctions.
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`3.11.2.5 CVD W-Clad Polysilicon LI.
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`REFERENCES
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`CHAP. 4 - MULTILEVEL INTERCONNECT
`
`
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`
`
`TECHNOLOGY FOR VLSI AND ULSI
`
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`176
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`4.1 EARLY DEVELOPMENT OF INTERCONNECT
`
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`
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`TECHNOLOGY FOR INTEGRATED CIRCUITS
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`176
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`4.1.1 Interconnects for Early Bipolar ICs, 176
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`4.1.2 Interconnects in Silicon-Gate NMOSICs, 178
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`4.1.3 Evolution of Interconnects for Bipolar ICs, 179
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`4.1.4 Evolution of Interconnects for CMOS ICs, 180
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`4.2 THE NEED FOR MULTILEVEL INTERCONNECT
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`TECHNOLOGIES
`180
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`181
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`4.2.1 Interconnect Limitations of VLSI,
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`4.2.1.1 Functional Density.
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`4.2.1.2 Propagation Delay.
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`4.2.1.3 Ease ofDesign and Gate Utilizationfor ASICs and Wafer Scale
`
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`Integration.
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`4.2.1.4 Cost.
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`4.2.2 Problems Associated with Multimetal Interconnect Processes, 187
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`4.2.3 Terminology of Multilevel Interconnect Structures,
`188
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`4.3 MATERIALS FOR MULTILEVEL INTERCONNECT
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`TECHNOLOGIES
`189
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`4.3.1 Conductor Materials for Multilevel Interconnects, 189
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`4.3.1.1 Requirements of Conductor Materials Usedfor VLSI Interconnects.
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`4.3.1.2 Local Interconnect Conductor Materials (Polysilicon, Metal-Silicides,
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`and Polycides).
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`xiii
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`4.3.1.3 Aluminum Metallization.
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`4.3.1.4 Tungsten and Other Conductor Materialsfor VLSI Interconnects.
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`4.3.2 Dielectric Materials for Multilevel Interconnects, 194
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`4.3.2.1 Requirements ofDielectric Layers in Multilevel Interconnects.
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`4.3.2.2 Poly-Metal Interlevel Dielectric (PMD) Materials.
`
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`4.3.2.3 CVD SiO2 Films as Intermetal Dielectrics.
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`4.3.2.4 Low-Temperature-TEOS SiO2 Films as Intermetal
`
`
`Dielectrics.
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`4.3.2.5 Other Materials and Deposition Processes Used to Form Intermetal
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`Dielectrics.
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`4.4
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`PLANARIZATION OF INTERLEVEL DIELECTRIC LAYERS 199
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`4.4.1. Terminology of Planarization in Multilevel Interconnects, 199
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`4.4.1.1 Degree ofPlanarization.
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`4.4.1.2 The Needfor Dielectric Planarization.
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`4.4.1.3 The Price that Must be Paid as the Degree ofDielectric Planarization
`
`
`
`is Increased.
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`4.4.1.4 Design Rules Related to Intermetal Dielectric-Formation and
`
`
`
`Planarization Processes.
`
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`4.4.2 Step Height Reduction of Underlying Topography as a Technique to
`
`
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`Alleviate the Need for Planarization,
`208
`
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`4.4.2.1 Provide Substrate Topography that is Completely Planar.
`
`
`4.4.2.2 Provide a Planar Surface over Local Interconnect Levels.
`
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`-
`4.4.2.3. Minimize the Thickness of the Metal 1 Layer.
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`4.4.2.4 Achieve Smoothing of Steps in DM1 by Sloping the Sidewalls of
`
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`Metal-1 Lines.
`,
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`4.4.3 Deposition of Thick CVD SiOo Layers and Etching Back Without a
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`Sacrificial Layer, 211
`
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`4.4.4 Oxide Spacers, 212
`
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`4.45 Polyimides as Intermetal Dielectrics, 214
`
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`4.4.6 Planarizing by Use of Bias-Sputtered SiOo, 217
`
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`4.4.7 CVD SiO2 and Bias-Sputter Etchback, 220
`
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`
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`
`
`222
`4.4.8 Planarization by Sacrificial Layer Etchback,
`4.4.8.1 Degree ofPlanarization Achieved by Sacrificial Etchback.
`
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`4.4.8.2 Advantages of the Sacrificial Etchback Process.
`
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`4.4.8.3 Sacrificial Etchback Process Problems.
`
`
`4.4.8.4 Alternative Sacrificial Etchback Processes.
`
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`
`4.4.9 Spin-On Glass (SOG), 449
`4.4.9.1 SOG Process Integration.
`
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`
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`4.4.92 The Etchback SOG Process.
`
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`
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`4.4.9.3 The Non-Etchback SOG Process.
`
`
`
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`4.4.10 Electron-Cyclotron-Resonance Plasma CVD, 237
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`4.4.11 Chemical-Mechanical Polishing, 238
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`CONTENTS
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`4.5.
`
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`METAL DEPOSITION AND VIA FILLING
`
`
`
`240
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`4.5.1. Conventional Approach to Via Fabrication and Formation of Metal-
`
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`
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`to-Metal Contacts through the Vias, 240
`
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`
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`4.5.1.1 Design Rules of Multilevel Metal Systems which are Impacted by
`
`
`
`
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`
`
`Conventional Via Processing Limitations.
`4.5.2 Advanced Via Processing (Vertical Vias and Complete Filling of Vias
`
`
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`
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`
`
`
`
`
`
`by Metal), 244
`
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`
`
`4.5.2.1 Increases in Packing Density Resulting from Advanced Via
`
`
`
`
`
`
`
`Process Technology.
`
`
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`
`4.5.3 Processing Techniques which Allow
`
`
`
`
`
`
`245
`Vertical Vias to be Implemented,
`4.5.3.1 Required Degree of Via Filling by Plugs.
`
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`4.5.4 CVD W TechniquesforFilling Vertical Vias and Contact Holes, 245
`
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`
`
`4.5.4.1 General Information on the CVD Tungsten Process.
`
`
`
`
`
`4.5.4.2 Blanket CVD W and Etchback. -
`
`
`
`
`4.5.4.3 Selective CVD W.
`
`
`
`
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`
`
`4.5.5 Other CVD Via Filling Processes, 253
`4.5.5.1 Blanket CVD Polysilicon and Etchbackfor Contact Hole Filling.
`
`
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`
`
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`
`
`4.5.5.2 Selective Deposition of Poly.
`
`
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`
`
`
`4.5.5.3 Selectively FormedSilicide Contact Plugs.
`
`
`
`4.5.5.4 CVD Aluminum.
`
`
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`
`
`
`4.5.6 Alternatives to CVD for Filling of Vias, 254
`
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`
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`4.5.6.1 Bias Sputtering of Al to Achieve Complete Filling of Via Holes.
`
`
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`
`
`4.5.6.2 Laser Planarization ofAl Films.
`
`
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`
`
`
`
`4.5.6.3 Contact Hole and Via Filling by Selective Electroless Metal
`
`Deposition.
`
`
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`
`
`
`4.5.7 Pillar Formation as an Alternative
`
`
`
`
`
`
`to Filling Contact Holes and Vias, 258
`
`
`
`4.6
`
`4.7
`
`
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`
`
`
`
`
`FILLED GROOVES IN A DIELECTRIC LAYER
`
`
`
`259
`
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`MANUFACTURING YIELD AND
`
`
`
`
`RELIABILITY ISSUES OF VLSI INTERCONNECTS
`
`
`
`260
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`4.7.1 Factors Which Impact Manufacturing Yield, 261
`
`
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`4.7.2 Multilevel Interconnect-Related Yield Issues, 261
`
`
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`
`
`
`
`
`4.7.3 General Reliability Issues Associated with IC Interconnects, 264
`
`
`4.7.3.1 Electromigration.
`
`
`
`
`
`4.7.3.2 Electromigration at the Contacts.
`
`
`4.7.3.3 Stress-Induced Metal Cracks and Voids.
`
`
`
`
`
`
`4.7.3.4 Corrosion.
`
`
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`4.7.4 Reliability Issues Associated with Multilevel Interconnects, 268
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`CONTENTS
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`XV
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`4.7.4.1 Hillock Formation and Prevention Measures.
`
`
`
`
`
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`
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`
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`4.7.4.2 Dielectric Void Reliability Problems.
`
`
`
`4.8 PASSIVATION LAYERS
`
`
`
`273
`
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`
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`
`
`4.9 SURVEY OF MULTILEVEL METAL SYSTEMS
`
`
`
`
`276
`
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`
`
`4.9.1 Bipolar Double-Level Metal Systems, 276
`
`
`
`
`
`4.9.2 CMOS Double-Level-Metal Systems, 277
`
`
`
`
`
`
`4.9.2.1 Non-Planarized DLM (2.0 um CMOS).
`
`
`
`
`
`
`
`4.9.2.2. Non-Planarized DLM: CVD-W Metal (2.0-um NMOS).
`
`
`
`
`
`
`
`
`
`
`4.9.2.3 Resist Etchback, Bias-Sputtered SiO02, and SOG DLMfor 1.5 pum
`
`
`CMOS.
`
`
`
`
`
`
`
`
`4.9.2.4 Non-Sacrificial Layer Etchback DLM (1.0-um CMOS).
`
`
`
`
`
`
`
`
`4.9.2.5 Alternative CMOS DLM Process with Ti:W/Mo as Metal 1.
`
`
`
`
`
`
`4.9.2.6 DLM Processes for Submicron CMOS.
`
`
`
`
`
`4.9.3 Three-Level Metal Systems, 283
`
`
`
`
`
`4.9.4 Four-Level Metal Systems, 285
`
`
`
`
`
`
`
`4.10 SUMMARY OF MULTILEVEL INTERCONNECT
`
`
`
`
`TECHNOLOGY REQUIREMENTS FOR VLSI
`
`
`
`
`286
`
`REFERENCES
`
`
`
`287
`
`
`
`
`
`
`
`
`CHAP. 5 - MOS DEVICES AND
`
`
`NMOS PROCESS INTEGRATION
`
`
`
`298
`
`
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`
`
`
`5.1 MOS DEVICE PHYSICS
`
`
`
`298
`
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`
`
`5.1.1 The Structure and Device Fundamentals of MOS Transistors, 298
`
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`5.1.2 The Threshold Voltage of the MOS Transistor, 301
`
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`
`
`5.1.3 Impact of Source-Body Bias on V7 (Body Effect), 304
`
`
`
`
`5.1.4 Current-Voltage Characteristics of
`
`
`
`MOSTransistors, 305
`5.1.5 The Capacitances of MOSTransistors, 307
`
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`
`5.2 MAXIMIZING DEVICE PERFORMANCE THROUGH DEVICE
`
`
`
`
`
`DESIGN AND PROCESSING TECHNOLOGY
`307
`
`
`
`
`
`5.2.1 Output Current (Ip) and Transconductance (gm), 308
`
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`
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`
`
`5.2.2 Controlling the Threshold Voltage through Process
`
`
`
`
`and Circuit-Design Techniques, 309
`
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`
`
`5.2.3 Subthreshold Currents (Ipst when Vg < IVqTI), 311
`Page 11 of 33
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`Xvi
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`CONTENTS
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`5.2.4 Switching Speed, 313
`
`
`
`
`5.2.5 Junction Breakdown Voltage (Drain-to-Substrate), 313
`
`
`
`
`
`
`5.2.6 Gate-Oxide Breakdown Voltage, 314
`
`
`
`5.2.7 High Field-Region Threshold-Voltage Value, 315
`
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`
`
`
`5.3 THE EVOLUTION OF MOS TECHNOLOGY
`
`
`
`
`
`(PMOS AND NMOS)_315
`
`
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`
`
`5.3.1 Aluminum-Gate PMOS, 316
`
`
`
`
`
`5.3.2 Silicon-Gate MOS Technology, 318
`
`
`
`
`
`5.3.3 Reduction of Oxide-Charge Densities, 319
`
`
`
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`
`
`
`
`5.3.4 lon Implantation for Adjusting Threshold Voltage, 321
`
`
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`
`
`
`5.3.5 Isolation Technology for MOS, 323
`
`
`
`
`5.3.6 Short-Channel Devices, 323
`
`
`
`
`
`
`5.4 PROCESS SEQUENCE FOR FABRICATING NMOS
`
`
`
`
`
`INVERTERS WITH DEPLETION-MODE LOADS
`324
`
`
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`
`
`
`
`
`
`
`
`
`5.4.1. Operation of an NMOSInverter with a Depletion-Mode Load, 324
`
`
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`
`
`
`
`5.4.2 Process Sequence of a Basic E-D NMOSIC Technology, 327
`
`
`
`
`
`5.4.2.1 Starting Material.
`
`
`
`
`
`
`
`5.4.2.2 Active Region and Field Region Definitions.
`
`
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`
`
`5.4.2.3 Gate-Oxide Growth and Threshold-Voltage Adjust Implant
`
`
`
`
`
`
`
`5.4.2.4 Polysilicon Deposition and Patterning.
`
`
`
`
`
`
`
`5.4.2.5 Formation of the Source and Drain Regions.
`5.4.2.6 Contact Formation.
`
`
`
`
`
`
`
`5.4.2.7 Metallization Deposition and Patterning.
`
`
`
`
`
`
`
`5.4.2.8 Passivation Layer and Pad Mask.
`
`
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`
`
`
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`
`
`
`5.5 SHORT-CHANNEL EFFECTS AND HOW THEY IMPACT MOS
`
`
`
`338
`PROCESSING
`
`
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`
`
`
`
`
`
`
`
`5.5.1 Effect of Gate Dimensions on Threshold Voltage, 338
`
`
`
`
`
`
`5.5.1.1 Short Channel Threshold Voltage Effect.
`
`
`
`
`
`
`
`5.5.1.2 Narrow Gate-Width Effect on Threshold Voltage.
`
`
`
`
`
`5.5.2 Short-Channel Effects on Subthreshold Currents (Punchthrough
`
`
`
`
`
`
`and Drain-induced Barrier Lowering), 341
`
`
`
`
`
`
`5.5.3 Short-Channel Effects on I-V Characteristics, 343
`
`
`
`
`
`5.5.4 Summary of Short-Channel Effects
`
`
`
`
`
`
`on the Fabrication of MOS ICs, 346
`
`
`
`
`
`
`
`
`
`
`
`5.6 HOT-CARRIER EFFECTS IN MOSFETS
`
`
`
`348
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`
`
`
`5.6.1 Substrate Currents Due to Hot Carriers, 349
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`xvii
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`
`
`5.6.2 Hot-Carrier injection into the Gate Oxide, 350
`
`
`
`
`
`
`5.6.3 Device-Performance Degradation Due to Hot-Carrier Effects, 352
`
`
`
`
`
`
`
`
`5.6.4 Techniques for Reducing Hot-Carrier Degradation, 354
`
`
`
`
`
`5.6.5 Lightly Doped Drains, 354
`
`
`
`
`
`
`5.6.5.1 Drain Engineeringfor Optimum LDD Structures.
`
`
`
`
`5.6.5.2 Asymmetrical Characteristics ofLDD MOSFETs.
`
`
`
`
`
`
`
`
`
`
`5.6.6 The Impact of IC Processing
`
`
`
`
`
`on Hot-Carrier Device Degradation, 361
`
`
`
`
`
`
`
`5.6.7 Hot-Carrier Effects in PMOS Transistors, 362
`
`
`
`5.6.8 Gate-Induced Drain-Leakage Current, 363
`
`
`
`
`
`REFERENCES
`
`
`
`
`363
`
`
`
`CHAP. 6 - CMOS PROCESS INTEGRATION
`
`
`
`
`
`
`
`368
`
`
`
`
`6.1
`
`
`
`
`INTRODUCTION TO CMOS TECHNOLOGY
`
`
`
`368
`
`
`
`
`
`
`
`
`
`
`
`
`6.1.1 The Power-Dissipation Crisis of VLSI and How CMOS Cameto the
`
`
`
`
`
`Rescue, 368
`
`
`
`
`
`
`6.1.2 Historical Evolution of CMOS, 370
`
`
`
`
`
`
`6.1.3 Operation of CMOSInverters, 373
`
`
`
`
`
`6.1.4 Advantages (and Disadvantages)
`
`
`
`
`
`of Modern CMOSTechnologies, 376
`
`
`6.1.4.1 Device/Chip Performance Advantages.
`
`
`
`
`
`6.1.4.2 Reliability Advantages of CMOS.
`
`
`
`
`6.1.4.3 Circuit Design Advantages of CMOS.
`
`
`
`
`
`
`
`
`6.1.4.4 Cost Analysis of CMOS.
`
`
`
`
`6.1.5 Disadvantages of CMOS, 380
`
`
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`
`
`
`
`
`
`THE WELL CONTROVERSY IN CMOS_381
`6.2
`
`
`
`
`
`
`
`
`
`6.2.1 The Need for Wells in CMOS, 381
`
`
`
`
`6.2.2 p-Well CMOS, 383
`
`
`
`
`6.2.3 n-WellCMOS, 384
`
`
`
`
`
`6.2.4 CMOS on Epitaxial Substrates, 385
`
`
`
`
`6.2.5 Twin-Well CMOS, 387
`
`
`
`
`6.2.6 Retrograde-Well CMOS, 389
`
`
`
`
`
`6.2.7 Summary of CMOS Well-Technology Issues, 392
`
`
`
`
`
`
`
`
`
`
`6.3 p-CHANNEL DEVICES IN CMOS~=
`
`
`
`392
`
`
`
`
`
`
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`
`
`6.3.1 PMOSDevices with n*+-Polysilicon Gates, 392
`
`
`6.3.1.1 Punchthrough Susceptibility.
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`xviii
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`CONTENTS
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`6.3.2 PMOS Devices with p*-Polysilicon Gates, 397
`6.3.3 Gate Materials having Symmetrical Work Functions (with Respect to
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`both NMOS and PMOSDevices), 398
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`6.4 LATCHUP IN CMOS
`
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`400
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`6.4.1 Parasitic pnpn Structures in CMOSCircuits, 400
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`6.4.2 Circuit Behavior of pnpn Diodes, 402
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`6.4.3 Device Physics Behavior of pnpn Diodes, 403
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`6.4.4 Summary of Conditions That Must Exist
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`in Order for Latchup to Occur, 406
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`6.4.5 Circuit Behavior of Actual pnpn Structures in CMOSCircuits, 406
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`6.4.5.1 Value ofB in CMOS Vertical Parasitic Bipolar Transistors.
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`6.4.5.2 Value ofB in CMOSLateral Parasitic Bipolar Transistors.
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`6.4.6 Circuit and Device Effects that Induce Latchup, 408
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`6.4.6.1 An external stimulusforward-biases the emitter-base of one transistor,
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`andits collector current then turns-on the secondtransistor.
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`6.4.6.2 An external stimulus causes current to flow through both bypass
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`resistors,forward-biasing one or both bipolar transistors.
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`6.4.6.3 Current is shunted through one of the parasitic transistors by some
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`degradation mechanism, and the resulting collector current flows
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`through the bypassresistor of the second transistor and turns it on.
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`6.4.7 Test Methods for Characterizing Latchup, 410
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`6.4.7.1 Modelling Latchup in CMOS Technology.
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`6.4.8 Techniques for Reduction
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`or Elimination of Latchup Susceptibility, 413
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`6.4.8.1 Processing Techniques that Reduce the Current Gains of the Parasitic
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`Bipolar Transistors.
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`6.4.8.2 Processing Techniques that Reduce Rsybh and Ry or Eliminate the
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`pnpn Structure.
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`6.4.8.3 Circuit Layout Techniques used to Decouple Parasitic Bipolar
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`Transistors.
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`6.5 CMOS ISOLATION TECHNOLOGY
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`419
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`6.5.1 TrenchIsolation for CMOS, 425
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`6.5.2 Isolation by Selective-Epitaxial Growth for CMOS, 426
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`6.6 CMOS PROCESS SEQUENCES
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`428
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`6.6.1 Basic n-Well CMOS Process Sequence, 428
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`6.6.2 Twin-Well CMOS Process Sequence, 431
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`6.6.2.1 Starting Material.
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`6.6.2.2 Forming the Wells and Channel Stops.
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`Page 14 of 33
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`Page 14 of 33
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`CONTENTS
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`xix
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`6.6.2.3 Active and Field Region Definition.
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`6.6.2.4 Gate Oxide Growth and Threshold Voltage Adjustment.
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`6.6.2.5 Polysilicon Deposition and Patterning.
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`6.6.2.6 Formation of the SourcelDrain Regions.
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`6.6.2.7 CVD Oxide Deposition and Contact Formation.
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`6.6.2.8 Metal 1 Deposition and Patterning.
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`6.6.2.9 Intermetal Dielectric Deposition!Planarization and Via Patterning.
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`6.6.2.10 Metal 2 Deposition and Patterning.
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`6.6.2.11 Passivation Layer Deposition and Patterning.
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`6.7 MISCELLANEOUS CMOS TOPICS
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`441
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`6.7.1 Electrostatic Discharge Protection for CMOS, 441
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`6.7.1.1 Diode Protection.
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`6.7.1.2 Node-to-Node Punchthrough.
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`6.7.1.3 Gate-Controlled Breakdown Structure.
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`6.7.1.4 pnpn-Diode ESD Protection for Advanced CMOSCircuits.
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`6.7.2 Power Supply Voltage Levels for Future CMOS, 446
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`6.7.3 Low-Temperature CMOS, 446
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`6.7.4 Three-Dimensional CMOS, 447
`
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`REFERENCES
`
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`447
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`
`CHAPTER 7 - BIPOLAR AND
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`BICMOS PROCESS INTEGRATION |
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`453
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`7.1 BIPOLAR TRANSISTOR STRUCTURES
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`FOR INTEGRATED CIRCUITS
`453
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`7.1.1 The Transistor Action 454
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`7.1.1.1 Basic Bipolar Transistor Physics.
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`7.1.1.2 Bipolar Transistor Current Gain.
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`7.1.2 Integrated-Circuit Transistor Stuctures 458
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`7.2 DIGITAL CIRCUITS USING BIPOLAR TRANSISTORS
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`459
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`7.2.1 Basic Bipolar-Transistor Inverter Circuits 459
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`7.2.2 Bipolar Digital-Logic-Circuit Families 460
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`7.3 MAXIMIZING BIPOLAR TRANSISTOR PERFORMANCE
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`THROUGH DEVICE DESIGN & PROCESSING TECHNOLOGY
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`464
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`Page 15 of 33
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`Page 15 of 33
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`XX
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`CONTENTS
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`7.3.1 CurrentGain 464
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`7.3.2 Early Voltage 466
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`7.3.3 High-Level Injection Effects (Kirk Effect) 467
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`7.3.4 Operating-Voltage Limits in Bipolar Transistors 468
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`7.3.4.1 Reachthrough Breakdown.
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`7.3.4.2 Punchthrough Breakdown.
`7.3.4.3 Breakdown Voltage and High-Level Injection Limits in Advanced
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`Bipolar Transistors.
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`7.3.5 Parasitic Series Resistancesin Bipolar Transistors 472
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`7.3.5.1 Collector Series Resistance, Rc.
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`7.3.5.2 Base Series Resistance, Rp.
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`7.3.5.3 Base-Spreading Resistance, Rp2 (and Emitter Current Crowding).
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`7.3.5.4 Emitter Series Resistance, RR.
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`7.3.6 Parasitic Junction Capacitancesin Bipolar Transistors 475
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`7.3.6.1 Storage Capacitances in Bipolar Transistors.
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`7.3.7 Bipolar Transistor Unity-Gain Frequency, fT 477
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`7.3.8 First Order non Device Design 477
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`7.3.9 Switching Speed Behavior in Bipolar ICs 478
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`7.3.9.1 Propagation-Delay Time Calculation in Bipolar Transistors.
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`7.3.9.2 Propagation Delay in Digital MOS versus Digital Bipolar Circuits.
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`7.3.9.3 General Switching Speed Behavior ofDigital Bipolar Circuits.
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`7.4 NON-OXIDE-ISOLATED BIPOLAR npn TRANSISTOR
`
`
`STRUCTURES
`482
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`7.4.1 Triple-Diffused (3D) Process 483 °
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`7.5 STANDARD-BURIED-COLLECTOR PROCESS
`
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`483
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`7.5.1 Characteristics of non Transistors Fabricated with the Standard-
`
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`
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`Buried-Collector (SBC) Process
`483
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`7.5.1.1 Limitations of Junction-Isolated SBC Transistorsfor VLSI Circuits.
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`7.5.2 Standard-Buried-Collector Process Flow 486
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`7.5.2.1 Starting Material.
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`7.5.2.2 Buried Layer Formation.
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`7.5.2.3 Epitaxial Growth.
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`7.5.2.4 Formation of Isolation Regions.
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`7.5.2.5 Deep-Collector Contact Formation (Optional).
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`7.5.2.6 Base Region Formation.
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`7.5.2.7 Emitter Region Formation.
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`7.5.2.8 Contact and Interconnect Layer Formation.
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`7.5.2.9 Washed Emitters.
`7.5.2.10 Schottky Contacts.
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`—
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`7.6 OXIDE-ISOLATED BIPOLAR TRANSISTORS
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`498
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`Page 16 of 33
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`Page 16 of 33
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`CONTENTS
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`xxi
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`7.7 ADVANCED BIPOLAR TRANSISITOR STRUCTURES FOR
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`VLSI AND ULSI
`500
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`
`7.8 ADVANCED EMITTER STRUCTURES
`
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`
`501
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`
`
`501
`7.8.1 Polysilicon Emitters
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`
`7.8.1.1 Models that Describe Polysilicon-Emitter Behavior.
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`
`7.8.1.2 Process Technology for Polysilicon-Emitter Fabrication.
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`
`7.8.2 Heterojunction Bipolar Transistors (HBTs)
`506
`
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`
`7.9 SELF-ALIGNED BIPOLAR STRUCTURES
`
`
`
`510
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`7.9.1 Double-Polysilicon Self-Aligned Structures 510
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`7.9.1.1 Limitations of Double-Polysilicon SA Structures.
`
`
`7.9.1.2 Current-Gain Degradation Due to Sidewall Injection in SA Bipolar
`
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`
`Structures.
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`7.9.1.3 Link-Up Region Formation.
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`7.9.2 Single-Polysilicon Self-Aligned Bipolar Structures 516
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`7.9.3 Sldewall-Base-COntact Structures (SICOS) 520
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`7.10 TRENCH-ISOLATED BIPOLAR TRANSISTORS
`
`
`
`522
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`7.11 BICMOS TECHNOLOGY
`
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`
`523
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`
`524
`7.11.1 Device and Circuit Advantages of BICMOS
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`7.11.1.1 Comparison ofBiCMOs and CMOSPropagation Delay Times.
`
`
`7.11.1.2 Power Consumption of BiCMOS versus CMOSGates.
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`7.11.1.3 Capability of Providing Either TTL or ECL Outputs From a
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`BiCMOS Chip.
`
`
`7.11.1.4 Process Complexity Increases Associated with BiCMOS.
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`7.11.15 Extending Process Equipment Life by Fabricating BiCMOS.
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`7.12 CLASSIFICATION OF BICMOS TECHNOLOGIES
`
`
`
`529
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`
`
`531
`7.12.1 Digital BICMOS Technology
`
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`
`
`7.12.1.1 Low-Cost Digital BiCMOS Technology.
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`
`
`7.12.1.2 High-Performance Digital BiCMOS.
`
`7.12.1.3 Device-Design Issues Related to Optimizing a High-Performance
`
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`
`
`Digital Modified-Twin-Well BiCMOSProcess.
`
`
`
`7.12.14 An Example Process Sequencefor Fabricating High-Performance 5-V
`
`
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`
`
`Digital BiCMOSICs.
`
`
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`
`
`543
`7.12.2 Process Integration of Analog/Digital BBCMOS
`
`
`
`
`7.12.2.1 Process-Integration Issues of Medium-Voltage Analog BiCMOS.
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`7.12.2.2 An Example of an Analog/Digital BiCMOS Process.
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`Page 17 of 33
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`Page 17 of 33
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`XXii
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`CONTENTS
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`
`551
`7.12.3 BICMOSApplications
`
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`
`
`7.12.3.1 Digital Logic Circuits and Gate Arrays.
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`
`
`
`7.12.3.2 Interface Driver Circuits.
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`
`
`7.12.3.3 BiCMOS SRAMs.
`
`
`7.12.3.4 Analog/Digital Applications.
`
`
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`
`
`7.13 Trends in BiCMOS Technology
`
`556
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`
`7.13 COMPLEMENTARY BIPOLAR (CB) TECHNOLOGY
`
`
`
`
`557
`
`
`
`REFERENCES
`
`
`
`560
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`
`
`
`
`CHAP. 8 -
`
`