`
`
`CVD OXIDE
`
`
`
`
`
` SILICON
`
`
`
`
`
`
`
`
`
`
`
`
`ISO-P process cri
`Fig. 1.
`
`
`
`
`
`before and after CMP pla
`
`
`
`
`
`Nevertheless,
`STI pia
`
`
`extremely long planarizing
`
`
`
`
`
`
`polishing in low density re
`
`
`
`
`T
`naturally polish faster.
`
`
`
`
`
`from the masking nitride in
`
`
`
`
`nitride in low density areas
`
`
`
`
`
`
`
`ratio is only about 3/1,
`thi
`
`
`
`
`is quite limited.
`Therefore
`
`
`
`
`
`
`ability of the CMP process.
`
`
`
`
`
`
`layout where the density va
`
`
`
`
`
`indicating the range of
`lev
`
`
`
`
`
`CMP process used for
`ISO-F
`
`
`
`
`
`approaching the size of
`a
`
`
`
`
`length is not desirable,
`h
`removal
`rates acro
`oxide
`
`
`
`
`
`
`thickness.
`The leveling le
`
`
`
`
`must therefore be optimized.
`
`
`
`
`
`
`
`
`The process used for
`
`
`
`
`
`
`
`Fig.
`1.
`A 20 nm layer o
`
`
`
`
`substrate,
`followed by dep
`
`
`
`
`
`and etching the a
`masking
`
`
`
`
`stack,
`the silicon substrate
`
`
`
`
`
`depth O
`-
`nm less
`100
`
`
`
`thickness.
`Trench depths ir
`
`
`
`After
`removing |
`study.
`
`
`
`
`chemically,
`20
`nm
`40
`-
`sidewalls of the trenches.
`
`
`
`
`
`iL
`
`
`
`
`
`OXIDE-FILLED TRENCH ISOLATION PLANARIZED
`
`
`
`USING CHEMICAL/MECHANICAL POLISHING
`J. M. Pierce, P. Renteln, W. R. Burger! and S. T. Ahn?
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fairchild Research Center,
`
`
`
`National Semiconductor Corporation
`
`
`
`
`Santa Clara, CA 95052
`
`
`
`
`
`
`
`
`is
`An oxide-filled shallow trench isolation process
`
`
`
`
`
`
`described, which
`includes
`a chemical/mechanical polishing
`
`
`
`
`
`
`
`
`
`
`
`the
`step to planarize the CVD oxide used to fill
`(CMP)
`
`
`
`
`
`
`
`trenches.
`The
`stringent
`leveling requirements
`for
`this
`
`
`
`
`
`
`
`
`
`application are discussed, and a newly developed CMP process
`
`
`
`
`
`
`
`
`
`
`The
`is demonstrated with a leveling length of several mm.
`
`
`
`
`
`
`
`
`
`
`isolation process has been applied to both CMOS and bipolar
`
`
`
`
`devices with good results.
`
`INTRODUCTION
`
`
`
`
`
`
`
`
`
`
`
`
`Shallow trench isolation (STI) filled with CVD oxide is attractive
`
`
`
`
`
`
`
`
`
`
`
`for
`scaled ULSI,
`because the encroachment
`and
`stress problems
`
`
`
`
`
`
`
`
`
`
`associated with field oxide growth are largely avoided.
`Figure 1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a simplified STI process flow,
`a key requirement of which is
`shows
`
`
`
`
`
`
`
`
`
`
`
`planarization of
`the CVD oxide
`to expose
`the nitride mask while
`
`
`
`
`
`
`
`
`
`
`
`controlling the relative heights of the active areas and field areas.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The final height of the field oxide must be higher than that of the
`
`
`
`
`
`
`
`
`
`
`
`
`active silicon under the nitride mask, but not high enough to produce
`
`
`
`
`
`
`
`
`
`
`
`
`step.
`a substantial
`A reasonable range for the step is 0-100 nm,
`
`
`
`
`
`
`
`
`
`which poses
`severe challenge for
`the planarization process.
`a
`
`
`
`
`
`
`
`
`
`
`
`Previous STI processes [1,2] have used planarizing resist over the CVD
`
`
`
`
`
`
`
`
`
`
`
`oxide and RIE etchback of the composite stack.
`Field areas wider
`
`
`
`
`
`
`
`
`
`
`
`
`than a
`few micrometers must be protected by a blocking resist layer
`
`
`
`
`
`
`
`
`patterned using an extra photomasking step,
`because _planarizing
`
`
`
`
`
`
`
`
`resists lose leveling ability beyond this range. Chemical/mechanical
`
`
`
`
`
`
`
`
`
`
`
`polishing (CMP) has also been used in conjunction with resist etchback
`
`
`
`
`
`
`
`
`
`
`to improve process margins [2]. These processes are obviously complex
`
`
`
`
`
`
`
`
`
`
`and expensive, and accumulation of tolerances associated with the many
`
`
`
`
`
`
`
`
`
`
`steps makes it difficult to achieve the final
`tolerances required.
`
`
`
`
`
`
`
`
`
`
`
`
`improved CMP process has been used alone to
`an
`In this work,
`
`
`
`
`
`
`
`
`
`
`
`
`planarize STI, without resist etchback and without the use of an extra
`
`
`
`
`
`
`
`
`
`
`masking step.
`We have named this simplified process
`ISO-P.
`The
`
`
`
`
`
`
`
`
`
`
`improved CMP process which makes
`the ISO-P process feasible levels
`
`
`
`
`
`
`
`
`
`
`over much longer distances than those leveled by spin-on processes.
`
`
`
`
`
`
`
`
`
`
`
`
`In addition, exposure of the masking nitride results in a reduction of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the polishing rate of oxide in nearby field areas to match that of the
`
`
`
`
`
`
`
`
`
`
`
`
`nitride.
`Thus
`the nitride mask tends
`to act as
`a polishing stop
`
`
`ayer.
`
`650
`
`
`
`
`
`Page 1 of 8
`
`TSMC Exhibit 1043
`TSMCv.IP Bridge
`IPR2016-01246
`
`
`
`
`
`
`Page 1 of 8
`
`TSMC Exhibit 1043
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`SILICON
`
`CVD OXIDE
`[SSS
`
`
`
`
`
`
`
`
`
`
`
`
`ION PLANARIZED
`
`\L POLISHING
`
`urger! and S. T. Ahn2
`
`
`
`
`
`Center,
`
`Corporation
`5052
`
`
`
`
`
`
`
`
`is
`h isolation process
`
`
`cal/mechanical polishing
`
`
`
`
`
`oxide used to fill
`the
`
`
`
`
`for
`requirements
`)
`this
`
`
`
`
`fly developed CMP process
`
`
`
`
`
`The
`gth of several mm.
`
`
`
`
`
`to both CMOS and bipolar
`
`
`
`
`
`
`
`1 with CVD oxide is attractive
`
`
`
`
`achment
`and
`stress problems
`
`
`
`largely avoided.
`Figure 1
`
`
`
`
`
`key requirement of which is
`
`
`
`
`
`the nitride mask while
`pose
`
`
`
`
`
`active areas and field areas.
`
`
`
`
`
`
`
`t be higher than that of the
`
`
`
`
`
`
`ut not high enough to produce
`
`
`
`
`
`
`
`e for the step is 0-100 nm,
`
`
`
`the planarization process.
`
`
`
`
`
`lanarizing resist over the CVD
`
`
`
`
`
`Field areas wider
`e stack.
`
`
`
`
`
`
`ad by a blocking resist layer
`
`
`
`
`ng
`step,
`because .planarizing
`is range. Chemical/mechanical
`
`
`
`
`
`
`
`njunction with resist etchback
`
`
`
`
`rocesses are obviously complex
`
`
`
`
`
`ances associated with the many
`
`
`
`tolerances required.
`Final
`
`
`
`
`
`
`
`vcess has been used alone to
`
`
`
`
`
`
`
`nd without the use of an extra
`
`
`
`
`The
`mplified process
`ISO-P.
`
`
`
`
`ISO-P process
`feasible levels
`
`
`
`
`leveled by spin-on processes.
`
`
`
`
`
`
`ride results in a reduction of
`
`
`
`
`
`
`
`leld areas to match that of the
`
`
`
`
`
`
`
`to act as
`a polishing stop
`;
`
`
`
`
`
`ISO-P process cross-sections
`Fig. 1.
`
`
`
`
`
`before and after CMP planarization.
`
`
`
`
`
`
`
`Fig. 2. Typical wafer
`
`
`
`
`layout showing need for
`
`
`
`long distance leveling.
`
`
`
`
`
`
`
`
`
`an
`Nevertheless, STI planarization using CMP alone requires
`
`
`
`
`
`
`
`
`
`
`extremely long planarizing range or
`leveling length to avoid over
`
`
`
`
`
`
`
`
`
`
`
`polishing in low density regions of the circuit where elevated areas
`
`
`
`
`
`
`
`
`
`
`
`naturally polish faster.
`The key requirement
`is to remove all oxide
`
`
`
`
`
`
`
`
`
`
`
`from the masking nitride in dense areas without breaking through the
`
`
`
`
`
`
`
`
`
`
`nitride in low density areas.
`Since the oxide/nitride polishing rate
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ratio is only about 3/1,
`the stopping power of a 150 nm nitride layer
`
`
`
`
`
`
`
`
`
`
`
`
`is quite limited. Therefore most of the burden falls on the leveling
`
`
`
`
`
`
`
`
`
`
`
`
`ability of
`the CMP process.
`Figure 2
`shows a typical memory wafer
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layout where the density varies from high to low to high over 5 mm,
`
`
`
`
`
`
`
`
`
`
`
`indicating the range of leveling required.
`One can conclude that a
`
`
`
`
`
`
`
`
`
`
`a
`CMP process used for
`ISO-P isolation must have
`leveling length
`
`
`
`
`
`
`
`
`
`
`
`approaching the size of a chip.
`A significantly greater
`leveling
`
`
`
`
`
`
`
`
`
`
`length is not desirable, however, because it results in nonuniform
`
`
`
`
`
`
`
`
`
`
`
`oxide removal
`rates across
`a wafer due
`to variations
`in wafer
`
`
`
`
`
`
`
`
`
`
`
`thickness.
`The leveling length of a CMP process for ISOQ-P isolation
`
`
`
`
`must therefore be optimized.
`
`
`
`PROCESS DETAILS
`
`
`
`
`
`
`
`
`
`
`
`
`in
`shown
`this work followed the scheme
`The process used for
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig.
`thermal
`SiO, was grown on the silicon
`1.
`A 20 nm layer of
`
`
`
`
`
`
`
`
`
`
`
`
`substrate,
`followed by deposition of
`nm of CVD Si3Ng.
`150
`After
`
`
`
`
`
`
`
`
`
`
`and etching the active area pattern in the oxide/nitride
`masking
`
`
`
`
`
`
`
`
`
`
`
`the silicon substrate was anisotropically etched using RIE to a
`stack,
`
`
`
`
`
`
`
`
`
`
`
`depth 0
`-
`nm Tess
`than the desired final
`isolation oxide
`100
`
`
`
`
`
`
`
`
`
`
`
`
`
`thickness.
`Trench depths in the range 0.5 - 1.0 um were used in this
`
`
`
`
`
`
`
`
`
`removing the photoresist
`and cleaning the wafers
`After
`study.
`
`
`
`
`
`
`
`
`
`
`
`chemically,
`20
`40 nm of
`thermal SiO) was
`to seal
`the
`grown
`-
`
`
`
`
`
`
`
`
`
`
`
`sidewalls of the trenches.
`At this point, channel stop implants were
`651
`
`
`
`
`Page 2 of 8
`
`Page 2 of 8
`
`

`

`
` Figure 4 shows SEM vic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the trench fill oxide was deposited using
`made in some cases. Next,
`
`
`
`
`and before stripping the
`
`
`
`
`
`
`
`
`
`
`
`CVD to a thickness approximately 50% greater than the trench depth.
`been added to improve cont
`
`
`
`
`
`
`
`
`
`quality local planarizati
`
`
`
`
`
`
`
`
`
`CMP planarization was carried out using a glass-impregnated
`
`
`
`
`
`is shown in Figs. 5-6.
`F
`
`
`
`
`
`
`
`
`
`
`polyurethane polishing pad with fumed colloidal
`silica slurry.
`
`
`
`
`
`
`
`
`memory wafer before and a
`
`
`
`
`
`
`
`
`
`
`Polishing was
`terminated when
`the nitride over
`the active silicon
`
`
`
`
`
`
`one array to the next acrc
`
`
`
`
`
`
`
`
`
`areas was completely exposed.
`The pad,
`sturry and polishing
`The initial step height
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`parameters were optimized to produce the leveling results discussed
`
`
`
`
`
`
`
`
`Fig.
`5C shows,
`the total
`
`
`
`
`
`
`
`
`
`below. After planarization,
`the nitride/oxide stack was stripped, and
`than 40 nm. At this scale,
`
`
`
`
`
`
`
`
`
`
`
`
`
`the devices were completed using normal process steps.
`
`
`
`
`
`it necessary to measure a
`
`
`
`
`
`
`Figure 6 shows the remain
`
`
`
`
`series of adjacent points
` RESULTS
`
`
`
`
`
`
`
`
`
`
`
`
`
`Figure 3
`shows
`the leveling characteristics of the CMP process
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`used in this work.
`Previously reported results [3] are also shown for
`
`
`
`
`
`
`
`
`
`
`
`
`
`comparison.
`The parameter used in Fig. 3 to characterize leveling is
`
`
`
`
`
`
`
`
`
`
`the planarization rate,
`a useful quantitative measure of
`the
`p,
`
`
`
`
`
`
`
`
`
`
`
`
`planarizing ability of
`CMP processes
`on wide patterns
`[3].
`For
`
`
`
`
`
`
`
`
`
`
`
`pattern widths of approximately 1 mm or more, CMP processes quickly
`
`
`
`
`
`
`
`
`
`
`
`
`smooth the sharp steps at pattern edges and begin eroding oxide from
`
`
`
`
`
`
`
`
`
`
`low areas as well as high ones. Nevertheless, planarization continues
`
`
`
`
`
`
`
`
`
`
`
`
`because high areas are eroded faster than low ones.
`In this regime,
`
`
`
`
`
`
`
`
`
`
`
`the remaining step height A is decreases exponentially with the mean
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`amount, d, of oxide removed, and p is defined to be the slope of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In(A) vs.-d line.
`As Fig. 3 indicates, p is high for narrow patterns
`
`
`
`
`
`
`
`
`
`
`and declines
`for wider ones.
`The current process
`shows useful
`
`
`
`
`
`
`
`
`
`
`
`
`
`planarization out
`to 5 mm widths, whichis in the range needed for
`ULSI
`isolation.
`For example,
`p = 2 um) at w= 5 mm implies that
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the residua]
`step height of a 5 mm wide pattern can be reduced by a
`
`
`
`
`
`
`
`
`
`
`
`
`factor of e“
`= 7.4 by polishing away 1 um of oxide.
`5
`
`= 0
`
`
`
`
`wo
`
`
`
`tb
`
`
`
`
`
`
`>
`
`
`
`
`
`CURRENT
`PROCESS
`
`
`
`PREVIOUS
`
`PROCESS
`
`
`
`
`
`;
`
`
`
`
`Fig. 3. Leveling
`characteristics of
`
`
`
`
`
`improved CMP process
`s
`
`
`
`compared with process
`
`
`reported previously [3].
`
`
`
`1
`
`3
`2
`4
`PATTERN WIDTH (mm)
`
`
`
`5
`
`
`
`6
`
`
`
`652
`
`
`
`
`
`
`
`
`
`
`
`Fig. 4. SEM cross-sect
`
`
`
`planarization.
`A poly
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PLANARIZATIONRATE(um™')
`
`
`
`
`
`
`
`
`
`
`Page 3 of 8
`
`
`
`Page 3 of 8
`
`

`

`
`
`
`
`
`
`
`il] oxide was deposited using
`
`
`
`
`
`ter than the trench depth.
`
`
`
`
`
`t using a glass-impregnated
`
`
`
`
`ed colloidal
`silica slurry.
`ide over
`the active silicon
`
`
`
`
`
`
`
`
`
`
`pad,
`slurry and polishing
`
`
`
`
`e
`leveling results discussed
`
`
`
`
`
`oxide stack was stripped, and
`
`
`rocess steps.
`
`
`
`
`
`
`the CMP process
`teristics of
`
`
`
`
`
`
`‘esults [3] are also shown for
`
`
`
`
`
`3 to characterize leveling is
`
`
`
`
`quantitative measure of
`the
`
`
`
`
`
`on wide patterns
`[3].
`For
`
`
`
`
`
`/ more, CMP processes quickly
`
`
`
`
`
`and begin eroding oxide from
`
`
`
`less, planarization continues
`
`
`
`
`
`
`
`in low ones.
`In this regime,
`
`
`
`
`
`; exponentially with the mean
`
`
`
`
`
`
`
`fined to be the slope of the
`
`
`
`
`
`
`p is high for narrow patterns
`
`
`
`
`urrent process
`shows useful
`
`
`
`
`
`
`).is in the range needed for
`
`
`“Vat w= 5 mm implies that
`
`
`
`
`
`
`
`
`
`
`
`
`
`| pattern can be reduced by a
`
`of oxide.
`
`
`
`
`
`
`Fig. 3. Leveling
`characteristics of
`
`
`
`
`
`improved CMP process
`
`
`
`compared with process
`
`
`reported previously [3].
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Figure 4 shows SEM views of an ISO-P wafer after CMP planarization
`
`
`
`
`
`
`
`
`
`
`
`and before stripping the exposed nitride mask.
`A poly-Si
`layer has
`
`
`
`
`
`
`
`
`
`
`been added to improve contrast and delineate surface topography. High
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`quality local planarization is evident.
`Long distance planarization
`
`
`
`
`
`
`
`
`
`
`
`
`
`is shown in Figs. 5-6.
`Figure 5 shows surface profilometer scans of a
`
`
`
`
`
`
`
`
`
`
`
`
`memory wafer before and after planarization.
`The 3 mm scans run from
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`one array to the next across a low density region more than 1 mm wide.
`
`
`
`
`
`
`
`
`
`
`
`
`
`initial step height was 1.2 um.
`the expanded scale trace in
`The
`As
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig.
`5C shows,
`the total
`remaining amplitude over a 3 mm span is less
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`than 40 nm. At this scale,
`the bow in the wafer is significant, making
`
`
`
`
`
`
`
`
`
`
`it necessary to measure actual
`film thicknesses to evaluate leveling.
`
`
`
`
`
`
`
`
`
`
`
`
`Figure 6 shows
`the remaining nitride and field oxide thicknesses at a
`
`
`
`
`
`
`
`
`
`
`
`
`
`series of adjacent points along a 12 mm path crossing the low density
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 4. SEM cross-sections of ISO-P structures after CMP
`
`
`
`
`
`
`
`
`planarization.
`layer was added to improve contrast.
`A poly-Si
`
`
`
`653
`
`
`
`
`Page 4 of 8
`
`Page 4 of 8
`
`

`

`
`
`POSITIONONWAFER(mm)
`
`
`
`
`
`
`
`
`
`
`
`1 0
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Oo
`
`ym»
`
`-
`
`
`
`1320
`
`
`Qo
`Qa
`a
`o
`ao
`~t
`
`
`
`N NON
`+r ee
`
`
`
`
`
`
`
`
`
`
`
`160
`
`
`
`
`
`140
`
`
`
`
`
`120
`
`
`
`
`
`100
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The orig
`region of Fig. 5.
`
`
`
`
`
`to 133 nm with a variation «
`
`
`
`
`
`nm. This excellent planariz
`
`
`
`
`between nitride and oxide m
`
`
`
`
`sufficient extra margin to a
`
`
`
`deposition and CMP.
`
`
`
`
`
`
`
`The
`b
`ISOQ-P process has
`
`
`
`
`devices.
`No significant deg
`
`
`
`
`
`which could be attributed to
`
`
`
`
`encroachment of STI means
`tl
`
`
`
`
`
`
`is available for active devi
`
`the transconductances of NM
`
`
`
`
`
`
`
`T
`LOCOS
`isolated controls.
`
`
`
`
`
`
`are approximately 0.7 um gre
`reduced encroachment.
`
`
`
`2000
`
`
`
`—
`
`a—
`
`
`£
`uu
`oS
`
`
`
`1000
`
`
`
`iso-P
`
`uc
`
`<o2
`
`
`
`
`wo
`Zz
`<[amy
`
`E
`
`2 R
`
`0
`
`0
`
`10
`
`
`NOMINAL CHANNEL |
`
`
`
`Planarization of shallow
`
`
`
`
`
`demonstrated, without resist
`
`
`
`
`
`masking step.
`A newly de
`
`
`
`
`
`
`
`
`leveling lengths in the ra
`
`
`
`
`bridge regions of varying
`
`
`
`
`isolation has been applied
`
`
`
`
`
`results, and the field oxide
`
` ao
`Fig.6.Remainingnitrideandfieldoxide
`
`over12mmspan.centeredonthesamelowdensityregion.
`
`23456789101112
`
`atadjacentpointsFigs.5and6are
`
`
`NITRIDETHICKNESS
`
`thickness
` POSITIONONWAFER
`
`
`
`
`(ui
`
`4) SSINNOIHL WI
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(wu) LHOISH 3OvsuNS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Expanded.(mm)Fig.5.SurfaceprofilesofISO-Pwafersover3mmspan.a.BeforeCMP.b.After.c.
`
`
`
`
`
`
`
`
`
`654
`
`
`
`
`
`Page 5 of 8
`
`Page 5 of 8
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The original 150 nm nitride mask has been reduced
`region of Fig. 5.
`to 133 nm with a variation of 12 nm.
`The oxide variation is about 40
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`nm. This excellent planarization coupled with the 1/3 etch rate ratio
`
`
`
`
`
`
`
`
`
`
`
`
`between nitride and oxide means
`that a 150 nm nitride mask provides
`
`
`
`
`
`
`
`
`
`sufficient extra margin to accommodate global nonuniformities in oxide
`
`
`
`deposition and CMP.
`
`
`
`
`
`
`
`
`
`
`
`
`
`The
`ISO-P process has been used to isolate both MOS and bipolar
`
`
`
`
`
`
`
`
`
`devices.
`No significant degradation in device properties was observed
`
`
`
`
`
`
`
`
`
`
`
`
`‘which could be attributed to the CMP process, and the essentially zero
`encroachment of STI means
`that an increased fraction of silicon area
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`is available for active devices.
`An example is shown in Fig. 7, where
`
`
`
`
`
`
`
`
`
`
`the transconductances of NMOS transistors are compared with those of
`LOCOS
`isolated controls.
`The effective widths of the ISQ-P devices
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`are approximately 0.7 um greater than those of the controls due to the
`reduced encroachment.
`
`
`
`2000
`
`
`
`
`
`mmspan.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`es
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1000
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 7. Transconductance
`
`
`
`
`
`of 2 um long NMOS
`transistors vs. drawn
`
`
`
`channel width.
`Increase
`
`
`
`
`
`
`
`in Wogp is 0.7 um.
`
`
`
`10
`
`20
`
`NOMINAL CHANNEL WIDTH (um)
`
`
`
`
`
`
`
`CONCLUSIONS
`
`
`
`
`
`
`
`
`
`
`
`Planarization of shallow trench isolation using CMP alone has been
`
`
`
`
`
`
`
`
`
`
`
`demonstrated, without resist etchback and without
`the use of an extra
`
`
`
`
`
`
`
`
`
`
`
`masking step.
`A newly developed CMP process was
`shown to produce
`
`
`
`
`
`
`
`
`
`
`
`
`leveling lengths
`in the range of several mm, which are required to
`
`
`
`
`
`
`
`
`
`
`bridge regions of varying density on
`typical ULSI circuits.
`The
`
`
`
`
`
`
`
`
`
`
`
`isolation has been applied to CMOS
`and bipolar devices with good
`
`
`
`
`
`
`
`
`
`results, and the field oxide encroachment is essentially zero.
`
`over12centeredonthesamelowdensityregion.
`
`eeeFigs.5and6are
`(mS) 0
`anpTET POSITIONONWAFER
`
`
`(mm)Fig.5.SurfaceprofilesofISO-Pwafersover3mmspan.a.BeforeCMP.b.After.c.Expanded.
`TRANSCONDUCTANCE
`lf|if}|ptrt+}ereCTENPTT[oTPa4
`
`
`
`(eyevA
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`655
`
`
`
`
`
`Page 6 of 8
`
`Page 6 of 8
`
`

`

`
`
`REFERENCES
`
`
`
`
`
`
`
`
`
`
`
`
`
`IEDM Tech. Digest, 1983, p. 27
`{1] T. Shibata et al.,
`
`
`
`
`
`
`
`
`
`
`
`IEDM Tech. Digest, 1989, p. 61
`[2] B. Davari et al.,
`
`
`
`
`
`
`
`
`
`[3] P. Renteln et al., Proc. 1990 VLSI Multilevel
`Interconnect
`
`
`
`Conf., p. 57
`Inc., Phoenix, AZ
`Present address: Motorola,
`
`
`
`
`
`
`
`
`
`
`
`
`Present address: Sharp Corp., Nara, Japan
`
`
`
`656
`
`
`Page 7 of 8
`
`
`
`
`
`REVIEW OF THIN O
`
`
`MEMORY 0.
`
`Electronic Devi
`
`
`
`
`
`Department of Elec
`
`
`
`University of Cincini
`
`
`
`
`
`The effect of varyin:
`
`
`
`
`thin oxynitride gate diele
`
`
`
`
`correlation among the c
`
`
`photoionization cross-secti
`
`
`
`properties (endurance, re
`
`
`
`nonvolatile memory devic:
`
`to 100 A resulted in higher
`
`
`
`
`
`
`
`
`
`injected charge and thus
`
`
`
`useful memory lifetime
`
`
`
`
`endurance was greater tt
`
`
`
`
`free dielectrics. The hyc
`
`
`
`silicon dangling bonds a:
`
`
`
`
`
`bandgapofsilicon nitride
`
`
`
`
`
`trapped in deep traps, yie
`of MNOSdevices.
`
`
`
`
`IN
`
`
`
`
`
`Amorphous silicon nitride
`
`
`
`
`chemical vapor deposition (LPC\
`
`
`
`
`and dichlorosilane (SiH2Cl9), pl
`insulators for non-volatile memo
`
`
`
`
`
`polysilicon/metal-nitride-oxide-si
`
`
`
`
`
`
`with the charge capture in memo
`referred to are electron or hole
`
`
`
`
`
`
`
`
`
`
`
`
`
`defects in the bandgapofthe sili
`
`
`
`
`
`
`devices are influenced by the cc
`
`
`
`
`
`nitride layer. The addition of ¢
`
`
`
`
`
`
`forming the oxynitridefilm [3], as
`
`
`
`
`
`during the film deposition proce
`
`
`
`
`properties.
`Interest in silicon 1
`
`
`
`Page 7 of 8
`
`

`

`
`|
`PROCEEDINGS OF THE .RGESCALESNWLONAL
`
`
`
`
`ALE INTEGRATION
`SYMPOSIUM ON ULTRA LARGE
`
`
`
`
`
`SCIENCE AND TECHNOLOGY
`
`
`
`
`
`
`
`
`I LSI SCIENCE AND TECHNOLOGY/1991
`
`
`
`
`
`
`
`
`
`
`Edited by
`
`
`
`John M. Andrews
`
`
`
`Naval Research Laboratory
`
`
`Washington, D.C.
`
`
`
`
`
`George K. Celler
`
`
`
`AT&T Bell Laboratories
`
`
`
`Murray Hill, New Jersey
`
`
`
`
`
`
`
`Assistant Editors
`
`
`
`
`Sam Broydo
`
`
`
`Wayne Bailey
`
`
`
`Jonathan Chapple-Soko!
`
`Linda Ephrath
`
`
`Steve Fonash
`
`
`Wayne Greene
`
`Bob Kostelak
`
`
`Hisham Massoud
`
`
`Ed Middlesworth
`
`
`Shyam Murarka
`Ken Monnig
`
`
`
`
`
`
`
`
`
`
`
`
`Carl Osburn
`
`Paul Nicollian
`
`
`
`Dan Peters
`
`
`Mark Pinto
`
`
`Gary Ray
`
`
`Arnold Reisman
`
`
`Dennis Schmidt
`
`
`Geraldine Schwartz
`
`Jimmie Wortman
`
`
`L-W. Wu
`
`
`
`
`
`|
`
`i
`‘
`
`ze'
`
`|
`
`{
`
`{
`
`|
`
`i |
`
`|
`
`|
`
`RY
`
`
`
`[BRA
`
`ARY
`
`
`
`|
`
`991 : proc
`
`
`
`Ht
`
`
`
`er
`
`
`Page 8 of 8
`
`ELECTRONICS AND DIELECTRIC SCIENCE AND TECHNOLOGY DIVISIONS
`
`
`
`Proceedings Volume 91-114
`
`
`THE ELECTROCHEMICAL SOCIETY, INC., 10 South Main St., Pennington, Nu 08534-2896
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 8 of 8
`
`