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`United States Patent 15
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`5,512,771
`[11] Patent Number:
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`Hiroki et al.
`[45] Date of Patent:
`Apr. 30, 1996
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`|0
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`[54] MOS TYPE SEMICONDUCTOR DEVICE
`HAVING A LOW CONCENTRATION
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`IMPURITY DIFFUSION REGION
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`[75]
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`Inventors: Akira Hiroki, Osaka; Kazumi
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`Kurimoto, Kobe; Shinji Odanaka,
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`Hirakata, all of Japan
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`[73] Assignee: Matsushita Electric Industrial Co.,
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`Ltd., Osaka, Japan
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`[21] Appl. No.: 147,866
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`[22] Filed:
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`Nov. 4, 1993
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`[30]
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`Foreign Application Priority Data
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`OTHER PUBLICATIONS
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`Huang, T. Y. et al., “A Novel Submicron LDD Transistor
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`Digest, pp. 742-745 (1986).
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`S. Hsia et al., “Polysilicon Oxidation Self—Aligned MOS
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`Ion Implantation Technique for VLSI” IEEE Electron
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`EPO,Partial European Search Report for counterpart appli-
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`cation EP93 1] 7804, mailed Dec. 28, 1993.
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`Primary Examiner—Steven H. Loke
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`Attorney, Agent, or Firm—Ratner & Prestia
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`Nov. 4, 1992
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`Nov. 4, 1992
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`[JP]
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`[JP]
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`Japam oo.esssssssscsseseeseeenees 4-294819
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`Sapam ieeeceessenereeeeeneee 4-294820
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`[37]
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`ABSTRACT
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`(51) Unt, C18 onecccecccsesccnenneee HOIL 29/76; HO1L 29/94;
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`HOIL 31/062; HO1L 31/113
`[52] U.S. C1. occeeseeesoeteneeene 257/369; 257/336; 257/344;
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`257/408
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`[58] Field of Search oocc eeesseenees 257/408, 336,
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`2571344, 369
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`[56]
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`References Cited
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`U.S. PATENT DOCUMENTS
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`8/1990 Parrillo oo... sesseeseeeeeeeseseresses 257/408
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`4/1992 Manukonda etal.
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`7/1992 Tignoret ab. wiesesesecsesesseeees 257/408
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`6/1993 Shimizu et al. eepees 437/35
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`8/1993) Hsu et al. we
`eeeeseerseeee 257/344
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`11/1993 Inuishi et al. oc esseeeenee 257/344
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`4,951,100
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`5,102,816
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`5,132,757
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`5,217,910
`
`5,241,203
`
`5,258,319
`
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`FOREIGN PATENT DOCUMENTS
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`An MOStype semiconductor device comprises a semicon-
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`ductor substrate including a p-type region doped with p-type
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`impurities and having a surface and an MOStransistor
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`formed in the p-type region, the MOStransistor including:
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`an n-type source region formed in the p-type region; an
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`n-type drain region formed in the p-type region and sepa-
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`rated from the n-type source region by a predetermined
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`distance; a channel region formed in the p-type region and
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`located between the n-type source and drain regions; a pair
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`of n-type impurity diffusion regions formed on both sides of
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`the channel region and having an impurity concentration
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`lower than that of the n-type source region;a gate insulating
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`film formed on the surface of the semiconductor substrate,
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`the gate insulating film directly covering the channel region
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`and the pair of n-type impurity diffusion regions; a gate
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`electrode formed onthe gate insulating film; and side walls
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`formed on the sides of the gate electrode, wherein each of
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`the side walls has a bottom portion extending along the
`surface of the semiconductor substrate from each sideof the
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`gate electrode, and each of the n-type source and drain
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`regions has a first portion covered with the bottom portion
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`61-112379=S/1986 Japan woecssseseststsesecsecteee 257/408
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`of the side wall and a second portion not covered with the
`5/1987
`Japan ....
`62-118578
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`bottom portion, a thicknessofthe first portion being smaller
`Japan ....
`3-109773
`5/1991
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`than that of the second portion. A method for fabricating
`3-272145 12/1991
`Japan ....
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`such an MOStype semiconductor device is also provided.
`4-58562
`2/1992
`Japan ....
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`5/1992
`Japan ....
`4-133333
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`WO9IT/15030 LO/T99L WIPO on. eescssesssseessseeserecentes 257/408
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`5 Claims, 9 Drawing Sheets
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`Page 1 of 22
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`TSMC Exhibit 1040
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 22
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`TSMC Exhibit 1040
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`Apr. 30, 1996
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`5,512,771
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`US. Patent
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`Sheet 1 of 9
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`U.S. Patent
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`Apr. 30, 1996
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`Sheet 2 of 9
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`5,512,771
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`US. Patent
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`Apr. 30, 1996
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`Sheet 3 of 9
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`5,512,771
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`"Fig7B.
`FIG.8B
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`Me "|CAL|
`| =
`5b
`6
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`RNG — |
`FIG.8C
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`FIG.7C
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`wr) Hid3d
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`PHOSPHORUS
`10X 10!“omS
`30 X 0c
`10X 108m
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`050075
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`SILICON SUBSTRATE
`185
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`[95
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`205
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`215
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`L-SHAPED SIDE WALL
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`yuayed*S'0
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`5,512,771
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`lO
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`FIG.
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`U.S. Patent
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`Apr. 30, 1996
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`Sheet 5 of 9
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`U.S. Patent
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`Sheet 6 of 9
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`Sheet 7 of 9
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`5,512,771 FIG.1SB
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`FIG.I3C
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`FIG.ISD
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`FIG. ISE
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`FIG. ISF
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`FIG. 14B
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`® FIG.I4A
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`U.S. Patent
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`FIG.14D
`gpg]
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`KSAT MRS
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`a
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`28
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`aZA
`SBS Ce anae
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`SAT MRS
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`FIG. I4E
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`U.S. Patent
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`Sheet 9 of 9
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`WY,LY
`KANE
`Le
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`33
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`FIG.I6
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`PRIOR ART
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`MMCASA
`3
`FG. eA
`36tr * FIG.I7B
`CRANEKL 31
`PRIOR ART
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`AsTu
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`5,912,771
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`1
`MOS TYPE SEMICONDUCTOR DEVICE
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`HAVING A LOW CONCENTRATION
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`IMPURITY DIFFUSION REGION
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`2
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`The width L,,, of the low-concentration diffusion regions
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`34 requires at least 0.1 xm. Therefore, for an MOStransistor
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`with the gate-drain overlap LDD structure, the effective
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`channel length L,, is shorter than the gate length L, by at
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`least 0.2 pm. Whenthe channellengthofthetransistoris half
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`a micronorless, the effective channel length L,, is as small
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`as 0.3 um or less. As a result, the infant degradation of the
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`characteristics of the device generally caused when the
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`channel thereof is shorter (short channel effects) becomes
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`more eminent, compared with the case of an LDD structure.
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`(2) Since the low-concentration diffusion regions 34 are
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`entirely located beneath the gate electrode 35,the drivability
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`of the transistor improves. However,
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`increase in the gate-to-drain capacitance. This significantly
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`lowers the driving characteristics of a circuit including the
`MOStransistor.
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`(3) When the thicknessof the gate oxide film 32 is 10 nm
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`or less, a tunnel current is induced between the energy
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`bands, which may become an additional cause of a leak
`current.
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`(4) At least two masking steps are required for forming the
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`low-concentration diffusion regions 34 and the high-con-
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`centration source/drain diffusion regions 33. For a CMOS
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`circuit, a total of four or more masking steps are required
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`including similar masking steps for forming a p-channel
`MOStransistor.
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`For the above reasons, favorable transistor characteristics
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`will not be obtained if the gate-drain overlap structure is
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`applied to an MOStransistor having a channellength ofhalf
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`a micron or less. Moreover, when it is applied to a CMOS
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`circuit, the entire fabricating process thereof will be further
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`complicated.
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`Now, problems of an MOS type semiconductor device
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`with the LDD structure will be described as follows by
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`showing the fabricating process thereof with reference to
`FIGS. 17A to 17C:
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`As shown in FIG. 17A, impurities of a second conduc-
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`tivity type such as phosphorus(P) ions are implanted into a
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`surface area of a semiconductor substrate 31 using a gate
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`electrode 35 as a mask, thereby forming the low-concentra-
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`tion diffusion regions 34. Thereafter, as shown in FIG. 17B,
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`an oxide film is first deposited on the semiconductor sub-
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`strate 31 covering the gate electrode 35 to a thickness of
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`approximately 200-250 nm. Then,the oxidefilm is removed
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`by anisotropic dry etching except portions thereof deposited
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`on the sides of the gate electrode 35. At this etching, since
`the width of the oxide film left unetched onthe sides of the
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`gate electrode 35,i.e., gate side walls 36 greatly depends on
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`the conditions of the etching, it is difficult to form the gate
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`side walls 36 with high accuracy. Therefore, when the width
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`of the resultant gate side walls 36 formed on thesides of the
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`gate electrode 35 is large as shown in FIG. 17C,
`the
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`high-concentration source/drain diffusion regions 33 formed
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`ductivity type such as As ions do not extend to reach a
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`portion beneath the gate electrode 35.
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`As a result, following problemsarise:
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`centration source/drain diffusion regions 33. For a CMOS
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`circuit, a total of four or more masking steps are required
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`including similar masking steps for forming a p-channel
`MOStransisior.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to a semiconductor device
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`and a methodfor fabricating the same. Morespecifically, the
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`present invention relates to an MOS(metal oxide semicon-
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`ductor) type semiconductor device and a complementary
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`MOS (CMOS)type semiconductor device, and a method for
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`fabricating the same.
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`2. Description of the Related Art
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`In recent years, in pursuit of a higher integration of a
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`VLSI (very large scale integrated circuit), an MOS type
`semiconductor device used for such a VLSI has been
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`increasingly miniaturized. At present, there is realized a
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`device having a channel length as small as half a micron. As
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`the device is miniaturized, however, the electric character-
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`istics of the device may be degraded by hotcarriers. This
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`brings a serious problem with regardto the reliability of the
`device.
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`In order to minimize the degradation of the device caused
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`by hot carriers and moreover to improve the device charac-
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`teristics such as transconductance,a gate-drain overlap LDD
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`(lightly doped drain) structure has been proposed. Examples
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`of such a structure includes an ITLDDstructure proposed in
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`T. Y. Hung, “IEEE 1986 IEDM”, Technical Digest, pp.
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`742-745 and a GOLD stmucture proposed in R. Izawa,
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`“IEEE Transaction on Electron Devices”, vol. 35, pp.
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`2088-2093, 1988.
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`‘Referring to FIG. 16, an MOStransistor having the
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`gate-drain overlap LDDstructure will be described.
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`Thetransistor includes n-type high-concentration source/
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`drain diffusion regions 33 and n-type low-concentration
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`diffusion regions 34 both of which are formed in a p-type
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`semiconductor substrate 31, a gate oxide film 32 formed on
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`a portion of the semiconductorsubstrate 31, a gate electrode
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`35 formed on the gate oxide film 32, and gate side walls 36
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`formed on both sides of the gate electrode 35. The high-
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`concentration source/drain diffusion regions 33 extend to
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`reach a portion beneath the ends of the gate electrode 35.
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`The low-concentration diffusion regions 34 are entirely
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`located beneath the gate electrode 35. With this structure, the
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`electric field generated laterally in the low-concentration
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`diffusion regions 34 is weakened by a potential applied to
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`the gate electrode 35 enoughto reduce the generation of hot
`carriers. Moreover, carriers in the low-concentration diffu-
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`sion regions 34 can be completely controlled by the gate
`electrode 35, and the source resistance at the low-concen-
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`tration diffusion regions 34 is reduced. As a result,
`the
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`drivability of the device improves.
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`However, the gate-drain overlap LDDstructure has prob-
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`lems when they are applied to an MOStransistor having a
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`channel length of a half-micron or less as follows:
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`(1) Since the low-concentration diffusion regions 34 are
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`entirely located beneath the gate electrode 35, the effective
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`channel length L,, has a following relationship:
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`Ligh,-2Lijaa
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`wherein L, is the gate length and L,,, is the width of the
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`low-concentration diffusion regions 34 (measured in the
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`channel direction).
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`Page 11 of 22
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`Page 11 of 22
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`

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`
`3
`SUMMARY OF THE INVENTION
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`5,512,771
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`4
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`as to coverthe first conductivity type region; patterning the
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`conductive material film to form the gate electrode; depos-
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`The MOStype semiconductor device of this invention
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`iting a second insulating film and a third insulating film
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`comprises a semiconductor substrate includingafirst con-
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`which hardly transmits an oxidizing substance on the semi-
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`ductivity type region doped with first conductivity type
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`conductor substrate in this order so as to cover the gate
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`impurities and having a surface and an MOStransistor
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`electrode; etching the third insulating film and the second
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`formed in the first conductivity type region,
`the MOS
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`insulating film in this order by an anisotropic etching
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`transistor including: a second conductivity type source
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`technique, leaving part of the third insulating film and the
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`region formedin the first conductivity type region; a second
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`second insulating film unetched on the sides of the gate
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`conductivity type drain region formed in the first conduc-
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`electrode; removing the third insulating film selectively by
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`tivity type region and separated from the second conductiv-
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`a selective etching technique, thereby forming L-shaped side
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`ity type source region by a predetermined distance; a chan-
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`walls made of the secondinsulating film; implanting second
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`nel region formed in the first conductivity type region and
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`conductivity type impurity ions into the semiconductor
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`located between the second conductivity type source region
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`substrate using the gate electrode as a mask,thereby forming
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`and the second conductivity type drain region; a pair of
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`second conductivity type impurity diffusion regions; and
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`second conductivity type impurity diffusion regions formed
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`implanting second conductivity type impurity ions into the
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`on both sides of the channel region and having an impurity
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`semiconductorsubstrate using the gate electrode as a mask,
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`concentration lower than that of the second conductivity
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`thereby forming second conductivity type source and drain
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`type source region; a gate insulating film formed on the
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`regions with an impurity concentration higher than that of
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`surface of the semiconductor substrate, the gate insulating
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`the second conductivity type impurity diffusion regions,
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`film directly covering the channel region and the pair of
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`each having a first portion covered with the side wall and a
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`second conductivity type impurity diffusion regions; a gate
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`second portion not covered with the side wall,
`the first
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`electrode formed on the gate insulating film; and side walls
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`section being thinner than the second portion.
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`formed onthe sides of the gate electrode, wherein each of
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`Alternatively, there is provided a method for fabricating
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`the side walls has a bottom portion extending along the
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`an MOStype semiconductor device comprising a semicon-
`surface of the semiconductor substrate from eachside of the
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`ductor substrate including a first conductivity type region
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`gate electrode, and each of the second conductivity type
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`doped with first conductivity type impurities and having a
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`source and drain regions hasa first portion covered with the
`surface and an MOStransistor formed in the first conduc-
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`bottom portion of the side wall and a second portion not
`tivity type region, the method comprising steps of: depos-
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`covered with the bottom portion, the first portion being
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`iting a first insulating film to be used as a gate insulating film
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`thinner than the second portion.
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`and a conductive material film to be used as a gate electrode
`on the semiconductor substrate in this order so as to cover
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`Alternatively, the MOS type semiconductor device of the
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`invention comprises a semiconductor substrate
`present
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`the first conductivity type region; patterning the conductive
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`including a first conductivity type region doped with first
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`material film to form the gate electrode; depositing a second
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`conductivity type impurities and having a surface and an
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`insulating film and a third insulating film which hardly
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`MOStransistor formed in the first conductivity type region,
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`transmits an oxidizing substance on the semiconductor sub-
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`the MOStransistor including: a second conductivity type
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`Strate in this order so as to cover the gate electrode; etching
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`source region formedin the first conductivity type region; a
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`the third insulating film and the secondinsulating film in this
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`second conductivity type drain region formed in the first
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`order by an anisotropic etching technique, leaving part of the
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`conductivity type region and separated from the second
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`third insulating film and the second insulating film unetched
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`conductivity type source region by a predetermined dis-
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`on the sides of the gate electrode; removing the third
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`tance; a pair of second conductivity type impurity diffusion
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`insulating film selectively by a selective etching technique,
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`regions formed so as to cover the PN-junction between the
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`thereby forming L-shaped side walls made of the second
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`second conductivity type source region and the first con-
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`insulating film; implanting second conductivity type impu-
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`ductivity type region and the PN-junction between the
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`rity ions into the semiconductor substrate using the gate
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`second conductivity type drain region andthefirst conduc-
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`electrode and the side walls as a mask at an accelerating
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`tivity type region, and having an impurity concentration
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`energy at which the impurity ions are not
`transmitted
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`lower than that of the second conductivity type source
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`throughthe side walls, thereby forming second conductivity
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`region; a channel region formedin the first conductivity type
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`type source and drain regions in portions of the semicon-
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`region and located between the pair of the second conduc-
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`ductor substrate substantially not covered with the gate
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`tivity type impurity diffusion regions; a gate insulating film
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`electrode and the side walls; and implanting second con-
`formed on the surface of the semiconductor substrate and
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`ductivity type impurity ions into the semiconductor sub-
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`directly covering the channel region; a gate electrode formed
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`strate using the gate electrode as a mask at an accelerating
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`on the gate insulating film; and side walls formed on the
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`energy at which the impurity ions are not
`transmitted
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`sidesof the gate electrode, wherein each of the side walls has
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`throughthe side walls, thereby forming second conductivity
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`a bottom portion extending along the surface of the semi-
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`type impurity diffusion regions with an impurity concentra-
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`conductor substrate from each side of the gate electrode.
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`tion lower than and a thickness greater than those of the
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`second conductivity type source and drain regions.
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`According to another aspect of the present invention,
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`there is provided a method for fabricating an MOS type
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`According to yet another aspect of the present invention,
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`semiconductor device comprising a semiconductor substrate
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`the complementary MOS type semiconductor device com-
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`including a first conductivity type region doped with first
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`prises.a semiconductor substrate including an n-type region
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`conductivity type impurities and having a surface and an
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`doped with n-type impurities and a p-type region doped with
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`MOStransistor formed in thefirst conductivity type region,
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`p-type impurities and having a surface, an n-channel MOS
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`the method comprising steps of: depositing a first insulating
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`transistor formedin the p-type region, and a p-channel MOS
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`film to be used as a gate insulating film of the transistor and
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`transistor formed in the n-type region, the n-channel MOS
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`a conductive material film to be used as a gate electrode of
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`transistor including: an n-type source region formed in the
`the transistor on the semiconductorsubstrate in this order so
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`p-type region; an n-type drain region formed in the p-type
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`Page 12 of 22
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`region and separated from the n-type source region by a
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`regions;
`forming a resist covering the n-channel MOS
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`predetermined distance; a channel region formed in the
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`transistor on the p-type region; implanting p-type impurity
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`p-type region and located between the n-type source region
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`ions into the n-type region using the resist as a mask, thereby
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`and the n-type drain region; a pair of n-type impurity
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`forming p-type source and drain regions each havingafirst
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`diffusion regions formed on both sides of the channel region
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`portion covered with the side wall and a second portion not
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`and having an impurity concentration lowerthan that of the
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`covered with the side wall, the first section being thinner
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`n-type source region; a gate insulating film formed on the
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`than the second portion, and providing the n-type conduc-
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`surface of the semiconductor substrate, the gate insulating
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`tivity to the gate electrode of the p-channel MOStransistor;
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`film directly covering the channel region and the pair of
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`and implanting p-type impurity ions into the n-type region
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`n-type impurity diffusion regions, portions of the gate insu-
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`using the resist as a mask, thereby forming p-type impurity
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`lating film above the pair of n-type impurity diffusion
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`diffusion regions with an impurity concentration lower than
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`regions being thicker than a portion thereof above the
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`that of the p-type source and drain regions.
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`channel region; and a gate electrode formed on the gate
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`Thus, the invention described herein makes possible the
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`insulating film, the p-channel MOStransistor including: a
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`advantages of (1) providing an MOS type semiconductor
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`p-type source region formed in the n-type region; a p-type
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`device and a complementary MOS type semiconductor
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`drain region formedin the n-type region and separated from
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`device capable of operating at high speed, minimizing the
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`the p-type source region by a predetermined distance; a
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`short channel effects, and providing highreliability, and (2)
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`channel region formed in the n-type region and located
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`providing a method for fabricating such an MOS type
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`between the p-type source region and the p-type drain
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`semiconductor device and a complementary device.
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`region; a gate insulating film formed on the surface of the
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`These and other advantages of the present invention will
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`semiconductor substrate and having a uniform thickness;
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`become apparent to those skilled in the art upon reading and
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`and a gate electrode formed on the gate insulating film.
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`understanding the following detailed description with refer-
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`According to yet another aspect of the present invention,
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`ence to the accompanying figures.
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`there is provided a method for fabricating a complementary
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`MOStype semiconductor device comprising a semiconduc-
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`tor substrate including an n-type region doped with n-type
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`FIG. 1 is a sectional view ofa first example of the MOS
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`impurities and a p-type region doped with p-type impurities
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`type semiconductor device of the present invention.
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`and having a surface, an n-channel MOStransistor formed
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`FIG. 2 is a sectional view of a second example of the
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`in the p-type region, and a p-channel MOStransistor formed
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`MOStype semiconductor device of the present invention.
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`in the n-type region, the method comprising the stepsof:
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`FIG.3 is a sectional. view of a third example of the MOS
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`depositing a first
`insulating film to be used as a gate
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`type semiconductor device of the present invention.
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`insulating film of the transistor and a conductive material
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`FIG. 4 is a sectional view of a fourth example of the MOS
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`film to be used as a gate electrode of the transistor on the
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`semiconductor substrate in this order so as to cover the
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`type semiconductor device of the present invention.
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`p-type region and the n-type region; patterning the conduc-
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`FIGS. 5A to 5C are sectional views showing the steps for
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`tive material film to form the gate electrode; depositing a
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`lubricating the MOStype semiconductor device ofthe first
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`second insulating film and a third insulating film which
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`example of the present invention.
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`hardly transmits an oxidizing substance on the semiconduc-
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`FIGS. 6A to 6D are sectional views showing the steps for
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`tor substrate in this order so as to cover the gate electrode;
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`fabricating the MOS type semiconductor device of the
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`forming a resist covering the gate electrode of the p-channel
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`second example of the present invention.
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`MOStransistor on the n-type region; etching portionsof the
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`FIGS. 7A to 7D are sectional views showing the steps for
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`third insulating film and the second insulating film not
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`fabricating the MOS type semiconductor device of the third
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`covered with theresist in this order by an anisotropic etching
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`example of the present invention.
`technique, leaving part of the third insulating film and the
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`FIGS.8Ato 8D are sectional views showing the steps for
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`second insulating film unetched on the sides of the gate
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`fabricating the MOS type semiconductor device of the
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`e