`
`
`United States Patent ti
`
`Manukonda et al.
`
`
`
`
`
`CNOAATA
`US005102816A
`
`
`{11] Patent Number:
`
`
`
`
`
`
`
`[45] Date of Patent:
`
`
`5,102,816
`
`
`Apr. 7, 1992
`
`
`
`[75]
`
`
`Inventors:
`
`
`
`[54] STAIRCASE SIDEWALL SPACER FOR
`
`
`
`
`IMPROVED SOURCE/DRAIN
`
`
`ARCHITECTURE
`
`V. Reddy Manukonda; Thomas E.
`
`
`
`
`Seidel, both of Austin, Tex.
`
`
`
`
`
`Sematech, Inc., Austin, Tex.
`[73] Assignee:
`
`
`
`
`
`
`[21] Appl. No.: 679,160
`
`
`
`
`(22] Filed:
`Mar. 26, 1991
`
`
`
`
`
`
`
`
`
`
`[63]
`
`
`[56]
`
`
`6/1989 CHAO oeecccseetcssnssstssisenee 437/44
`4,837,180
`
`
`
`
`
`
`6/1989 Chiu etal.
`a 437/44
`4,843,023
`
`
`
`
`
`
`
`8/1989 Maet al.
`w. 437/44
`4,855,247
`
`
`
`
`
`
`
`
`4,873,557 10/1989 Kito ......
`ves 357/23
`
`
`
`
`
`4,998,150
`3/1991 Rodder et ale cscrussseseeeue 437/44
`
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`3/1986 European Pat. Off.
`.
`0173953
`
`
`
`
`
`6/1988 European Pat. Off.
`.
`0268941
`
`
`
`
`
`0057024 12/1981 Japan .
`
`
`
`
`0241267 11/1985 Japan wscssnsasesssnceneensuee, 156/643
`
`
`
`
`0160976
`7/1986 Japan .
`
`
`
`
`0118578
`5/1987 Japan .
`
`
`
`
`7/1987 Japan .
`0173763
`
`
`
`
`0046763
`2/1988 Japan......
`
`
`
`0132164
`5/1989 Japan .....
`
`
`
`8/1989 United Kingdom .
`2214349
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`Pfiester, ““LDD MOSFET’s Using Disposable Sidewall
`
`
`
`
`
`Spacer Technology”, IEEE Electron Device Letters,
`
`
`
`
`
`vol. 9, No. 4, Apr. 1988, pp. 189-192.
`
`
`
`
`
`
`
`
`
`ww 437/34
`
`
`sone 437/34
`
`
`
`
`
`
`
`
`
`
`
`
`Related U.S. Application Data
`
`
`
`
`Continuation of Ser. No. 499,783, Mar. 27, 1990, aban-
`
`
`
`
`
`
`
`
`doned.
`
`Int. CM oo. HOIL 21/336; HO1L 27/092
`[51]
`
`
`
`
`
`
`
`
`
`[52] US. Ch. caccccssscsssesssesssssssssscssersseeee 437/443 437/29;
`
`
`
`
`
`437/30; 437/34; 437/41; 437/56; 437/67;
`
`
`
`
`
`357/23.3
`
`[58] Field of Search 0.0... cece 437/27, 28, 29, 30,
`
`
`
`
`
`
`
`
`
`437/34, 40, 41, 44, 56, 57, 238, 241, 235;
`
`
`
`
`
`
`
`
`
`357/23.3; 156/643, 650, 651, 652, 653, 646
`
`
`
`
`
`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`Bower .
`3,472,712 10/1969
`
`
`
`.
`Kerwinet al.
`3,475,234 10/1969
`
`
`
`
`
`
`Bower .
`3,615,934 10/1971
`
`
`
`2/1978 De La Moneda -esecsessene 437/41
`4,072,545
`
`
`
`
`
`
`
`
`5/1980 Komeda etal... 437/44
`4,204,894
`
`
`
`
`
`
`
`4,356,040 10/1982 Fuetal. .
`
`
`
`
`
`
`5/1983 Tasch, Jr. et al. senescence 357/23
`4,384,301
`
`
`
`
`
`
`
`4,488,351 12/1984 Momose...
`. 437/34
`
`
`
`
`
`
`4,530,150
`7/1985 Shirato ..
`. 437/44
`
`
`
`
`
`
`4,642,878
`2/1987 Maeda ..
`. 437/34
`
`
`
`
`
`
`2/1988 Parrillo et al.
`. 437/44
`4,722,909
`
`
`
`
`
`
`
`
`3/1988 Wooet al.
`. 437/44
`4,728,617
`
`
`
`
`
`
`4,735,916 4/1988 Hommaetal. ..
`437/162
`
`
`
`
`
`
`
`
`4,740,484
`4/1988 Norstriim et ale
`ccescccseccscens 437/44
`
`
`
`
`
`
`
`
`5/1988 Huet al........
`156/643
`4,744,859
`
`
`
`
`
`
`
`5/1988 Parrillo etal.
`. 437/37
`4,745,086
`
`
`
`
`
`
`4,753,898
`6/1988 Parrillo etal.
`437/57
`
`
`
`
`
`
`
`
`7/1988 Mueller........
`4,760,033
`437/57
`
`
`
`
`
`4,764,477
`8/1988 Changet al.
`437/34
`.
`
`
`
`
`
`
`
`
`4,808,544 2/1989 Matsui ...
`437/44
`
`
`
`
`
`
`4,818,714 4/1989 Haskell .
`437/34
`
`
`
`
`
`4,818,715 4/1989 Chao........
`. 437/44
`
`
`
`
`
`
`4,826,782
`5/1989 Sachitanoet al. cccsce. 437/162
`
`
`
`
`
`
`okey
`
`
`
`(List continued on next page.)
`
`
`
`
`
`
`
`
`
`Primary Examiner—Olik Chaudhuri
`
`
`
`Assistant Examiner-—M, Wilczewski
`
`
`
`Attorney, Agent, or Firm—William W. Kidd
`
`
`
`
`
`[57]
`ABSTRACT
`
`
`Selective etching of a conformal nitride layer overlying
`
`
`
`
`
`
`
`a conformal oxide layer and a subsequentetching of the
`
`
`
`
`
`
`
`
`
`oxide layer provide for a staircase shaped sidewall
`
`
`
`
`
`
`
`
`spacer which is used to align source and drain regions
`
`
`
`
`
`
`
`
`
`
`during implantation. Extent of the implanted n—/n+
`
`
`
`
`
`
`
`and/or p-—/p+ regions within the substrate can be
`
`
`
`
`
`
`
`
`tightly controlled due to the tight dimensional toler-
`
`
`
`
`
`
`
`ances obtained by the footprint of the spacer. Further
`
`
`
`
`
`
`
`
`the source/drain profiles can be utilized with elevated
`
`
`
`
`
`
`
`‘polysilicon and elevated polysilicon having subsequent
`
`
`
`
`
`salicidation.
`
`
`
`
`
`
`14 Claims, 7 Drawing Sheets
`
`
`
`
`
`
`
`“
`
`©.
`
`a
`
`«@
`tt:
`
`fox
`
`$4:
`pales
`se
`
`Page 1 of 17
`
`TSMC Exhibit 1039
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 17
`
`TSMC Exhibit 1039
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`5,102,816
`
`
`
`Page 2
`
`
`
`
`
`
`
`
`
`
`CMOS Devices with Self-Aligned Shallow-Deep
`Junctions, pp. 487-489.
`
`
`
`
`
`
`
`
`
`
`
`
`IEEE, Feb. 1985, Matsumoto et al., An Optimized and
`
`
`
`
`
`
`
`Reliable LDD Structure for 1-um NMOSFET Based
`
`
`
`
`
`
`on Substrate Current Analysis, pp. 429-433.
`
`
`
`
`
`
`
`
`TEEE, Feb. 1986, Huang et al., A Novel Submicron
`LDDTransistor with Inverse-T Gate Structure IEDM
`
`
`
`
`
`
`86, pp. 742-745.
`
`
`
`IEEE, Oct. 1984, Oh and Kim, A New MOSFET
`
`
`
`
`
`
`
`
`
`Structure with Self-Aligned Polysilicon Source and
`
`
`
`
`
`
`
`
`
`
`Drain Electrodes, pp. 400-402.
`
`
`
`
`
`
`
`
`IEEE,Jul. 1989, Yamadaet al., Spread Source/Drain
`(SSD) MOSFET Using Selective Silicon Growth for
`
`
`
`
`
`
`
`
`
`
`
`64Mbit Drams pp. 2.4.1-2.4.4.
`
`
`
`
`OTHER PUBLICATIONS
`
`
`IBM Technical Disclosure Bulletin, vol. 32, No. SA,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Oct. 1989, “Method for Making Lightly Doped Drain
`
`
`
`
`Shallow Junctions”, pp. 110-111.
`IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun.
`
`
`
`
`
`
`
`
`
`1985, “New Scheme to Form Shallow N+ and P+
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Junctions for MOS Devices”, pp. 366-367.
`. 2244 Research Disclosure (1989) Jul., No. 303, New
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`York, U.S., “Method for Making Devices having Re-
`duced Field Gradients at Junction Edges”, p. 496.
`
`
`
`
`
`
`
`
`1988 Symposium on VLSI Technology, Ohetal., Si-
`
`
`
`
`
`
`
`
`multaneous Formation of Shallow-Deep Stepped Sour-
`
`
`
`
`
`ce/Drain for Sub-Micron CMOS, May10-13, 1988, pp.
`
`
`
`
`
`
`
`
`73-74.
`
`
`IEEE, Nov. 1989, Lu et al., Submicrometer Salicide
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 2 of 17
`
`Page 2 of 17
`
`

`

`U.S. Patent
`
`
`
`
`Apr. 7, 1992
`
`
`
`
`
`Sheet 1 of 7
`
`
`
`
`
`
`5,102,816
`
`
`
`op
`JO
`PRIOR AAT
`/7 /
`<—SOyASSeer4 2
`
`
`
`
`
`
`
`/§
`/4
`
`
`A4
`
`
`
`
`
`rN_N
`
`
`
`
`
`FOX
`
`
`
`
`
`fi
`
`
`
`
`
`
`
`
`
`
`
`PRIOR ART
`
`Pr?
`
`
`
`
`
`
`
`
`PRIOR ART
`22
`
`
`
`
`
`HESTON
`
`FOX
`
`Page 3 of 17
`
`Page 3 of 17
`
`

`

`U.S. Patent
`
`
`
`
`Apr. 7, 1992
`
`
`
`
`
`Sheet 2 of 7
`
`
`
`
`
`
`5,102,816
`
`
`
`
`
`
`ae
`Ss
`~
`CEE
`RRIANWa
`
`FeaReLeeead Bheehebd
`i
`EXAKAASS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`=
`
`
`
`
`
`
`
`
`
`Page 4 of 17
`
`Page 4 of 17
`
`

`

`U.S. Patent
`
`
`
`
`Apr. 7, 1992
`
`
`
`
`
`Sheet 3 of 7
`
`
`
`
`5,102,816
`
`
`
`
`
`60
`
`
`
`42
`
`
`
`63,/77
`
`:
`SSN JY
`42
`\NW NM
`2S
`v7Ne
`Css
`1, 63
`
`
`
`
`
`
`
`
`
`
`
`AA
`
`PaKNEE ig
`was
`
`TRS
`4
`
`
`
`42
`
`
`<q NNRNNY
`
`LANVNNASA
`
`42
`
`
`
`
`
`Page 5 of 17
`
`Page 5 of 17
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 6 of 17
`
`

`

`
`U.S. Patent
`
`
`
`
`
`Apr. 7, 1992
`
`
`
`
`
`
`Sheet 5 of 7
`
`
`
`5,102,816
`
`
`
`“O25
`
`Page 7 of 17
`
`Page 7 of 17
`
`
`

`

`Sheet 6 of 7
`
`
`
`
`
`
`5,102,816
`
`
`
`
`
`GF ég
`eeCDINAAA
`
`
`U.S. Patent
`
`
`
`
`
`Apr. 7, 1992
`
`
`
`Page 8 of 17
`
`Page 8 of 17
`
`
`
`

`

`
`U.S. Patent
`
`
`
`Apr. 7, 1992
`
`
`
`
`
`Sheet 7 of 7
`
`
`
`
`5,102,816
`
`
`
`
`VRBSER)/
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FOX
`
`65
`
`
`
`
`
`
`
`Page 9 of 17
`
`Page 9 of 17
`
`

`

`1
`
`
`
`5,102,816
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`_ w
`
`
`
`20
`
`
`
`STAIRCASE SIDEWALL SPACER FOR
`
`
`
`
`IMPROVED SOURCE/DRAIN ARCHITECTURE
`
`
`
`
`2
`SUMMARYOF THE INVENTION
`
`
`
`
`
`
`
`
`
`A “staircase” gate sidewall spacer is described in
`
`
`
`
`
`
`which tighter dimensional tolerances of the spacer pro-
`
`
`
`
`
`
`
`
`
`
`
`
`vides for a tighter control of source-drain spacing and
`
`
`
`
`
`
`
`This application is a continuation, of application Ser.
`source and drain doping profiles particularly as applied
`
`
`
`
`
`
`
`
`No. 499,783, filed Mar. 27, 1990, now abandoned.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to “double doped” source and drain regions. The side-
`
`BACKGROUNDOF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`wall spaceris utilized to align areas of a substrate for ion
`1. Field of the Invention
`
`
`
`
`
`
`
`
`implantation of the source and drain regions. The
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`source and drain regions can be either an n-channel
`
`
`
`
`
`
`
`
`
`The present invention relates to the field of MOS
`
`
`
`
`
`
`
`device or a p-channel device. By combining the n-chan-
`
`
`
`
`
`
`
`
`integrated circuits and, particularly to the process of
`
`
`
`
`
`
`nel and the p-channel, a CMOSdevice can be fabri-
`
`
`
`
`
`
`
`
`
`
`
`forming source and drain regions of a CMOSintegrated
`cated.
`circuit device.
`
`
`
`2. Prior Art
`
`
`
`
`
`
`
`
`
`After a gate is formed over a substrate, a conformal
`
`
`
`
`
`
`
`
`
`
`
`oxide layer and then a conformal nitride layer are
`
`
`
`
`
`
`
`
`In the design of integrated circuits various processes
`
`
`
`
`
`
`
`formed. Subsequent anisotropic etching leaves an oxide
`are knownforfabricating the actual device. Techniques
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`spacer adjacent to the gate sidewall, primarily due to
`
`have evolved over the years in which various layers are
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the selective etching of the overlying nitride layer.
`formed onto a silicon substrate, wherein these layers are
`
`
`
`
`
`
`
`After the removal of the remaining nitride by either
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`subjected to one or more of a variety of photolitho-
`
`
`
`
`
`
`
`isotropic or anisotropic etching, a staircase sidewall
`
`
`
`
`graphic, patterning, etching, exposing, implanting steps,
`
`
`
`
`
`
`
`
`oxide spacer remains. Subsequently, an n—(or p—)
`
`etc., in order to form the desired device One type of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`implant is performed, followed by an n+ or (p+) im-
`
`
`
`
`
`
`integrated circuit
`is a metal-oxide semiconductor
`
`
`
`
`
`
`
`
`plant to form the “double doped” source and drain
`
`
`
`
`
`
`
`(MOS)field-effect transistor (FET) in which source
`regions.
`
`and drain regions of the transistor are separated by a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Because the first implant is performed at a higher
`
`
`
`
`
`
`
`
`
`
`
`
`
`channel region underlying the gate of the transistor.
`
`
`
`
`
`
`
`energy level, ions penetrate the lower portion ofthe
`
`Where the transistor is formed on the substrate, source
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`stair case shaped spacer. The second implantis achieved
`
`
`
`
`
`
`
`
`and drain regions are formed in the substrate and the
`
`
`
`
`
`
`
`
`
`
`
`
`
`at a lower energy level than the first, so that the ions do
`
`
`
`
`
`
`
`
`
`
`gate region resides above the surface of the substrate.
`
`
`
`
`
`
`
`
`
`not readily penetrate the spacer. Thus, after annealing,
`
`
`
`
`
`
`
`
`
`Typically the source and drain regions are formed by
`
`
`
`
`
`
`
`
`
`in which ion damage is removed and the implants are
`
`
`
`
`
`
`
`
`
`
`
`doping the substrate in the area where these regionsare
`controllably diffused further into the substrate, a separa-
`
`
`
`
`
`
`
`
`
`
`
`
`to be formed. Ion implantation is one technique for
`
`
`
`
`
`
`
`
`
`
`
`
`
`tion region of n—(or p—) resides between the n+ or
`
`
`
`
`
`
`
`
`
`doping the source and drain. Using gate alignment, the
`
`
`
`
`
`
`(p++) region and the channel region. Further, because
`
`
`
`
`
`
`
`
`
`
`
`
`gate or the gate and an adjacent dielectric spacer are
`
`
`
`
`
`
`
`
`the “footprint” dimensions of the spacers can be tightly
`
`
`
`
`
`
`
`
`
`
`used to align the substrate area where the doping is to
`
`
`
`
`
`
`
`controlled during their formation, sharper definition of
`
`
`
`
`
`
`
`
`
`occur. A well known practice is to provide a first im-
`
`
`
`
`the location of the source and drain regionsis achieved.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plant to define a first implanted area and a second im-
`Furthermore, considerable process simplification is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plant to define a second implanted area. The second
`
`
`
`
`
`
`
`
`achieved by the process architecture of the present
`
`
`
`
`
`
`
`implanted area is the actual source or drain and thefirst
`
`
`
`
`
`
`
`invention. In particular, both n— and n+(or p— and
`
`
`
`
`
`
`
`
`
`
`
`
`implanted area provides a graded doping or lightly
`
`
`
`
`
`
`
`
`p+) implants can be performed in one ion implant ma-
`
`
`
`
`
`
`
`
`
`
`
`
`doped region between the source or the drain from the
`
`
`
`
`
`
`
`
`chine operation. Thus, reducing the process step count
`
`
`channel, in order to provide improved deviceintegrity,
`
`
`
`
`
`
`and allowsfor cost and yield-risk reduction in manufac-
`
`
`
`
`
`
`
`
`
`
`
`
`
`especially higher breakdown drain voltages.
`turing.
`
`
`
`
`
`
`
`Although these techniques are well-known, the vari-
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`
`
`
`
`
`
`
`ous specific processes are applicable for fabricating
`devices of a certain size. As device geometry shrinks,
`
`
`
`
`
`
`
`
`FIG.1 is a cross-sectional view showing a formation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`attempts are made to form more and moretransistors on
`
`
`
`
`
`
`
`
`
`
`
`of a gate and subsequent oxide layer to form a priorart
`MOSdevice.
`
`
`
`
`
`
`
`
`a given area of a semiconductor wafer. For example, a
`
`
`semiconductor device fabricated utilizing “submicron”
`
`
`
`
`FIG.2 is a cross-sectional view showing a formation
`
`
`
`
`
`
`
`
`
`
`
`
`
`technology will contain many morecircuit elements per
`
`
`
`
`
`
`of n—/n+ source and drain regions for the prior art
`
`
`
`
`device of FIG. 1.
`unit area than a device fabricated using “above-micron”
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG.3 is a cross-sectional view showing the unpre-
`
`technology. However, as device size continues to
`
`
`
`
`
`
`
`shrink, the dimensional tolerances required of the vari-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`dictability of the formation of source and drain regions
`
`
`ous formed layers and/or devices also shrink and be-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of the prior art device of FIG. 2, dueto variationsin the
`
`
`
`
`
`
`
`come morecritical. Thus tolerances adequate for form-
`
`
`
`
`
`
`
`
`
`slope of the sidewall oxide.
`
`
`
`
`FIG.4 is a cross-sectional view of the present inven-
`
`
`
`
`
`
`
`
`
`
`
`
`ing source and drain regions for a given size device,
`
`
`
`
`
`
`
`
`
`
`
`such as a device fabricated using 1.5 micron technol-
`
`
`
`
`
`
`
`tion showing a formation of a gate onasilicon substrate
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ogy, may be inadequate for improved devices, such as a
`and a subsequent formation of an oxide layer above the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`device fabricated using 0.35, 0.5 or even 0.8 micron
`
`gate and the substrate.
`FIG. 5 is a cross-sectional view of a formation of a
`
`
`technology.
`
`
`
`
`
`
`
`
`
`
`nitride layer over the oxide layer of FIG.4.
`
`
`
`
`
`
`
`
`
`
`
`invention provides for an improved
`The present
`
`
`
`
`
`
`FIG.6 is a cross-sectional view of a gate region of a
`
`
`
`
`
`
`
`
`
`
`
`method of forming source and drain regions in a semi-
`
`
`
`
`
`
`device of the present invention, in which sidewall spac-
`
`
`
`
`
`conductor device, wherein the sharper definition, such
`
`
`
`
`
`
`
`ers remain after etching the oxide and nitride layers of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`as tighter control of source-drain spacing and source
`FIG.5.
`
`
`
`
`
`
`
`
`and drain doping profiles, of these regions permit for
`
`
`
`FIG.7 is a cross-sectional view of the device of FIG.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the fabrication of devices using submicron technology.
`
`6 after removal of the nitride remnant on the sidewall
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Further, the improved method also provides for an ease
`spacers.
`
`
`of manufacture in fabricating the device.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`40
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 10 of 17
`
`Page 10 of 17
`
`

`

`3
`
`FIG. & is a cross-sectional view showing an n— im-
`
`
`
`
`
`
`
`
`
`plant to form n— source and drain regions to the device
`
`
`
`
`
`
`
`of FIG. 7.
`
`
`
`FIG.9 is a cross-sectional view showing an n+ im-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plant to form n+ source and drain regionsto the device
`
`
`
`
`of FIG. 8.
`:
`
`
`
`FIG. 10 is a cross-sectional view showing the source
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and drain regions of the device of FIG. 9 after anneal-
`
`
`
`
`ing, in which n—-/n+ regions diffuse further into the
`
`
`
`
`
`
`substrate.
`
`FIG.11 is a cross-sectional view showing the forma-
`
`
`
`
`
`
`
`
`
`
`
`
`tion of sidewall spacers to respective gates of both n-
`
`
`
`
`
`
`
`
`
`
`
`channel and p-channel areas of a CMOSdevice ofthe
`
`
`present invention.
`
`
`FIG. 12 is a cross-sectional view showing an n—-
`
`
`
`
`
`
`
`
`
`
`
`implant to form n— source and drain regions to the
`
`
`
`
`
`device of FIG, 11.
`
`
`
`
`FIG. 13 is a cross-sectional view showing an n+
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`implant to form n+ source and drain regions to the
`
`
`
`
`
`device of FIG, 12,
`
`
`
`
`FIG. 14 is a cross-sectional view showing a p— im-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plant to form p— source and drain regions to the device
`
`
`of FIG.13.
`
`
`
`FIG.15 is a cross-sectional view showing a p+ im-
`
`
`
`
`
`
`
`
`
`
`
`
`
`plant to form p+ source and drain regions to the device
`
`
`
`
`
`
`of FIG. 14.
`.
`
`
`
`FIG. 16 is a cross-sectional view showing the CMOS
`
`
`
`
`
`
`
`
`device of FIG. 15 after annealing.
`
`
`
`
`
`
`FIG. 17 is a cross-sectional view showing an alterna-
`
`
`
`
`
`
`
`
`tive embodiment in which an elevated polysilicon layer
`
`
`
`
`
`
`
`is formed above a substrate and adjacent to sidewall
`
`
`
`
`
`
`
`
`
`
`
`
`
`spacers ofthe present invention.
`FIG.18is a cross-sectional view showing a formation
`
`
`
`
`
`
`
`
`
`
`of n—/n+ source and drain regions underlying the
`
`
`
`
`
`
`
`
`
`
`elevated polysilicon of FIG. 17.
`FIG. 19 is a cross-sectional view showing a CMOS
`
`
`
`
`
`
`
`
`device of the alternative embodiment in which n—/n+
`
`
`
`
`
`
`
`
`
`
`
`
`
`and p—/p+ source and drain regions are formed un-
`
`
`
`
`derlying elevated polysilicon.
`,
`
`
`FIG. 20 is a cross-sectional view showing a CMOS
`
`
`
`
`
`
`
`
`device of another alternative embodiment in which an
`
`
`
`
`
`
`
`
`
`
`
`
`
`elevated polysilicon layer is formed above a substrate
`
`
`
`and adjacent to sidewall spacers, but having a thickness
`
`
`
`
`
`
`
`
`
`
`
`
`that elevates the polysilicon layer above the footof the
`
`
`
`
`
`
`
`
`spacer in order to implant a narrow region in the sub-
`
`
`
`
`strate.
`
`FIG. 21 is a cross-sectional view of the elevated
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`polysilicon device of FIG, 20, but having a subsequent
`salicidation layer.
`
`
`DETAILED DESCRIPTION OF THE PRESENT
`
`
`
`
`INVENTION
`
`
`A process for fabricating a semiconductor device
`
`
`
`
`
`
`
`
`
`
`
`
`using stepped spacer for improved formation of doped
`
`
`
`regions is described. A prior art techniqueis first de-
`
`
`
`
`
`
`
`
`
`scribed in order to provide a better understanding of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`advantages derived by the practice of the present inven-
`
`
`tion. In the following description, numerous specific
`
`
`
`
`details are set forth, such as specific thicknesses, tem-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`peratures, etc., in order to provide a thorough under-
`
`
`
`
`
`
`
`
`standing of the present invention. It will be obvious,
`
`however, to one skilled in the art that the present inven-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tion may be practiced without these specific details. In
`
`
`
`other instances, well-known processes have not been
`
`
`
`
`
`
`described in detail in order not to unnecessarily obscure
`
`
`
`
`
`
`
`
`the present invention.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,102,816
`
`
`
`4
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PRIOR ART
`
`
`
`
`
`
`
`Referring to FIG. 1, a prior art semiconductor device
`
`
`
`
`10 is shown. Device 10 is a metal-oxidc-semiconductor
`
`
`
`
`
`
`
`
`
`
`
`(MOS)device having a substrate 11, which substrate 11
`
`
`
`
`
`
`
`
`typically comprised of silicon. Circuit elements
`is
`
`
`
`
`formed on substrate 11 are typically separated by field-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`oxide regions, such as field-oxide regions 12 of FIG. 1.
`
`
`
`
`
`
`
`
`
`
`A gate 14 is then formed on substrate 11. Gate 14 is
`
`
`
`
`
`
`
`
`
`
`
`
`
`typically comprised of a polysilicon region 15 separated
`from the substrate 11 by a dielectric region 16, which
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`dielectric 16 is typically comprised of an oxide such as
`
`
`
`silicon oxide (Si02).
`
`
`
`
`
`
`
`
`
`
`
`Utilizing a self-aligned technique, the gate 14 is used
`
`
`
`
`
`to define a channel regionin the substrate 11 underlying
`
`
`
`
`
`
`
`the gate 14. A source and drain regionsare then subse-
`
`
`
`
`
`
`
`
`
`
`
`
`
`quently definedas the regions of the substrate bounding
`
`
`
`
`
`
`
`the channel region, such that the source and drain re-
`
`
`
`
`
`
`
`
`
`
`gions do not extend appreciably into the substrate 11
`
`
`
`
`
`
`
`
`
`
`
`underlying gate 14. Prior to forming the source and
`
`
`
`
`
`drain regions, an oxide layer 17 is deposited.
`
`
`
`
`
`
`
`By using well-known photoresist deposition, photo-
`
`
`
`
`
`lithographic and etching techniques, oxide layer 17 is
`
`
`
`
`
`
`
`
`
`
`etched to expose portions of substrate 11 for the pur-
`
`
`
`
`
`
`
`
`
`pose of forming the source and drain regions as shown
`
`
`
`in FIG. 2. The etching process is typically anisotropic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`such that a portion of oxide layer 17 remains adjacent to
`
`
`
`
`
`
`
`
`the vertical sides of gate 14. In someinstances, a portion
`
`
`
`
`
`
`
`of the oxide layer 17 also remains above gate 14. The
`
`
`
`
`
`
`
`
`
`
`
`
`portion of the oxide layer 17 remaining adjacent to gate
`
`
`
`
`
`
`14 is commonly referred to as a spacer, thus gate 14 is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`bounded by spacer regions 22, as shown in the cross-
`
`
`sectional illustration of FIG. 2.
`
`
`
`
`
`
`
`
`
`
`
`
`Next, a masking technique is used to expose only
`
`
`
`
`those areas which will be subjected to implantation. As
`
`
`
`
`
`
`
`
`
`
`shown in FIG. 2, a n— region 23 is formed due to an
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`n— implantation. Subsequently, a second masking step
`
`
`
`
`
`is utilized to define an area for performing the n+ im-
`
`
`
`
`
`
`
`
`
`
`
`
`
`plantation. The n+ region 24 resides within n— region
`
`
`
`23 and this demarcation is especially important in the
`
`
`
`
`
`
`
`
`
`
`
`region proximate to the channel region underlying the
`
`
`
`
`
`
`
`
`gate 14, An annealing step is used to anneal the source
`
`
`
`
`
`
`
`
`
`
`and drain, which annealing step extends the n— and n+
`
`
`
`
`
`
`
`
`
`regions further toward the channel region and in some
`
`
`
`
`
`
`
`
`
`instances, the n— region extends into the channel re-
`
`
`
`
`
`gion, but not extending appreciably into the channel
`
`
`
`
`
`
`
`
`
`
`
`
`region underlying the gate 14. One such priorart tech-
`
`
`
`
`
`
`
`
`
`nique to form n— and n+(“double doped”) source and
`
`
`
`
`
`drain regions is described in Matsumoto et al., “An
`
`
`
`
`
`
`
`
`
`Optimized and Reliable LDD Structure for 1-um
`
`
`NMOSFET Based on Substrate Current Analysis,
`
`
`
`
`
`
`IEEETransactions on Electron Devices, Vol. ED-32,
`
`
`
`
`
`
`
`
`
`
`
`
`
`No. 2, Feb. 1985, pp 429-433, in which a lightly doped
`
`
`
`
`drain (LDD)structureis discussed.
`
`
`
`
`
`
`
`
`
`
`
`
`
`The spacers 22, in conjunction with gate 14, function
`
`
`
`
`
`
`
`
`
`
`to align the substrate 11 for the implantation step. Spac-
`ers 22 are used to ensure that n— and n+ region 23 and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`24 profiles are distinct and that the n—, or both n—- and
`
`
`
`
`n-+ regions 23 and 24, do not extend appreciably into
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the channel region underlying the gate 14. Further,it is
`
`
`
`
`
`
`
`
`
`
`to be noted that two separate masks and masking steps
`
`
`
`
`
`
`
`
`are necessary to first implant the n— region 23 and a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`second step to implant the n+ region 24 in order to
`
`
`
`
`provide a separation of the n+ region from the channel
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`region for the purpose of providing better source and
`
`
`
`drain isolation from the channel region. In some in-
`
`
`
`
`
`
`
`
`
`
`
`stances the n+ region is doped first, followed by the
`
`
`
`
`
`
`
`
`
`
`doping of the n-region. An advantage of the n+ being
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`w5
`
`
`
`
`
`
`
`50
`
`
`
`
`
`60
`
`
`
`
`Page 11 of 17
`
`Page 11 of 17
`
`

`

`5,102,816
`
`
`
`
`
`
`
`
`
`
`
`
`—0
`
`
`
`
`
`
`
`
`
`
`
`
`
`35
`
`
`40
`
`
`
`45
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`—
`
`
`
`
`6
`
`
`
`
`
`
`
`
`crons, more notably the use of 0.8, 0.5 and 0.35 micron
`
`
`
`
`
`
`
`
`and smaller technologies. Furthermore,it is appreciated
`
`
`
`
`
`
`that
`techniques have been suggested for improving
`
`
`
`
`
`
`
`steps for submicron “double doped” source and drain.
`
`
`
`
`
`
`
`
`
`
`
`One such techniqueutilizing an inverse T-gate structure
`
`
`for submicron LD transistor is described in Huang et
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`al.,“A Novel Submicron LDD Transistor with Inverse
`
`
`
`
`
`
`T-Gate Structure”, IEEE IDEM,1986, pp 742-745.
`
`
`
`THE PREFERRED EMBODIMENT
`
`
`
`
`
`
`
`
`
`
`Referring to FIG.4, a semiconductor device 40 of the
`
`
`
`
`
`
`
`
`preferred embodiment is shown. Device 40 is a MOS
`
`
`
`
`
`
`
`device having a substrate 41 which is typically com-
`
`
`
`
`
`
`
`prised ofsilicon. Field oxide regions 42 are formed on
`
`
`
`
`
`the substrate 41 to localize the formation of circuit ele-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ments. Field oxide regions are shown in FIG.4 to iso-
`
`
`
`late an area of device 40 for the formation of a given
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`circuit element. A gate 44 is formed on substrate 41,
`
`
`
`
`
`
`
`which gate 41 is comprised of a polysilicon region 45
`
`
`
`
`
`
`
`
`
`separated from the substrate 41 by a dielectric region
`
`
`
`
`
`
`
`46. The dielectric region is typically comprised of an
`
`
`
`
`
`
`
`
`oxide, such as silicon dioxide (S$i02).
`
`
`
`
`
`
`
`
`
`
`After the formation of gate 44, an oxide layer 47 is
`
`
`
`
`
`
`
`
`deposited over the device 40. In the preferred embodi-
`
`
`
`
`
`
`
`
`
`
`
`ment, oxide layer 47 is comprised of a conformally
`
`
`
`
`
`
`
`
`coated silicon dioxide (SiO2) andis deposited by a well-
`
`
`
`
`
`
`knownsuitable chemical vapor deposition (CVD) pro-
`
`
`
`
`
`cess in order to obtain the conformal topology (confor-
`
`
`
`
`
`
`
`
`
`mal meaning that the deposited layer conforms to the
`
`
`
`
`
`
`
`
`
`underlying topology). Such deposition of SiO2 is well-
`
`
`
`
`
`
`
`
`
`
`knownin the prior art. CVD oxidelayer 47 is deposited
`
`
`
`
`
`
`
`
`to a thickness range of approximately 100-1,000 ang-
`
`
`
`
`
`
`
`stroms. SiO2 is preferred in that SiO2 provides for mini-
`
`
`
`
`
`mal and controllable interface charge states afforded by
`
`
`
`
`
`
`SiO2 on the underlying silicon.
`
`
`
`
`
`
`
`
`
`
`
`
`Referring to FIG. 5, a CVD conformalnitride layer
`
`
`
`
`
`
`48 is next deposited over the CVD oxide layer 47. Ni-
`
`
`
`
`
`
`
`
`
`
`
`tride layer 48 is deposited by CVD,such as by thermal
`
`
`
`
`
`
`
`
`
`
`
`
`
`-decomposition of silane SiH4 and ammonia NHéto a
`
`
`
`
`thickness of approximately 100-1,000 angstroms. Thus
`
`
`
`
`
`
`
`the nitride layer 48 of the preferred embodimentis com-
`
`
`
`
`
`
`
`
`
`prised ofsilicon nitride Si3N4, although any disposable
`
`
`
`
`material with good etch selectivity against SiO2 and Si
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`can be used. Polysilicon can be used butis less preferred
`
`
`
`
`
`
`becauseof its conductance should any residue remain in
`
`
`
`
`
`
`
`
`
`
`
`the subsequent steps below.
`
`
`
`
`
`Subsequently, both layers 47 and 48 areselectively
`
`
`
`
`
`
`
`
`
`
`
`
`etched to expose portions of the substrate 41 between
`
`
`
`
`
`
`
`
`
`the FOX regions 42 and gate 44. The exposed substrate
`
`
`areas will later form the source and drain regions about
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`gate 44. Nitride layer 48 is etched with high selectivity
`
`
`
`
`
`
`
`
`
`
`to SiO2 first and then SiO2layer 47is etched with high
`
`
`
`
`
`
`
`
`
`
`
`selectivity to both silicon and nitride. This technique
`
`
`
`
`
`
`
`allows for end-point detection and highly defined stair-
`
`
`
`
`case structure shown in FIG. 6. A dry anisotropic etch
`
`
`
`
`
`
`
`
`
`
`
`
`is used for both etch cycles.
`
`
`Because of the formation ofthenitride layer 48 above
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the oxide layer 47, several advantages are derived. The
`
`
`
`
`
`
`
`
`
`
`
`nitride etch provides for a more uniform etch cycle than
`
`
`
`
`
`
`
`
`the oxide etch, as well as having a better anisotropic
`
`
`
`
`
`
`
`
`
`
`properties. Additionally, because of the use of the ni-
`
`
`
`
`
`
`
`
`
`
`tride etch, the FOX regions 42 are not etched away
`
`
`which allows for controlled isolation (field inversion
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`voltage threshold). It is to be noted that in the prior art
`
`
`
`
`
`
`
`
`
`device 10 of FIG. 1, oxide etching of the oxide layer 17
`
`
`
`
`
`
`
`
`
`
`
`can cause portions of the FOX regions12 to be etched
`
`
`
`
`
`
`
`
`
`
`
`awayif the oxide layer 17 is not uniform in thickness.
`
`
`
`
`
`
`
`
`
`
`However, with device 40 of the present invention, ni-
`
`
`
`
`
`5
`
`
`
`
`
`performed first is that ion channeling effects can be
`
`
`
`reducedslightly.
`
`
`
`
`
`
`The width of the region underlying each of the side-
`
`
`
`
`
`
`
`
`
`
`wall spacers 22 is commonly termed a “footprint”. For
`
`
`
`
`
`
`
`
`
`
`device 10 of FIG. 2, a footprint for one ofthe sidewall
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`spacers 22 is shownbythe footprint distance 27.It is to
`
`
`
`
`
`
`
`
`
`be appreciated that the width of footprint 27is a critical
`
`
`
`
`
`
`
`
`
`
`measurement for determining the extent of the horizon-
`
`
`
`
`
`
`
`
`
`
`tal penetration of n— region 23 in the substrate. A loose
`
`
`
`
`
`
`
`
`
`
`tolerance of the width of footprint 27 will necessarily
`
`
`
`
`
`result in a wide disparity of the extent of the penetration
`
`
`
`
`
`
`
`of n— region 23 and, hence, will more than likely im-
`
`
`
`
`
`
`
`
`
`pact the extentof the penetration of n+ region 24. The
`
`
`
`
`
`
`
`
`recognition of this variance is a key factor to the under-
`
`
`
`
`
`
`
`
`
`
`
`
`
`standing the motivation behindthe practice of the pres-
`
`
`ent invention. Therefore, it is desirable to maintain a
`
`
`
`
`
`
`
`
`small variance about a mean value specified for the
`
`
`
`
`
`
`
`
`width of the footprint 27.
`
`
`
`
`
`
`As shown in FIG. 3, a variation in the slope of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`sidewall spacer 22 causes a corresponding difference in
`
`
`
`
`
`
`
`
`the width of the footprint 27 and this variation in the
`
`
`
`
`
`
`
`
`
`
`
`
`slope is illustrated by slope (shown as dotted lines) 30
`
`
`
`
`
`and 31. This difference in the width of the footprint 27
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`will cause n+ region 24 and/or n— region 23 to vary
`
`
`
`
`
`
`
`
`
`
`
`
`correspondingly (shown as doped regions 32 and 33)
`
`
`
`
`
`
`
`
`
`from the channel region underlying the gate 14. Any
`
`
`
`
`
`
`
`significant variation of the location of n+ region 24
`
`
`
`
`
`
`
`
`
`and/or n— region 23, will ultimately affect the operat-
`
`
`
`ing parameters of the device 10, such as threshold,
`
`
`
`
`
`
`
`
`
`
`punchthrough voltage, and source-drain leakage cur-
`
`
`
`
`
`
`rent. It is to be noted that in the example of FIG.3,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`doped region 33 can extend significantly toward or
`
`
`
`
`
`
`
`
`
`even into the channel region. When region 33 extends
`
`
`
`
`
`
`
`
`
`
`
`
`appreciably into the channel region, it can present an
`
`
`
`
`
`
`undesirable, or even fatal (in the case of extremely short
`
`
`
`
`
`
`
`
`channel devices), condition for the transistor.
`
`
`
`
`
`A variety of factors affect the dimensional width of
`
`
`
`
`
`
`
`
`
`
`
`the footprint 27. More notable factors are the gate 14
`
`
`
`
`
`
`
`
`
`
`
`
`
`profile, as well as its uniformity, slope of the sidewall
`
`
`
`
`
`
`
`spacer 22, depositon non-uniformity of oxide layer 17
`
`
`
`
`
`and etch non-uniformity of oxide layer 17 to form side-
`
`
`
`
`
`
`
`
`
`
`
`wall spacer 22, the non-uniformity being across the
`
`
`
`
`
`
`
`
`
`wafer. Additionally, in some instances where the slope
`
`
`
`
`
`
`
`
`
`of the sidewall spacer 22 varies, during subsequent
`
`
`
`
`
`
`metal formation steps, metal “stringers” can extend
`
`
`
`from the metal contacts at the source and/or drain
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`regions, along the sidewall 22 to a gate contact line
`
`
`
`
`
`
`
`
`
`
`residing on the upperportion ofthe gate 14. This condi-
`
`
`
`
`tion can cause an electrical short of the source and/or
`
`
`
`
`
`
`
`
`
`drain to the gate.
`:
`
`
`
`
`
`
`
`
`
`Finally it is to be noted that simila