`
`
`United States Patent ti
`
`Manukonda et al.
`
`
`
`
`
`CNOAATA
`US005102816A
`
`
`{11] Patent Number:
`
`
`
`
`
`
`
`[45] Date of Patent:
`
`
`5,102,816
`
`
`Apr. 7, 1992
`
`
`
`[75]
`
`
`Inventors:
`
`
`
`[54] STAIRCASE SIDEWALL SPACER FOR
`
`
`
`
`IMPROVED SOURCE/DRAIN
`
`
`ARCHITECTURE
`
`V. Reddy Manukonda; Thomas E.
`
`
`
`
`Seidel, both of Austin, Tex.
`
`
`
`
`
`Sematech, Inc., Austin, Tex.
`[73] Assignee:
`
`
`
`
`
`
`[21] Appl. No.: 679,160
`
`
`
`
`(22] Filed:
`Mar. 26, 1991
`
`
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`
`
`
`[63]
`
`
`[56]
`
`
`6/1989 CHAO oeecccseetcssnssstssisenee 437/44
`4,837,180
`
`
`
`
`
`
`6/1989 Chiu etal.
`a 437/44
`4,843,023
`
`
`
`
`
`
`
`8/1989 Maet al.
`w. 437/44
`4,855,247
`
`
`
`
`
`
`
`
`4,873,557 10/1989 Kito ......
`ves 357/23
`
`
`
`
`
`4,998,150
`3/1991 Rodder et ale cscrussseseeeue 437/44
`
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`3/1986 European Pat. Off.
`.
`0173953
`
`
`
`
`
`6/1988 European Pat. Off.
`.
`0268941
`
`
`
`
`
`0057024 12/1981 Japan .
`
`
`
`
`0241267 11/1985 Japan wscssnsasesssnceneensuee, 156/643
`
`
`
`
`0160976
`7/1986 Japan .
`
`
`
`
`0118578
`5/1987 Japan .
`
`
`
`
`7/1987 Japan .
`0173763
`
`
`
`
`0046763
`2/1988 Japan......
`
`
`
`0132164
`5/1989 Japan .....
`
`
`
`8/1989 United Kingdom .
`2214349
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`Pfiester, ““LDD MOSFET’s Using Disposable Sidewall
`
`
`
`
`
`Spacer Technology”, IEEE Electron Device Letters,
`
`
`
`
`
`vol. 9, No. 4, Apr. 1988, pp. 189-192.
`
`
`
`
`
`
`
`
`
`ww 437/34
`
`
`sone 437/34
`
`
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`
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`
`
`
`Related U.S. Application Data
`
`
`
`
`Continuation of Ser. No. 499,783, Mar. 27, 1990, aban-
`
`
`
`
`
`
`
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`doned.
`
`Int. CM oo. HOIL 21/336; HO1L 27/092
`[51]
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`[52] US. Ch. caccccssscsssesssesssssssssscssersseeee 437/443 437/29;
`
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`
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`437/30; 437/34; 437/41; 437/56; 437/67;
`
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`357/23.3
`
`[58] Field of Search 0.0... cece 437/27, 28, 29, 30,
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`437/34, 40, 41, 44, 56, 57, 238, 241, 235;
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`357/23.3; 156/643, 650, 651, 652, 653, 646
`
`
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`
`
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`
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`4,488,351 12/1984 Momose...
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`
`
`
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`7/1985 Shirato ..
`. 437/44
`
`
`
`
`
`
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`2/1987 Maeda ..
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`
`
`
`
`
`2/1988 Parrillo et al.
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`
`
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`
`
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`4/1988 Norstriim et ale
`ccescccseccscens 437/44
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`
`
`
`
`
`
`
`5/1988 Huet al........
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`
`
`
`
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`
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`
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`
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`6/1988 Parrillo etal.
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`
`
`
`
`
`
`
`
`7/1988 Mueller........
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`
`
`
`
`
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`8/1988 Changet al.
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`.
`
`
`
`
`
`
`
`
`4,808,544 2/1989 Matsui ...
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`
`
`
`
`
`
`4,818,714 4/1989 Haskell .
`437/34
`
`
`
`
`
`4,818,715 4/1989 Chao........
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`
`
`
`
`
`
`4,826,782
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`
`
`
`
`
`
`okey
`
`
`
`(List continued on next page.)
`
`
`
`
`
`
`
`
`
`Primary Examiner—Olik Chaudhuri
`
`
`
`Assistant Examiner-—M, Wilczewski
`
`
`
`Attorney, Agent, or Firm—William W. Kidd
`
`
`
`
`
`[57]
`ABSTRACT
`
`
`Selective etching of a conformal nitride layer overlying
`
`
`
`
`
`
`
`a conformal oxide layer and a subsequentetching of the
`
`
`
`
`
`
`
`
`
`oxide layer provide for a staircase shaped sidewall
`
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`
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`spacer which is used to align source and drain regions
`
`
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`
`
`during implantation. Extent of the implanted n—/n+
`
`
`
`
`
`
`
`and/or p-—/p+ regions within the substrate can be
`
`
`
`
`
`
`
`
`tightly controlled due to the tight dimensional toler-
`
`
`
`
`
`
`
`ances obtained by the footprint of the spacer. Further
`
`
`
`
`
`
`
`
`the source/drain profiles can be utilized with elevated
`
`
`
`
`
`
`
`‘polysilicon and elevated polysilicon having subsequent
`
`
`
`
`
`salicidation.
`
`
`
`
`
`
`14 Claims, 7 Drawing Sheets
`
`
`
`
`
`
`
`“
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`©.
`
`a
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`«@
`tt:
`
`fox
`
`$4:
`pales
`se
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`Page 1 of 17
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`TSMC Exhibit 1039
`TSMCv. IP Bridge
`IPR2016-01246
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`Page 1 of 17
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`TSMC Exhibit 1039
`TSMC v. IP Bridge
`IPR2016-01246
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`5,102,816
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`Page 2
`
`
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`CMOS Devices with Self-Aligned Shallow-Deep
`Junctions, pp. 487-489.
`
`
`
`
`
`
`
`
`
`
`
`
`IEEE, Feb. 1985, Matsumoto et al., An Optimized and
`
`
`
`
`
`
`
`Reliable LDD Structure for 1-um NMOSFET Based
`
`
`
`
`
`
`on Substrate Current Analysis, pp. 429-433.
`
`
`
`
`
`
`
`
`TEEE, Feb. 1986, Huang et al., A Novel Submicron
`LDDTransistor with Inverse-T Gate Structure IEDM
`
`
`
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`
`
`86, pp. 742-745.
`
`
`
`IEEE, Oct. 1984, Oh and Kim, A New MOSFET
`
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`
`
`Structure with Self-Aligned Polysilicon Source and
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`Drain Electrodes, pp. 400-402.
`
`
`
`
`
`
`
`
`IEEE,Jul. 1989, Yamadaet al., Spread Source/Drain
`(SSD) MOSFET Using Selective Silicon Growth for
`
`
`
`
`
`
`
`
`
`
`
`64Mbit Drams pp. 2.4.1-2.4.4.
`
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`
`
`OTHER PUBLICATIONS
`
`
`IBM Technical Disclosure Bulletin, vol. 32, No. SA,
`
`
`
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`
`
`
`
`
`
`
`
`
`Oct. 1989, “Method for Making Lightly Doped Drain
`
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`
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`Shallow Junctions”, pp. 110-111.
`IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun.
`
`
`
`
`
`
`
`
`
`1985, “New Scheme to Form Shallow N+ and P+
`
`
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`
`
`
`
`
`
`Junctions for MOS Devices”, pp. 366-367.
`. 2244 Research Disclosure (1989) Jul., No. 303, New
`
`
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`
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`
`
`
`
`
`
`
`
`York, U.S., “Method for Making Devices having Re-
`duced Field Gradients at Junction Edges”, p. 496.
`
`
`
`
`
`
`
`
`1988 Symposium on VLSI Technology, Ohetal., Si-
`
`
`
`
`
`
`
`
`multaneous Formation of Shallow-Deep Stepped Sour-
`
`
`
`
`
`ce/Drain for Sub-Micron CMOS, May10-13, 1988, pp.
`
`
`
`
`
`
`
`
`73-74.
`
`
`IEEE, Nov. 1989, Lu et al., Submicrometer Salicide
`
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`5,102,816
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`op
`JO
`PRIOR AAT
`/7 /
`<—SOyASSeer4 2
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`PRIOR ART
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`HESTON
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`FOX
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`VRBSER)/
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`STAIRCASE SIDEWALL SPACER FOR
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`IMPROVED SOURCE/DRAIN ARCHITECTURE
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`2
`SUMMARYOF THE INVENTION
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`A “staircase” gate sidewall spacer is described in
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`which tighter dimensional tolerances of the spacer pro-
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`vides for a tighter control of source-drain spacing and
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`This application is a continuation, of application Ser.
`source and drain doping profiles particularly as applied
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`No. 499,783, filed Mar. 27, 1990, now abandoned.
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`to “double doped” source and drain regions. The side-
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`BACKGROUNDOF THE INVENTION
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`wall spaceris utilized to align areas of a substrate for ion
`1. Field of the Invention
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`implantation of the source and drain regions. The
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`source and drain regions can be either an n-channel
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`The present invention relates to the field of MOS
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`device or a p-channel device. By combining the n-chan-
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`integrated circuits and, particularly to the process of
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`nel and the p-channel, a CMOSdevice can be fabri-
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`forming source and drain regions of a CMOSintegrated
`cated.
`circuit device.
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`2. Prior Art
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`After a gate is formed over a substrate, a conformal
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`oxide layer and then a conformal nitride layer are
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`In the design of integrated circuits various processes
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`formed. Subsequent anisotropic etching leaves an oxide
`are knownforfabricating the actual device. Techniques
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`spacer adjacent to the gate sidewall, primarily due to
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`have evolved over the years in which various layers are
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`the selective etching of the overlying nitride layer.
`formed onto a silicon substrate, wherein these layers are
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`After the removal of the remaining nitride by either
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`subjected to one or more of a variety of photolitho-
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`isotropic or anisotropic etching, a staircase sidewall
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`graphic, patterning, etching, exposing, implanting steps,
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`oxide spacer remains. Subsequently, an n—(or p—)
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`etc., in order to form the desired device One type of
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`implant is performed, followed by an n+ or (p+) im-
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`integrated circuit
`is a metal-oxide semiconductor
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`plant to form the “double doped” source and drain
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`(MOS)field-effect transistor (FET) in which source
`regions.
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`and drain regions of the transistor are separated by a
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`Because the first implant is performed at a higher
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`channel region underlying the gate of the transistor.
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`energy level, ions penetrate the lower portion ofthe
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`Where the transistor is formed on the substrate, source
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`stair case shaped spacer. The second implantis achieved
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`and drain regions are formed in the substrate and the
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`at a lower energy level than the first, so that the ions do
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`gate region resides above the surface of the substrate.
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`not readily penetrate the spacer. Thus, after annealing,
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`Typically the source and drain regions are formed by
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`in which ion damage is removed and the implants are
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`doping the substrate in the area where these regionsare
`controllably diffused further into the substrate, a separa-
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`to be formed. Ion implantation is one technique for
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`tion region of n—(or p—) resides between the n+ or
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`doping the source and drain. Using gate alignment, the
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`(p++) region and the channel region. Further, because
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`gate or the gate and an adjacent dielectric spacer are
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`the “footprint” dimensions of the spacers can be tightly
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`used to align the substrate area where the doping is to
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`controlled during their formation, sharper definition of
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`occur. A well known practice is to provide a first im-
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`plant to define a first implanted area and a second im-
`Furthermore, considerable process simplification is
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`plant to define a second implanted area. The second
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`implanted area is the actual source or drain and thefirst
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`invention. In particular, both n— and n+(or p— and
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`implanted area provides a graded doping or lightly
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`p+) implants can be performed in one ion implant ma-
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`doped region between the source or the drain from the
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`chine operation. Thus, reducing the process step count
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`and allowsfor cost and yield-risk reduction in manufac-
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`especially higher breakdown drain voltages.
`turing.
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`Although these techniques are well-known, the vari-
`BRIEF DESCRIPTION OF THE DRAWINGS
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`ous specific processes are applicable for fabricating
`devices of a certain size. As device geometry shrinks,
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`FIG.1 is a cross-sectional view showing a formation
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`attempts are made to form more and moretransistors on
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`of a gate and subsequent oxide layer to form a priorart
`MOSdevice.
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`a given area of a semiconductor wafer. For example, a
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`FIG.2 is a cross-sectional view showing a formation
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`technology will contain many morecircuit elements per
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`of n—/n+ source and drain regions for the prior art
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`device of FIG. 1.
`unit area than a device fabricated using “above-micron”
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`FIG.3 is a cross-sectional view showing the unpre-
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`dictability of the formation of source and drain regions
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`ous formed layers and/or devices also shrink and be-
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`of the prior art device of FIG. 2, dueto variationsin the
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`come morecritical. Thus tolerances adequate for form-
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`slope of the sidewall oxide.
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`FIG.4 is a cross-sectional view of the present inven-
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`ing source and drain regions for a given size device,
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`such as a device fabricated using 1.5 micron technol-
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`tion showing a formation of a gate onasilicon substrate
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`ogy, may be inadequate for improved devices, such as a
`and a subsequent formation of an oxide layer above the
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`device fabricated using 0.35, 0.5 or even 0.8 micron
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`gate and the substrate.
`FIG. 5 is a cross-sectional view of a formation of a
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`technology.
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`nitride layer over the oxide layer of FIG.4.
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`invention provides for an improved
`The present
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`FIG.6 is a cross-sectional view of a gate region of a
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`method of forming source and drain regions in a semi-
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`device of the present invention, in which sidewall spac-
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`conductor device, wherein the sharper definition, such
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`ers remain after etching the oxide and nitride layers of
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`as tighter control of source-drain spacing and source
`FIG.5.
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`and drain doping profiles, of these regions permit for
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`FIG.7 is a cross-sectional view of the device of FIG.
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`the fabrication of devices using submicron technology.
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`6 after removal of the nitride remnant on the sidewall
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`Further, the improved method also provides for an ease
`spacers.
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`of manufacture in fabricating the device.
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`Page 10 of 17
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`Page 10 of 17
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`3
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`FIG. & is a cross-sectional view showing an n— im-
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`plant to form n— source and drain regions to the device
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`of FIG. 7.
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`FIG.9 is a cross-sectional view showing an n+ im-
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`plant to form n+ source and drain regionsto the device
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`of FIG. 8.
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`FIG. 10 is a cross-sectional view showing the source
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`and drain regions of the device of FIG. 9 after anneal-
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`ing, in which n—-/n+ regions diffuse further into the
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`substrate.
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`FIG.11 is a cross-sectional view showing the forma-
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`tion of sidewall spacers to respective gates of both n-
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`channel and p-channel areas of a CMOSdevice ofthe
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`present invention.
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`FIG. 12 is a cross-sectional view showing an n—-
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`implant to form n— source and drain regions to the
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`device of FIG, 11.
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`FIG. 13 is a cross-sectional view showing an n+
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`implant to form n+ source and drain regions to the
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`device of FIG, 12,
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`FIG. 14 is a cross-sectional view showing a p— im-
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`plant to form p— source and drain regions to the device
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`of FIG.13.
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`FIG.15 is a cross-sectional view showing a p+ im-
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`plant to form p+ source and drain regions to the device
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`of FIG. 14.
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`FIG. 16 is a cross-sectional view showing the CMOS
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`device of FIG. 15 after annealing.
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`FIG. 17 is a cross-sectional view showing an alterna-
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`tive embodiment in which an elevated polysilicon layer
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`is formed above a substrate and adjacent to sidewall
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`spacers ofthe present invention.
`FIG.18is a cross-sectional view showing a formation
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`of n—/n+ source and drain regions underlying the
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`elevated polysilicon of FIG. 17.
`FIG. 19 is a cross-sectional view showing a CMOS
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`device of the alternative embodiment in which n—/n+
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`and p—/p+ source and drain regions are formed un-
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`derlying elevated polysilicon.
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`FIG. 20 is a cross-sectional view showing a CMOS
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`device of another alternative embodiment in which an
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`elevated polysilicon layer is formed above a substrate
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`and adjacent to sidewall spacers, but having a thickness
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`that elevates the polysilicon layer above the footof the
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`spacer in order to implant a narrow region in the sub-
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`strate.
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`FIG. 21 is a cross-sectional view of the elevated
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`polysilicon device of FIG, 20, but having a subsequent
`salicidation layer.
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`DETAILED DESCRIPTION OF THE PRESENT
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`INVENTION
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`A process for fabricating a semiconductor device
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`using stepped spacer for improved formation of doped
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`regions is described. A prior art techniqueis first de-
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`scribed in order to provide a better understanding of the
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`advantages derived by the practice of the present inven-
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`tion. In the following description, numerous specific
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`details are set forth, such as specific thicknesses, tem-
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`peratures, etc., in order to provide a thorough under-
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`standing of the present invention. It will be obvious,
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`however, to one skilled in the art that the present inven-
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`tion may be practiced without these specific details. In
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`other instances, well-known processes have not been
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`described in detail in order not to unnecessarily obscure
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`the present invention.
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`5,102,816
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`4
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`PRIOR ART
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`Referring to FIG. 1, a prior art semiconductor device
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`10 is shown. Device 10 is a metal-oxidc-semiconductor
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`(MOS)device having a substrate 11, which substrate 11
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`typically comprised of silicon. Circuit elements
`is
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`formed on substrate 11 are typically separated by field-
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`oxide regions, such as field-oxide regions 12 of FIG. 1.
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`A gate 14 is then formed on substrate 11. Gate 14 is
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`typically comprised of a polysilicon region 15 separated
`from the substrate 11 by a dielectric region 16, which
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`dielectric 16 is typically comprised of an oxide such as
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`silicon oxide (Si02).
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`Utilizing a self-aligned technique, the gate 14 is used
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`to define a channel regionin the substrate 11 underlying
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`the gate 14. A source and drain regionsare then subse-
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`quently definedas the regions of the substrate bounding
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`the channel region, such that the source and drain re-
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`gions do not extend appreciably into the substrate 11
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`underlying gate 14. Prior to forming the source and
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`drain regions, an oxide layer 17 is deposited.
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`By using well-known photoresist deposition, photo-
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`lithographic and etching techniques, oxide layer 17 is
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`etched to expose portions of substrate 11 for the pur-
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`pose of forming the source and drain regions as shown
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`in FIG. 2. The etching process is typically anisotropic
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`such that a portion of oxide layer 17 remains adjacent to
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`the vertical sides of gate 14. In someinstances, a portion
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`of the oxide layer 17 also remains above gate 14. The
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`portion of the oxide layer 17 remaining adjacent to gate
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`14 is commonly referred to as a spacer, thus gate 14 is
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`bounded by spacer regions 22, as shown in the cross-
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`sectional illustration of FIG. 2.
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`Next, a masking technique is used to expose only
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`those areas which will be subjected to implantation. As
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`shown in FIG. 2, a n— region 23 is formed due to an
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`n— implantation. Subsequently, a second masking step
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`is utilized to define an area for performing the n+ im-
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`plantation. The n+ region 24 resides within n— region
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`23 and this demarcation is especially important in the
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`region proximate to the channel region underlying the
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`gate 14, An annealing step is used to anneal the source
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`and drain, which annealing step extends the n— and n+
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`regions further toward the channel region and in some
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`instances, the n— region extends into the channel re-
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`gion, but not extending appreciably into the channel
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`region underlying the gate 14. One such priorart tech-
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`nique to form n— and n+(“double doped”) source and
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`drain regions is described in Matsumoto et al., “An
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`Optimized and Reliable LDD Structure for 1-um
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`NMOSFET Based on Substrate Current Analysis,
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`IEEETransactions on Electron Devices, Vol. ED-32,
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`No. 2, Feb. 1985, pp 429-433, in which a lightly doped
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`drain (LDD)structureis discussed.
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`The spacers 22, in conjunction with gate 14, function
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`to align the substrate 11 for the implantation step. Spac-
`ers 22 are used to ensure that n— and n+ region 23 and
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`24 profiles are distinct and that the n—, or both n—- and
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`n-+ regions 23 and 24, do not extend appreciably into
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`the channel region underlying the gate 14. Further,it is
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`to be noted that two separate masks and masking steps
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`are necessary to first implant the n— region 23 and a
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`second step to implant the n+ region 24 in order to
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`provide a separation of the n+ region from the channel
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`region for the purpose of providing better source and
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`drain isolation from the channel region. In some in-
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`stances the n+ region is doped first, followed by the
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`doping of the n-region. An advantage of the n+ being
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`w5
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`Page 11 of 17
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`Page 11 of 17
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`5,102,816
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`—0
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`35
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`—
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`6
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`crons, more notably the use of 0.8, 0.5 and 0.35 micron
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`and smaller technologies. Furthermore,it is appreciated
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`that
`techniques have been suggested for improving
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`steps for submicron “double doped” source and drain.
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`One such techniqueutilizing an inverse T-gate structure
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`for submicron LD transistor is described in Huang et
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`al.,“A Novel Submicron LDD Transistor with Inverse
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`T-Gate Structure”, IEEE IDEM,1986, pp 742-745.
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`THE PREFERRED EMBODIMENT
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`Referring to FIG.4, a semiconductor device 40 of the
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`preferred embodiment is shown. Device 40 is a MOS
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`device having a substrate 41 which is typically com-
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`prised ofsilicon. Field oxide regions 42 are formed on
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`the substrate 41 to localize the formation of circuit ele-
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`ments. Field oxide regions are shown in FIG.4 to iso-
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`late an area of device 40 for the formation of a given
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`circuit element. A gate 44 is formed on substrate 41,
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`which gate 41 is comprised of a polysilicon region 45
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`separated from the substrate 41 by a dielectric region
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`46. The dielectric region is typically comprised of an
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`oxide, such as silicon dioxide (S$i02).
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`After the formation of gate 44, an oxide layer 47 is
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`deposited over the device 40. In the preferred embodi-
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`ment, oxide layer 47 is comprised of a conformally
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`coated silicon dioxide (SiO2) andis deposited by a well-
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`knownsuitable chemical vapor deposition (CVD) pro-
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`cess in order to obtain the conformal topology (confor-
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`mal meaning that the deposited layer conforms to the
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`underlying topology). Such deposition of SiO2 is well-
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`knownin the prior art. CVD oxidelayer 47 is deposited
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`to a thickness range of approximately 100-1,000 ang-
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`stroms. SiO2 is preferred in that SiO2 provides for mini-
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`mal and controllable interface charge states afforded by
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`SiO2 on the underlying silicon.
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`Referring to FIG. 5, a CVD conformalnitride layer
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`48 is next deposited over the CVD oxide layer 47. Ni-
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`tride layer 48 is deposited by CVD,such as by thermal
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`-decomposition of silane SiH4 and ammonia NHéto a
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`thickness of approximately 100-1,000 angstroms. Thus
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`the nitride layer 48 of the preferred embodimentis com-
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`prised ofsilicon nitride Si3N4, although any disposable
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`material with good etch selectivity against SiO2 and Si
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`can be used. Polysilicon can be used butis less preferred
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`becauseof its conductance should any residue remain in
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`the subsequent steps below.
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`Subsequently, both layers 47 and 48 areselectively
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`etched to expose portions of the substrate 41 between
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`the FOX regions 42 and gate 44. The exposed substrate
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`areas will later form the source and drain regions about
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`gate 44. Nitride layer 48 is etched with high selectivity
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`to SiO2 first and then SiO2layer 47is etched with high
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`selectivity to both silicon and nitride. This technique
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`allows for end-point detection and highly defined stair-
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`case structure shown in FIG. 6. A dry anisotropic etch
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`is used for both etch cycles.
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`Because of the formation ofthenitride layer 48 above
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`the oxide layer 47, several advantages are derived. The
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`nitride etch provides for a more uniform etch cycle than
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`the oxide etch, as well as having a better anisotropic
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`properties. Additionally, because of the use of the ni-
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`tride etch, the FOX regions 42 are not etched away
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`which allows for controlled isolation (field inversion
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`voltage threshold). It is to be noted that in the prior art
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`device 10 of FIG. 1, oxide etching of the oxide layer 17
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`can cause portions of the FOX regions12 to be etched
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`awayif the oxide layer 17 is not uniform in thickness.
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`However, with device 40 of the present invention, ni-
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`5
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`performed first is that ion channeling effects can be
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`reducedslightly.
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`The width of the region underlying each of the side-
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`wall spacers 22 is commonly termed a “footprint”. For
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`device 10 of FIG. 2, a footprint for one ofthe sidewall
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`spacers 22 is shownbythe footprint distance 27.It is to
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`be appreciated that the width of footprint 27is a critical
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`measurement for determining the extent of the horizon-
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`tal penetration of n— region 23 in the substrate. A loose
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`tolerance of the width of footprint 27 will necessarily
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`result in a wide disparity of the extent of the penetration
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`of n— region 23 and, hence, will more than likely im-
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`pact the extentof the penetration of n+ region 24. The
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`recognition of this variance is a key factor to the under-
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`standing the motivation behindthe practice of the pres-
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`ent invention. Therefore, it is desirable to maintain a
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`small variance about a mean value specified for the
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`width of the footprint 27.
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`As shown in FIG. 3, a variation in the slope of the
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`sidewall spacer 22 causes a corresponding difference in
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`the width of the footprint 27 and this variation in the
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`slope is illustrated by slope (shown as dotted lines) 30
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`and 31. This difference in the width of the footprint 27
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`will cause n+ region 24 and/or n— region 23 to vary
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`correspondingly (shown as doped regions 32 and 33)
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`from the channel region underlying the gate 14. Any
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`significant variation of the location of n+ region 24
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`and/or n— region 23, will ultimately affect the operat-
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`ing parameters of the device 10, such as threshold,
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`punchthrough voltage, and source-drain leakage cur-
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`rent. It is to be noted that in the example of FIG.3,
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`doped region 33 can extend significantly toward or
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`even into the channel region. When region 33 extends
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`appreciably into the channel region, it can present an
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`undesirable, or even fatal (in the case of extremely short
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`channel devices), condition for the transistor.
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`A variety of factors affect the dimensional width of
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`the footprint 27. More notable factors are the gate 14
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`profile, as well as its uniformity, slope of the sidewall
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`spacer 22, depositon non-uniformity of oxide layer 17
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`and etch non-uniformity of oxide layer 17 to form side-
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`wall spacer 22, the non-uniformity being across the
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`wafer. Additionally, in some instances where the slope
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`of the sidewall spacer 22 varies, during subsequent
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`metal formation steps, metal “stringers” can extend
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`from the metal contacts at the source and/or drain
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`regions, along the sidewall 22 to a gate contact line
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`residing on the upperportion ofthe gate 14. This condi-
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`tion can cause an electrical short of the source and/or
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`drain to the gate.
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`Finally it is to be noted that simila