CERTIFICATE OF TRANSLATION
`
` I
`
` Roger P. Lewis, whose address is 42 Bird Street North,
`Martinsburg WV 25401, declare and state the following:
`
`I am well acquainted with the English and Japanese languages and
`have in the past translated numerous English/Japanese documents
`of legal and/or technical content.
`
`I hereby certify that the Japanese translation of the attached
`documents identified as:
`
`JP Hei 7 – 183518
`Semiconductor Device and the Production Method Thereof
`
`
`is true, and that all statements of information and belief are
`believed to be true, and that these and similar statements are
`punishable by fines or imprisonment, or both, under Section 1001
`of Title 18 of the United States Code.
`
`
`
`SINCERELY,
`
`
`
`ROGER P. LEWIS
`
`Date: October 20, 2016
`
`Page 1 of 48
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`TSMC Exhibit 1031
`TSMC v. IP Bridge
`IPR2016-01246
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`

`

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`(19) Japan Patent Office (JP) (11) [Unexamined] Patent Application Publication No.
`
`
`(12) Publication of Patent Application (A)
`Pat. Pub. Hei. 7 [1995] – 183518
`(Publication Date) 7th Year of Heisei (1995) 7th Month 21st Day [July 21, 1995]
`______________________________________________________________________
`(51) Int.Cl.6 Classification Symbol
`JPO File No. F1
`Basis for Classification
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`H01L 29/78
`
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`21/336
`301 T 8826-4M
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`21/28
`301 Y
`H01L 29/ 78
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`7514-4M
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`M
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`21/ 76
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`Examination Request: Not Requested No. of Claims: 15 FD (Total 17 Pages)
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`Pat. App. Hei. 6 [1994] - 303260
`
`6th Year of Heisei (1994) 11th Month 10th Day
`[November 10, 1994]
`
`Pat. App. Hei. 5 [1993] – 2842820
`Hei. 5 (1993)
`Japan (JP)
`
`Continued on Last Page
`______________________________________________________________________
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`(21) Application No.
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`(22) Application Date
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`(31) Priority Application No.
`(32) Priority Date
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`(33) Priority Country
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`(71) Applicant
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`(72) Inventor
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`(72) Inventor
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`(72) Inventor
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`000005821
`Matsushita Electric Industrial Co., Ltd.
`1006 Ōaza Kadoma, Kadoma-shi, Ōsaka-fu
`Tetsuya UEDA
`Matsushita Electric Industrial Co., Ltd.
`1006 Ōaza Kadoma, Kadoma-shi, Ōsaka-fu
`Takashi UEHARA
`Matsushita Electric Industrial Co., Ltd.
`1006 Ōaza Kadoma, Kadoma-shi, Ōsaka-fu
`Kōsaku Yano
`Matsushita Electric Industrial Co., Ltd.
`1006 Ōaza Kadoma, Kadoma-shi, Ōsaka-fu
`Benrishi Hiroshi MAEDA (and 2 others)
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`(74) Agent
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`______________________________________________________________________
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`[Translation of 1st page of source document continued on 2/2]
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`Page 2 of 48
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`

`

`[Translation of 1st page of source document continued from 1/2]
`
`(54)
`Title of the Invention
`
`
`
`
`
`
`
`
`(57) Abstract
`
`Semiconductor Device and the Production Method
`Thereof
`
`
`
`To provide a method for producing semiconductor devices that are easily
`Objective
`
`planarized whilst making an effort to achieve low resistance of the diffusion layer without
`causing reaction of the substrate silicon.
`
`
`
`A process for the formation of LOCOS film 2 for the purpose of dividing
`Composition
`
`the active region Rac into a plurality of regions in the vicinity of the surface of the
`semiconductor substrate, a process for the formation of gate electrode 4, which has a
`gate oxide film in the active region Rac, a process for the formation of side wall 5 on
`both sides of gate electrode 4, a process for the formation of impurity diffusion layer 6 in
`the active region Rac of both sides of gate electrode 4, [and] a process for the
`deposition of multi-layer metal film 7 over the entire surface of the substrate so that the
`entire surface of metal layer is polished by means of chemical machine polishing (CMP)
`and only metal film 7 remains on the impurity diffusion layer 6. When the CMP is
`completed, the polished surface is such that the surroundings of each of the metal
`layers 7 are encompassed by side wall 5 of both sides of gate electrode 4 and the
`LOCOS film, and each of the multi-layer metal films 7 are individually isolated.
`
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`Page 3 of 48
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`

`

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`
`
`[Legend for Figure in the lower left of the 1st source document page]
`
`(a) (
`) 5
` 
`4 (
`)
`
`

`(LOCOS
`) 2
`)
`3 (
` 
`(
`) 1
`
`(
`) 6
`
`(b) 7a (W/TiN/Ti
`(c) 7 (
`
`8 (
`)
`! "
`(d) (
`) 11
`#$ %
`10 (
`)
`(& 
`(e) (W
`) 12
`*')
`(f) 13 (
`1
`-
`
`
`(Side Wall) 5
`4 (Gate Electrode)
`(LOCOS Film) 2
`3 (Gate Oxide Film)
`(Silicon Substrate) 1
`(Impurity Diffusion Layer) 6
`(b) 7a (W/TiN/Ti Film)
`(c) 7 (Multi-Layer Metal Film)
`8 (Surface Region)
`(d) (Contact Hole) 11
`10 (Low Temperature Oxide Film)
`(e) (W Plug) 12
`(f) 13 (1st Metal Interconnect)
`
`
`
`)
`
`
`)
`
`+,.
`
`)
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`Page 4 of 48
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`

`

` (2 [1/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`
`
`Scope of Claims
`
`Claim 1
`A production method for semiconductors that include a plurality of MISFET
`
`
`and which is characterized by the fact that it is equipped with
`a process for the formation of an outer periphery separation portion of the active region
`of the semiconductor substrate at a location that is higher than the surface of the above
`described active region,
`a process for the introduction of threshold value control impurity of the above described
`MISFEET [sic],
`a process for the formation, within the above described active region, of the gate
`electrode and gate insulation film of the above described MISFET,
`a process for the formation of side walls, which are composed of insulation material, on
`both sides of the above described gate electrode,
`a process for the formation of the above described MISFET’s drain source, which
`becomes the 2 impurity diffusion layers,
`a process for the deposition of a metal film on the entire surface of the substrate after
`the formation of the above described gate electrode, side wall and outer periphery
`separation part, [and]
`a process by which a portion of the above described metal films, the outer periphery
`portion and the gate electrode are removed, and when the chemical machine polishing
`is completed, within the polished surface, the metal films on the above described
`impurity diffusion layer is surrounded by the above described gate electrode and outer
`periphery separation part so as to electrically isolate each [metal film].
`Claim 2
`A production method for semiconductors that described in Claim 1 and that
`
`
`is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that a LOCOS film is formed in the process for the formation of the above described
`outer periphery separation part, [and]
`in the process wherein the above described chemical machine polishing is performed,
`when the chemical machine polishing is completed, within the polished surface, each of
`the metal films on the above described impurity diffusion layer is surrounded by the
`above described side wall and LOCOS film.
`Claim 3
`A production method for semiconductors that is described in Claim 1 that is
`
`
`characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that in the process for the formation of the above described outer periphery
`separation part, after the formation on the semiconductor substrate of a groove that
`surrounds the above described active region a LOCOS film is formed in the process for
`the formation of the above described outer periphery separation part, [and]
`so that in the process for performing the chemical machine polishing, when the
`chemical machine polishing is completed, within the polished surface, each of the
`metals films on each of the above described impurity diffusion layers are surrounded by
`each of the above described side wall and the above described embedded oxide film.
`
`
`
`Page 5 of 48
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`

` (2 [2/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`
`
`A production method for semiconductors that is described in Claim 1 and
`Claim 4
`
`that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that a process for the formation of a LOCOS film in the surroundings of the above
`described active region is included,
`so that the process for the formation of the above described outer peripheral separation
`part includes the process for the formation of the gate interconnect surrounds the above
`described active region whilst also being positioned so that at least a portion in located
`on the above described LOCOS film and the process for the formation of the side walls
`that is made of insulation materials and is on the side portion of the above described
`gate interconnect,
`so that the process for the formation of the above described gate interconnect is
`performed at the same time as the process for the formation of above described gate
`electrode,
`so that the process for the formation of the side walls of the above described gate
`interconnect is performed at the same time as the process for the formation of the side
`walls of the above described gate electrodes, [and]
`so that in the process for performing the chemical machine polishing, when the
`chemical machine polishing is completed, within the polished surface, the metals films
`on the above described impurity diffusion layer is surrounded by the above described
`side wall and the above described embedded oxide film.
`Claim 5
`A production method for semiconductors that is described in Claim 4 and
`
`
`that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that when the above described chemical machine polishing is completed, the gate
`interconnect and the gate electrodes are connected.
`Claim 6
`A production method for semiconductors that is described in Claim 2 or 3
`
`
`and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that the process for the formation of the above described gate insulation film and
`gate electrode is one in which there is stepped insulation gate insulation film that is
`composed of a portion with a thickness with which the above described MISFET
`functions and a portion with a thickness with which the above described MISFET cannot
`function is formed.
`Claim 7
`A production method for semiconductors that is described in Claim 2 or 3
`
`
`and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that in the process for the introduction of the above described impurity diffusion layer
`the formation of the directly below the above described gate electrode so as to
`introduce impurities into a region so that the impurity concentration corresponds to the
`threshold value for the above described MISFET to function and into a region so as to
`have a high impurity concentration that corresponds to that at which the MISFET does
`not function.
`
`
`Page 6 of 48
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`

` (2 [3/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`
`
`A production method for semiconductors that is described in Claim 1. 2. 3
`Claim 8
`
`or 4 and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`it is further equipped with a process for the formation of local interconnect that connects
`metal films of both sides of the above described gate electrode and the above described
`gate electrode.
`Claim 9
`A production method for semiconductors that is described in Claims 1, 2, 3
`
`
`or 4 and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`by the use of polysilicon for the above described local interconnect.
`Claim 10
`A production method for semiconductors that is described in Claims 1, 2, 3
`
`
`or 4 and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that in the process for the formation of the above described gate electrode, the gate
`electrodes are of a polycide structure.
`Claim 11
`A production method for semiconductors that is described in Claims 1, 2, 3
`
`
`or 4 and that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that the process for the formation of the above described impurity diffusion is layer
`includes
`a process to be performed after the process by which the above described gate
`insulation film and gate electrode are formed, for the injection of low concentration of
`impurity ions into the semiconductor substrate of the above described active region with
`at least the above described gate electrode serving as the mask, and
`
`
`
`Page 7 of 48
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`

`

` (3 [1/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
` a
`
` process to be performed after the process by which the above described gate
`insulation film and gate electrode are formed, for the injection of high concentration of
`impurity ions into the semiconductor substrate of the above described active region with
`at least the above described gate electrode and side wall serving as the mask.
`Claim 12
`A production method for semiconductors that is described in Claim 1 and
`
`
`that is characterized by the fact that it is equipped, in the production method for
`semiconductors,
`so that in the process for the formation of the above described outer periphery
`separation part are formed a 1st active region for measurement that is sequential to the
`active region that forms the MIFFET [sic] of the test pattern and the portion within the
`active region in question for the gate electrode formation, a 2nd active region for
`measurement that is sequential to the portion that forms the drain within the above
`described active region, a 3rd active region for measurement that is sequential to the
`portion that forms the source of the above described active region, and a 4th active
`region for measurement that is isolated from each of the above described active regions,
`so that in the process for the formation of the above described gate insulation film and
`the gate electrode, an insulation film and electrode for gate are formed on the above
`described 1st active region for measurement in a manner such that they are connected
`to the gate electrode and gate insulation film of the MISFET of the test pattern,
`so that in the process for the formation of the side wall of the above described gate
`electrode, side walls are also formed on both side portions of the gate electrode of the
`test pattern,
`so that in the process of the formation of the above described impurity diffusion layer,
`drains and sources are formed on both side portions of the gate electrode of the
`MISFET of the test pattern whilst at the same time impurity ions are injected into the
`region that spans from the above described drain to the above described 2nd active
`region for measurement and the region that spans from the above described source to
`the above described 3rd active region for measurement,
`so that in the process for the formation of the above described metal film a metal film is
`also deposited on the entire surface of the test pattern,
`so that in the process for performing the above described chemical machine polishing,
`are retained on the region that spans from the test pattern’s above described active
`region drain to the above described 2nd region for measurement a metal film as an
`isolated electrode for drain purposes, on the region that spans from the source of the
`above described active region to the above described 3rd region for measurement a
`metal film as an isolated source for source purposes, and on the above described 4th
`region for measurement a metal film as an isolated electrode for the substrate,
`so that, when the above described chemical machine polishing is completed, it is
`additionally equipped with a process for the direct measurement of the characteristics of
`the MISFET via each of the electrodes and the above described impurity diffusion layer.
`Claim 13
`A semiconductor device wherein a plurality of MISFETs are mounted on
`
`
`the semiconductor substrate and which is characterized by the fact it is equipped with
`
` (3 [2/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`Page 8 of 48
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`

`

`
`an element separation that partitions into active regions the region in the vicinity of the
`surface of the above described semiconductor substrate,
`a gate insulation film and gate electrode that are formed in each of the above described
`active regions,
`a side wall which is made of insulation material and which is formed on both sides of the
`above described gate electrode,
`an impurity diffusion layer which functions as a source drain and which is formed in the
`active regions of both sides of the above described gate electrode,
`a gate interconnect which surrounds the active region and which is formed on the above
`described element separation,
`a side wall which is made of insulation material and which is formed on the side portion
`of the above described gate interconnect, [and]
`on the semiconductor substrate of the above described active region, 2 metal films that
`are isolated from the other regions on the top edge surface by the formation of the
`above described active region so as to be self-aligning vis-à-vis each of the side walls of
`the above described gate electrode and the side wall of the gate interconnect, and on
`the top edge surface of the above described gate electrode, the side wall thereof, the
`gate interconnect and the top edge surface of the side wall thereof are planarized.
`Claim 14
`A semiconductor device wherein a plurality of MISFETs are mounted on
`
`
`the semiconductor substrate and which is characterized by the fact it is equipped with
`an element separation that partitions into active regions the region in the vicinity of the
`surface of the above described semiconductor substrate,
`a gate electrode which h is formed in the above described active region,
`a stepped gate insulation film which is inserted between the above described gate
`electrode and the semiconductor substrate
`a portion of thickness for the above described MISFET to function and a portion of
`thickness for the above described MISFET to not function
`a side wall which is made of insulation material and which is formed on both sides of the
`above described gate electrode,
`an impurity diffusion layer which is formed in the active regions of both sides of the
`above described gate electrode,
`on the semiconductor substrate of the above described active region, 2 metal films that
`are isolated from the other regions on the top edge surface by the formation of the
`above described active region so as to be self-aligning vis-à-vis each of the side walls of
`the above described gate electrode and the element separation, and on the top edge
`surface of the gate electrode, the side wall thereof, the gate interconnect and the top
`edge surface of the side wall thereof are planarized.
`Claim 15
`A semiconductor device wherein a plurality of MISFETs are mounted on
`
`
`the semiconductor substrate and which is characterized by the fact it is equipped with
`an element separation that partitions into active regions the region in the vicinity of the
`surface of the above described semiconductor substrate,
`a gate insulation film and gate electrode that are formed on the semiconductor substrate
`of the above described active region,
`
` (3 [3/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`Page 9 of 48
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`

`

`
`the formation of the directly below the gate electrode in question so as to introduce
`impurities into a region so that the impurity concentration corresponds to the threshold
`value for the above described MISFET to function and into a region so as to have a high
`impurity concentration that corresponds to that at which the MISFET does not function
`a side wall which is made of insulation material and which is formed on both sides of the
`above described gate electrode,
`an impurity diffusion layer which is formed in the active regions of both sides of the
`above described gate electrode,
`on the semiconductor substrate of the above described active region, 2 metal films that
`are isolated from the other regions on the top edge surface by the formation of the
`above described active region so as to be self-aligned vis-à-vis each of the side walls of
`the above described gate electrode and element separation, on the top edge surface,
`Detailed Explanation of the Invention
`
`
`0001
`
`
`The present invention is one that relates to the
`Field of Industrial Application
`
`
`semiconductors that are mounted onto field-effect type transistor and the production
`method thereof, and in particular […]
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`Page 10 of 48
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` (4 [1/2]) Pat. Pub. Hei. 7 [1995] – 183518
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`[…] it is one that relates to the countermeasures for decreasing the resistance of the
`impurities diffusion layer of field-effect type transistors.
`0002
`In the recent years, the miniaturization of large-scale semiconductor integrated
`
`
`circuits has progressed, and there has been on-going miniaturization of MISFETs by
`means of lowering the gate interconnection and impurity diffusion layer resistance. As a
`method for lowering the impurity diffusion layer resistance, recently there has been the
`practical realization of the so-called [“]salicide[”] technology. An example of this is a
`method for reducing the resistance value of the impurity diffusion layer through the
`deposition of a high melting point metal such as Ti on the impurity diffusion layer in a
`silicon substrate, after which there is silicidization by means of the mutual diffusion of
`the Si and the Ti between the silicon substrate and the Ti film. Because the aspect ratio
`of the contact hole has been increased, in order to control as much as possible the
`contact area of the interconnect and the silicon, a method wherein W is embedded into
`the contact hole by means of selective CVD or the contact hole is embedded using
`blanket W has also been introduced.
`0003
`Furthermore, as a method wherein the above described 2 technologies have
`
`
`been combined, there is Martin S. Wang et al.’s 1991 IEEE. VLSI Symposium 5-5P41
`“A NOVEL DOUBLE-SELF-ALIGND [sic] TiSi2/T
`■0004■
`iN CONTACT WITH SELECTIVE CVD PLUG W FOR SUBMICRON DEVICE AND
`INTERCONNECT APPLICATIONS” has been proposed.
`0005
`The following is an explanation of the multiple salicide methods presented in
`
`
`the above described literature whilst referring to Figures 18(a) ~ (f). Figures 18(a) ~ (f)
`illustrate the changes in the cross sectional structure of the silicon substrate during the
`production process of a semiconductor device.
`0006
`Figure 18(a) shows the condition when a MOS transistor with an LDD
`
`
`structure has been formed. 1 is a silicon substrate, 2 is element separation using the
`LOCOS method, 3 is a gate oxide film, 4 is a polysilicon electrode, 5 is a side wall, [and]
`6 is an impurity diffusion layer (the impurity diffusion layer includes a low concentration
`source drain 6a and a high concentration source/drain 6b). Up to the stage that is
`shown in Figure 18(a), the method is the same as the conventional method for
`producing CMOS devices. Also, doping with As, P and B, and thermal processing are
`conducted in accordance with the n-channel MOS transistor [and] p-channel MOS
`transistor characteristics. Next, as is shown in Figure 18(b), the Ti thin film 30a for
`salicidization is deposited using sputtering, and as shown in Figure 18(c), after the
`annealing for purposes of the silicidization, the Ti on the oxide film is removed by wet
`etching, and the N2 injection is performed. Under this condition, the TiSix (silicidized
`titanium layer) 30 is formed only on the impurity diffusion layer 6 and the gate
`polysilicon 4. In the process that is shown in Figure 18(d), after the deposition of the
`BPSG film, the contact hole 11 is formed using photolithography and dry etching (([sic]
`CHF3+O2 based gas) at the desired position on the BPSG film 10. Next, as is shown in
`Figure 18(e), W plug 12 is deposited using the selective CVD method. Then, as is
`shown in Figure 18(f), after sputtered TiN/AlSiCu/Ti fim is deposited, the resulting film is
`patterned to form the metal interconnection 13. By means of the above process are […]
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` (4 [2/2]) Pat. Pub. Hei. 7 [1995] – 183518
`
`obtained a semiconductor device which has a MOS transistor with a salicide structure
`and a W plug that is formed by selective CVD.
`0007
`
`
`However, the conventional semiconductor
`Issues the Invention Seeks to Resolve
`
`
`device with the above described structure had the following problems:
`(1) In order to form the silicide film 30, it is necessary to have a reaction between the
`high melting point metal and the silicon substrate but if the depth of the impurity
`diffusion layer is shallow, the formation of a junction between the high melting point
`metal and the silicon becomes difficult. Thus, with future devices which require the
`formation of an impurity diffusion layer that is as shallow as possible, the formation of an
`effective junction becomes difficult, and thus salicide technology is not necessarily
`compatible with future devices.
`(2) The silicide layer has weak resistance to CF-based gases in the etching for the
`formation of the contact hole, and defects such as pin holes readily occur. Thus there is
`the danger of actually inviting an increase in the resistance of the impurity diffusion layer.
`(3) With transistors wherein the junction portion of the high melting point and the silicon
`is shallow, it is not possible to sufficiently over-etch as a means with which to be certain
`to form each contact hole. Thus, there is the danger of inviting deterioration of the
`interconnection reliability.
`(4) Thermal treatment at 650°C or higher temperature is required in order to lower the
`resistance of the silicide layer. Thus, there is the danger of inviting deterioration of the
`electrical characteristics of the transistor.
`(5) It is difficult for the silicide layer to serve as a sufficient barrier metal layer for
`purposes of forming the W plug by means of the selective CVD method so that the
`process margin in terms of junction leaks is scant.
`(6) Also, with the structure that is shown in Figure 18(f), the planarization of the
`substrate of the BPSG film 10 is poor.
`0008
`The present invention is one resulting from consideration given to these points,
`
`
`and its objective is to offer a semiconductor device structure and production method
`thereof wherein it is possible to obtain insulation and approximately complete
`planarization of the top edge surface, regardless of the thermal processing that
`becomes necessary in the course of the silicidization of the impurity diffusion layer of
`the silicon substrate whilst forming the high melting point on the impurity diffusion layer
`is a self-adjusting manner.
`0009
`
`
`
`The Measures for Resolving the Issues
`
`
`The measures of Claim 1 of this invention for achieving the above described objective
`are a process for the formation, as method for the production of a semiconductor device
`wherein is included a plurality of MISFETs, outer peripheral separation portion in the
`vicinity of the active region of the semiconductor substrate, up to a location that is
`higher than the surface of the above described active region,
`a process for the formation […]
`
` (5 [1/3]) Pat. Pub. Hei. 7 [1995] – 183518
`
`
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`Page 12 of 48
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`

`

`
`[…] of the gate electrode and gate insulation layer of the above described MISFET
`within the above described active region, a process for the formation on both sides of
`the above described gate electrode the side wall that is made of insulation material, a
`process for the formation within the above described active region 2 impurity diffusion
`layers consisting of the above described MISFET source drain, a process for the
`deposition, after the formation of the above described gate electrode, side wall and
`outer separation portion, of a metal film on the entire surface of the substrate,
`and a process wherein the above described metal film, the outer periphery separation
`portion and the gate electrode are removed by means of chemical machine polishing
`and after the chemical machine polishing is completed, within the polished surface the
`metal film on the above described impurity layer is surrounded by the above described
`gate electrode and the outer periphery separation portion so as to electrically isolate
`each [metal film]
`0010
`The measures of Claim 2 of the invention consist of a method wherein, with
`
`
`the production method for the semiconductors described in Claim 1, in the process for
`the formation of the above described outer periphery separation portion, the LOCOS
`film is formed, and in the process for performing the above described chemical machine
`polishing, when the chemical machine polishing is completed, each of the above
`described metal films within the polished surface are surrounded by the above side
`walls and the LOCOS film.
`0011
`The measures of Claim 3 of the invention consist of a method wherein, with
`
`
`the production method for the semiconductors described in Claim 1, in the process for
`the formation of the above described outer periphery separation portion, after the
`grooves that surround the above described active regions are formed on the
`semiconductor substrate, the grooves in question are filled and the embedded oxide
`films are formed, and in the process for performing the above described chemical
`machine polishing, when the chemical polishing is completed, the metal films on the
`each of the above described impurity diffusion layer is surrounded by the above
`described side walls and the above described embedded oxide film.
`0012
`The measures of Claim 4 of the invention consists of a method wherein the
`
`
`production method for a semiconductor device as described in Claim 1 there is
`designed a process for the formation of a LOCOS film in the vicinity of the above
`described active region, and in the process for the formation of the above described
`outer peripheral separation portion, there is a process for the formation of the gate
`interconnect that surrounds the above described active region and that at least one
`portion is located on the above described LOCOS film and a process for the formation
`of the side walls which are made of an insulation material and located on the side
`portion of the above described gate interconnection. And, the process for the formation
`of the above described gate interconnections is performed at the same time as the
`process for the formation of the above described gate electrodes, and the process for
`the formation of the side walls of the above described gate interconnections is
`performed at the same time as the process for the formation of the side walls of the
`above described gate electrodes, and the process for performing the above described
`
` (5 [2/3]) Pat. Pub. Hei. 7 [1995] – 183518
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`Page 13 of 48
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`chemical machine polishing is such that when the chemical machine polishing is
`completed, the metal film on the above described impurity diffusion layer within the
`polished surface is surrounded by the side wall of the above described gate electrode
`and the side wall of the above described gate interconnections.
`
`0013
`The measures of Claim 5 of the invention are a method for the production
`
`
`method of the semiconductor device that is described in Claim 4 in which the gate
`interconnection and the gate electrodes are connected at the point in time when the
`process of the above described chemical machine polishing is completed.
`0014
`The measures of Claim 6 of the invention are a method for the production
`
`
`method of the semiconductor device that is described in Claim 2 and/or 3 in which the
`method is one for the formation, in the process for the formation of the above described
`insulation film and the gate electrode, stepped gate insulation films composed of that
`which has a portion of a thickness for the above described MISFET to function and a
`portion of thi