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`ID
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`(11) Laid Open Patent Application
`(19) Japan Patent Office (JP)
`Publication
`(12) Laid Open Patent Publication (A)
`S59-181062
`Office Cont. No.
`
`(43) Publication October 15, 1984
`7377-5F
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`
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`8122-5F
`
`Number of invention 1
`
`
`Examination request No
`
`
`
`(total of 6 pages)
`Tokyo Shibaura Denki Corporation Research
`Institute
`(71) Applicant Toshiba Corporation
`72 Horikawa-cho, Saiwai-ku, Kawasaki-shi
`(74) Representative
`Takehiko Suzue, Patent Attorney, and two
`others
`
`(54) MOS semiconductor device production method
`
`(21) Patent Application No. S58-53537
`(22) Filing date March 31, 1983
`(72) Inventor Fumio Horiguchi
`1, Komukai-Toshiba-cho, Saiwai-ku,
`Kawasaki-shi
`
`
`
`
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`SPECIFICATION
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`1. Title of the invention
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`MOS semiconductor device production method
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`2. Claims
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`(1) An MOS semiconductor device production method, comprising a step of selectively
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`etching element separation regions of a semiconductor substrate to form grooves, a step of
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`doping the grooves with an impurity giving the same conductivity type as the substrate to
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`form an inversion prevention layer, a step of embedding a first insulating film in the
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`grooves and making the top surface of the insulating film higher than the surface of the
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`substrate, a step of selectively forming a gate electrode on an element formation region of
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`the substrate via a gate insulating film and making the step between the top surface of the
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`electrode and the substrate surface smaller than the step between the first insulating film
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`and the substrate surface, a step of forming a second insulating film on the sidewalls of the
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`steps by self-alignment, and a step of doping the substrate surface with an impurity giving
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`the conductivity type opposite to the substrate using the first and second insulating films as
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`a mask to form source/drain regions.
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`(2) The MOS semiconductor device production method according to Claim 1, wherein the
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`step of forming a second insulating film consists of depositing a second insulating film on
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`the entire surface and then overall etching the insulating film by reactive ion etching to
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`leave the insulating film only on the sidewalls of the steps.
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`TSMC Exhibit 1029
`TSMC v. IP Bridge
`IPR2016-01246
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`3. Detailed explanation of the invention
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`[Scope of the invention]
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`The present invention relates to an MOS semiconductor device production method and
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`particularly relates to a method of producing a MOS semiconductor device in which a
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`number of MOS transistors are highly integrated.
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`[Technological background and problems]
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`Recently, semiconductor devices such as ICs and LSIs have increasingly been improved
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`in integration and density. For example, MOS semiconductor memories are currently
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`mass-produced with the highest integration of 64 Kbit dynamic RAM and the progress to
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`higher integration of 256 Kbit dynamic RAM and even 1M bit dynamic RAM will be made
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`with no doubt.
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`As factors of hampering higher integration on a semiconductor device, issues arise in
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`microfabrication techniques. Particularly, the accuracy of stacking layers forming
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`transistors is a factor of diminishing increase in the number of elements per unit area on a
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`semiconductor substrate. Therefore, if the accuracy of stacking is determined with
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`absolute accuracy, in other words, if the positions of elements are determined without
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`taking into account stacking errors of the layers, higher integration can be achieved. In
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`that sense, the polysilicon gate channel length self-alignment technique is among typical
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`techniques currently practiced. This method comprises, as shown in a plane view of the
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`MOS transistor in Fig. 1 (a) and a cross-sectional view at the arrowed line L-L in Fig. 1 (b),
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`forming an oxide film in element separation regions by selective oxidization to insulate and
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`separate each element formation region, forming a polysilicon gate electrode on the
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`element formation region via a gate oxide film, and ion-injecting or diffusing from above
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`the polysilicon gate electrode an impurity giving the conductivity type opposite to the
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`substrate to form source/drain regions. Here, in the figures, the reference number 1
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`presents an Si substrate; 2, an element separation oxide film; 3, an inversion prevention
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`layer; 4, a gate oxide film; 5, a gate electrode; 6 and7, source/drain regions; 8, an interlayer
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`insulating film; and 9, a wiring Al film. In this method, no impurity is introduced under
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`the gate electrode 5 and this portion serves as a channel region, and self-aligned with the
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`gate electrode position, the source/drain are formed, whereby no positional shift with
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`respect to the gate electrode 5, source 6, and drain 7 occurs. Therefore, higher integration
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`is accordingly achieved.
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`However, the above kind of method has the following problem. In other words, in a
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`MOS transistor produced by the above method, the inversion prevention layer 3 formed by
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`doping of an impurity giving the same conductivity type as the substrate 1 under the
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`element separation oxide film 2 makes contact at portions A with the source/drain regions 6
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`and 7 formed by doping the element formation region with an impurity giving the
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`conductivity type opposite to the substrate 1. The impurity concentration is approximately
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`1x1017 [cm-3] in the inversion prevention layer 3 and approximately 5x1019 [cm-3] in the
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`source/drain 6 and 7; PN junctions of two high concentration impurities are created.
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`Therefore, the depletion layer at the portions A has a very small thickness of approximately
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`0.1 [µm]. On the other hand, the depletion layer at flat portions (portions C) shown in Fig.
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`(b) can be approximately 1 [µm] or larger in thickness by using a high resistance substrate.
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`Then, the junction capacitance is several times larger in value at the portions A than at the
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`flat portions C. This is a major factor of aggravating the circuit properties of various
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`kinds of semiconductor devices.
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`The above problem is discussed hereafter using an MOS dynamic memory by way of
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`example. Fig. 2 explains the structure of a currently-used conventional MOS dynamic
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`memory, showing the planar structure of a memory cell part of the folded bit line
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`arrangement using Al bit lines 21. Here, the reference number 22 presents word lines
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`serving as the gate electrode of the transfer gate; 23, a cell capacitor; and 24, a first-layer
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`polysilicon window forming an electrode of the cell capacitor 23. The charge stored in the
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`cell capacitor 23 is transferred to the bit line 21 via the transfer gate. In this regard, it is
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`desirable to increase the capacitance CS of the cell capacitor 23 relative to the stray
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`capacitance CB of the bit line 21 in order to increase the potential difference between the
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`bit line and enter large signals into the sense amplifier. The stray capacitance CB of the
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`bit line 21 is determined by the junction capacitance Ca of a drain part 25 of the transfer
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`gate, the capacitance Cb between the gate and drain, the capacitances between the other
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`gate and bit line and between the capacitor electrode and bit line, and the like. Among
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`these, the capacitances excluding Ca and Cb can be diminished by increasing the interlayer
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`insulating films. However, the capacitances Ca and Cb are determined by the processing
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`steps and are difficult to diminish in value. Therefore, assuming that the bit line
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`capacitance is determined by the capacitances Ca and Cb and CS is constant, the value
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`CS/CB defining the sensitivity of the sense amplifier is determined mostly by the values of
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`Ca and Cb. In other words, it is desirable to diminish the values of Ca and Cb as much as
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`possible in order to increase the sensitivity of the sense amplifier.
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`Here, the junction capacitance Ca of the drain part of the transfer gate is mostly
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`determined by the junction capacitance between the element separation region end and
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`drain as described above. Therefore, the sensitivity of the sense amplifier can be
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`improved by diminishing this junction capacitance. On the other hand, Cb is the
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`capacitance between the part of the source/drain region that laterally extends under the gate
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`and the gate in the regions B shown in Fig. 1 (a) and (b). It is also desirable to diminish
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`Cb. The cell part of an MOS dynamic memory is described above. The above-described
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`matters can apply to conventional integrated circuits. The source/drain stray quantity is
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`determined by the junction capacitance with the field end, and if this is reduced, the circuit
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`properties can significantly be improved.
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`However, as long as the current selection oxidization element separation technique and
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`gate polysilicon self-alignment technique are used, increase in the junction capacitance at
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`the field region ends is inevitable.
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`
`
` [Objective of the invention]
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`The objective of the present invention is to provide a MOS semiconductor device
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`production method making it possible to significantly reduce the junction capacitance
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`between the source/drain region and substrate at the element separation region ends of a
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`MOS transistor and concurrently reduce the capacitance between the source/drain region
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`and gate and thereby contributing to much smaller elements and their higher integration.
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`[Summary of the invention]
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`The present invention is summarized as follows. Using an element separation method of
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`embedding an insulating film such as a CVD-SiO2 film in the element separation regions
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`(the BOX method), a field insulating film is embedded to a level higher than the surface of
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`the substrate and the step between the element separation insulating film and the substrate
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`surface is made larger than the step between the gate electrode formed later and the
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`substrate surface, and an insulating film having a width proportional to the magnitudes of
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`the steps is formed on the sidewalls of the steps by self-alignment, which is followed by
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`doping of an impurity to form a source/drain so that the impurity layer makes contact with
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`the undersides of the gate electrode ends and makes no contact with the inversion
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`prevention layer.
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`In other words, the present invention provides a method of producing an MOS
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`semiconductor device, comprising the steps of selectively etching element separation
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`regions of a semiconductor substrate to form grooves, doping the grooves with an impurity
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`giving the same conductivity type as the substrate to form an inversion prevention layer,
`
`embedding a first insulating film in the grooves and making the top surface of the
`
`insulating film higher than the surface of the substrate, selectively forming a gate electrode
`
`on an element formation region of the substrate via a gate insulating film and making the
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`step between the top surface of the electrode and the substrate surface smaller than the step
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`between the first insulating film and the substrate surface, forming a second insulating film
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`on the sidewalls of the steps by self-alignment, and doping the substrate surface with an
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`impurity giving the conductivity type opposite to the substrate using the first and second
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`insulating films as a mask to form source/drain regions.
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`[Efficacy of the invention]
`
`The present invention uses an insulating film formed on the sidewalls of the steps of the
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`element separation insulating film and gate electrode as a mask in doping of an impurity to
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`form a source/drain, whereby it is possible to prevent contact between the source/drain and
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`inversion prevention layer and significantly reduce the junction capacitance between the
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`source/drain and substrate at the element separation region ends. Thus, the stray
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`capacitance of the circuit nodes connected to the source or drain is reduced, whereby
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`high-speed signal response is possible, and it is useful for significantly improving the
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`circuit operation speed. Moreover, it is also useful for improving the sensitivity of the
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`sense amplifier of a dynamic memory. Furthermore, if the sensitivity of the sense
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`amplifier is kept constant, the capacitance of the cell capacitor can also be reduced in
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`accordance with a reduction in the stray capacitance of the bit line. Thus, the same
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`integration level as in the prior art can be achieved in a smaller cell area, and the chip area
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`can be reduced. As the chip area is reduced, an increased number of chips can be obtained
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`from a single substrate and advantageously, the production cost per chip can be reduced.
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`Moreover, along with a reduction in the junction capacitance at the element separation
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`region ends, the effect of lateral infiltration of the source/drain region under the gate can be
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`eliminated, whereby the capacitance between the gate and source/drain via the gate oxide
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`film can also be reduced. In addition to advantageously increased circuit speed and
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`improved sensitivity of the sense amplifier as described above, other advantages, such as
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`so-called short channel effect with which the channel length effective due to lateral
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`infiltration of the impurity under the gate becomes smaller than the gate length, can be
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`suppressed.
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`Moreover, the positions of contacts to the source/drain are determined by the positions of
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`the gate electrode and element separation insulating film and by their steps, whereby there
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`is no need of photo engraving for forming contact holes. Therefore, since there is no need
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`for forming contacts in small areas within the source/drain regions in consideration of the
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`contact positions being shifted in those regions, the contact area can be increased, and even
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`the contact resistance can be lowered, whereby the circuit operation delay can be prevented.
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`Furthermore, the insulating film is larger in height in the element separation region than in
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`the element formation region, whereby it is possible to eliminate the reverse narrow
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`channel effect caused by the gate electric field concentrating at the channel element
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`separation region ends from the gate electrode on the element separation region (the effect
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`of lowering the threshold voltage VT as the channel width is reduced).
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`[Embodiment]
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`Fig. 3 (a) to (n) are cross-sectional views showing steps of producing an MOS transistor
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`according to an embodiment of the present invention. First, a P-type (100) Si substrate 31
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`having a specific resistance of 5 to 50 [Ω·cm] as shown in Fig. 3 (a) is prepared and an
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`element formation region on the substrate 31 is covered with a resist 32. Then, using
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`reactive ion etching utilizing a discharge gas including CF4, the substrate 31 is selectively
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`etched with the resist 32 as a mask as shown in Fig. 3 (b) to form grooves of 5000 to 10000
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`[Å] in depth in element separation regions (field regions). Subsequently, an impurity
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`giving the same conductivity type as the substrate 31 is introduced in the grooves of the
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`substrate 31 by ion injection to form a field inversion prevention layer 33. Then, after the
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`resist 32 is removed, a CVD-SiO2 film (first insulating film) 34 is deposited to a thickness
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`approximately equal to the depth of the grooves of the field regions as shown in Fig. 3 (c).
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`Subsequently, a resist 35 is applied on the entire surface, and the resist 35 is patterned so as
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`to leave the resist 35 only on the field regions as shown in Fig. 3 (d). Then, a resist 36 is
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`applied on the entire surface and fattened as shown Fig. 3 (e), which is followed by reactive
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`ion etching under conditions for etching the resists 35 and 36 and CVD-SiO2 film 34 at an
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`equal etching speed so as to expose the substrate surface in the element formation region as
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`shown in Fig. 3 (f). The steps up to here are the same as the known steps of embedding an
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`insulating film.
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`Then, the exposed surface of the substrate 31 is etched to make the element formation
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`region lower than the CVD-SiO2 film 34 in the field regions as shown in Fig. 3 (g).
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`Subsequently, the surface of the substrate 31 is thermally-oxidized to form a gate oxide film
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`(gate insulating film) 37 of approximately 100 to 400 [Å] as shown in Fig. 3 (h), and then a
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`polysilicon film 38 serving as the gate electrode and a CVD-SiO2 film 39 are
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`embedded/deposited over the entire surface in sequence as shown in Fig. 3 (i).
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`Subsequently, a resist 40 is formed on the gate electrode formation part as shown in Fig. 3
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`(j). The CVD-SiO2 film 39, polysilicon film 38, and gate oxide film 37 are selectively
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`etched in sequence by reactive ion etching using the resist 40 as a mask. Then, the resist
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`40 is removed and a CVD-SiO2 film (second insulating film) 41 is deposited on the entire
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`surface as shown in Fig. 3 (k). At this point, the CVD-SiO2 film 41 thickly adheres to the
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`sidewalls of the step between the CVD-SiO2 film 34 and substrate surface and the
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`sidewalls of the step between the gate electrode part and the substrate surface. Then, the
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`CVD-SiO2 film 41 is etched overall by reactive ion etching. In this case, the CVD-SiO2
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`film 41 on the sidewalls of the steps is thick and therefore the CVD-SiO2 film 41 remains
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`only on the sidewalls of the steps as shown in Fig. 3 (l). The width of the CVD-SiO2 film
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`41 remaining on the sidewalls of the steps can be adjusted by the magnitude of the steps.
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`In this state, the gate electrode 38 is insulated and contact holes between the source/drain
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`formation regions and metal wires are formed within those regions. Therefore, as an
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`impurity giving the conductivity type opposite to the substrate is ion-injected through the
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`holes, PN junctions between the source/drain and substrate are formed.
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`Then, an impurity giving the conductivity type opposite to the substrate 31 is ion-injected
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`into the substrate 31 using the insulating films 34, 39, and 41 as a mask to form
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`source/drain regions 42 and 43 as shown in Fig. 3 (m). At this point, the step between the
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`top surface of the gate electrode part (which is determined by the thicknesses of the gate
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`oxide film 37, gate electrode 38, and CVD-SiO2 film 39) and the substrate surface and the
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`thickness of the adhered CVD-SiO2 film 41 are properly selected so that the distance over
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`which the impurity injected into the source/drain formation regions laterally diffuses is
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`equal to the lateral width of the CVD-SiO2 film 41 remaining on the sidewalls of the gate
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`electrode part, whereby the length of the gate electrode 38 in the channel direction and the
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`effective channel length determined by the distance between the source/drain regions 42
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`and 43 can be made equal. As a result, the above-described Cb can be diminished.
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`Moreover, contact between the source/drain regions 42 and 43 and the inversion prevention
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`layer 33 due to diffusion of the impurity can be prevented by making the lateral width of
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`the CVD-SiO2 film 41 remaining on the sidewalls of the CVD-SiO2 film 34 in the field
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`regions sufficiently larger than the lateral width of the CVD-SiO2 film 41 remaining on the
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`sidewalls of the gate electrode part. To do so, it is sufficient that the step between the top
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`surface of the CVD-SiO2 film 34 and the substrate surface is larger than the step between
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`the top surface of the gate electrode part and the substrate surface. In this way, the
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`depletion layer from the source/drain regions 42 and 43 are sufficiently thick and the
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`junction capacitance Ca at the field ends can significantly be reduced.
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`Thereafter, a wiring Al film 44 is deposited and patterned as shown in Fig. 3 (n), whereby
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`the Al film 44 makes contact with the source/drain regions 42 and 43 via contact holes
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`formed in the source/drain regions 42 and 43. As a result, the contact with the field and
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`gate can be made by self-alignment without the need of a mask for forming contacts.
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`As described above, the method of this embodiment can prevent contact between the
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`source/drain regions 42 and 43 and the inversion prevention layer 33 and prevent lateral
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`extension of the source/drain regions 42 and 43 under the gate electrode 38. Thus, it is
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`possible to significantly reduce the junction capacitances Ca and Cb and obtain the
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`above-described efficacy.
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`The present invention is not confined to the above-described embodiment. For example,
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`the above-described first and second insulating films are not limited to CVD-SiO2 films
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`and can be Si3N4 or other insulating films. Furthermore, the above-described gate
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`electrode is not limited to those of polysilicon and can be of silicide, high melting point
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`metal, or the like. Moreover, the step between the first insulating film and the substrate
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`surface and the step between the gate electrode and substrate surface can be modified as
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`appropriate according to the specification. Furthermore, the second insulating film can be
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`modified in adhered film thickness and formation method as appropriate. Moreover, the
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`substrate is not limited to those of the P-type Si and can be an N-type Si substrate or other
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`semiconductor substrate with no problems. The present invention can be implemented
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`with various other modifications to the extent not departing from the gist of the present
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`invention.
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`4. Brief explanation of the drawings
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`Fig. 1 (a) is a plane view showing a prior art MOS transistor structure. Fig. 1 (b) is a
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`cross-sectional view at the arrowed line L-L in Fig. 1 (a). Fig. 2 is a plane view showing
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`the structure of an MOS dynamic memory of the folded bit line arrangement of Al bit lines
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`currently in use. Fig. 3 (a) to (n) are stepwise cross-sectional views for explaining an
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`embodiment of the present invention.
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`31 … Si substrate (semiconductor substrate), 33… inversion prevention layer, 34 …
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`element separation CVD-SiO2 film (first insulating film), 37 … gate oxide film (gate
`
`insulating film), 38 … polysilicon gate electrode, 39 … CVD-SiO2 film (second insulating
`
`film), 42 and 43 … source/drain region, 44 … wiring Al film.
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`
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`Representative for Applicant: Takehiko Suzue, Patent Attorney
`
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`CERTIFICATE OF TRANSLATION
`
` I
`
` Roger P. Lewis, whose address is 42 Bird Street North,
`Martinsburg WV 25401, declare and state the following:
`
` I
`
` am well acquainted with the English and Japanese languages
`and have in the past translated numerous English/Japanese
`documents of legal and/or technical content.
`
` I
`
` hereby certify that the Japanese translation of the
`attached document identified as:
`
`
`JP S59-181062
`
`is true, and that all statements of information and belief
`are believed to be true, and that these and similar
`statements are punishable by fines or imprisonment, or both,
`under Section 1001 of Title 18 of the United States Code.
`
`
`SINCERELY,
`
`
`
`ROGER P. LEWIS
`
`
`
`Date: September 12, 2016
`
`
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