`
`
`
`(21) International Application Number: PCT/US88/03841|Published
`With internationalsearch report.
`
`WORLD INTELLECTUAL PROPERTY ORGANIZATION
`PCT
`International Bureau
`INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`(51) International Patent Classification 4 :
`(11) International Publication Number:
`WO 90/05377
`HO1L 21/265, 29/96
`(43) International Publication Date:
`17 May 1990 (17.05.90)
`
`
`
`
`
`(22) International Filing Date:
`
`31 October 1988 (31.10.88)
`
`(71) Applicant (for all designated States except US): MICRON
`TECHNOLOGY, INC. [US/US]; 2805 East Columbia
`Road, Boise, ID 83706 (US).
`
`(72) Inventor; and
`(75) Inventor/Applicant(for US only) : LOWREY,Tyler, A. [US/
`US]; 8536 Brookside Lane, Boise, ID 83703 (US).
`
`(74) Agent: PROTIGAL,Stanley, N.; Micron Technology, Inc.,
`2805 East Columbia Rd., Boise, ID 83706 (US).
`
`(81) Designated States: AT, AU, BB, BE (European patent),
`BG, BR, CH, DE, DK, FI, FR (European patent), GB,
`HU,IT (European patent), JP, KR, LK, LU, MC, MG,
`MW,NL, NO, RO, SD, SE, SU, US.
`
`(54) Title: LOCAL ENCROACHMENT REDUCTION
`Periphery
`
`(57) Abstract
`
`Local Encroachment Reduction (LER)is described, in which a fraction offield oxideis selectively etched. A high energy
`boron implant is used to maintain adequate active area isolation after the removal. This implant also doubles as an LER high
`capacitance and provides a carrier to minority substrate electrons. After the high energy boron implant, an N-type bottom plate
`capacitor
`is
`implanted. At that
`point, the wafer is completed by
`existing techniques.
`.
`ae
`pacitor is
`imp
`P
`P
`y
`5
`q
`IP Bridge Exhibit 2031
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 24
`
`Page 1 of 24
`
`IP Bridge Exhibit 2031
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`Codes used to identify States party to the PCT on the front pages of pamphlets publishing international
`applications under the PCT..
`
`United States of America a
`BASeYROESzSEER Madagascar
`
`AT
`
`Central African Republic
`Congo
`Switzerland
`Cameroon
`Germany, Federal Republic af
`Denmark
`.
`
`Mali
`Mauritania
`Malawi
`Netherlands
`Norway
`Romania
`Sudan
`Sweden
`Senegal
`Soviet Union
`Chad
`Togo
`
`FOR THE PURPOSES OF INFORMATION ONLY
`
`United Kingdom
`Hungary
`Italy
`—
`Japan
`Democratic People’s Republic
`of Korea
`Republic of Korea
`Liechtenstein
`Sri Lanka
`Luxembourg
`Manaco
`
`Page 2 of 24
`
`ES
`FI
`FR
`GA
`GB
`HU
`IT
`JP
`KP
`
`KR
`
`uL
`
`K
`us
`MC
`
`Page 2 of 24
`
`

`

`WO90/05377
`
`PCT/US88/03841
`
`-|-
`LOCAL ENCROACHMENT REDUCTION
`
`Field of the Invention
`
`=
`
`This
`
`invention
`
`relates
`
`to fabrication of
`
`semiconductor circuit devices and more particularly to
`
`reducing encroachment of field oxide
`for
`techniques
`area of
`a semiconductor array during the
`into active
`field oxide.
`growth of
`The invention has particular
`utility in memory arrays such as dynamic random access
`
`memories (DRAMs).
`
`Background of the Invention
`
`10
`
`This
`
`invention relates
`
`to the manufacture of
`
`semiconductor circuit devices. More specifically the
`
`invention
`
`relates
`
`to manufacture
`
`of multilayer
`
`semiconductor circuit devices
`
`in which photomasking
`
`steps are used in the manufacture.
`
`15
`
`The invention uses various materials which are
`
`electrically
`
`either
`
`conductive,
`
`insulating
`
`or
`
`semiconducting,
`
`although the completed semiconductor
`
`circuit device itself
`
`is usually referred to asa
`
`"semiconductor".
`
`One of
`
`the materials
`
`used
`
`is
`
`20
`
`silicon, which
`
`appears
`
`as either
`
`single crystal
`
`silicon
`or
`as polycrystalline
`referred to as polysilicon
`or
`
`silicon material,
`"poly"
`in this
`
`disclosure.
`
`This
`invention
`describes
`a
`technique
`to
`maximize cell capacitor area
`in a high density/high
`
`25
`
`volume DRAM (dynamic random access memory) fabrication
`process.
`It is called "local encroachment reduction"
`
`Page 3 of 24
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`

`

`WO 90/05377
`
`PCT/US88/03841
`
`a
`
`or "LER"
`
`for short.
`
`The
`
`invention is applicable to
`
`all high density DRAM planar processes
`
`from the
`
`16Kbit to the 4Megbit generations and beyond.
`
`known
`for high density DRAM
`It
`is well
`that maximum cell
`process/cell design,
`capacitor
`
`active area must be obtained as a_percentage of
`repeating geometry area in a DRAM array. This active
`region/repeating region ratio determines the overall
`die size for a given feature size capability. This
`then translates directly into cost per bit.
`The
`active capacitor
`region must
`be
`large enough
`to
`insure proper
`sensing of data by the bitline sense
`amps and to insure strong immunity
`to single event
`upsets such as alpha particles.
`
`10°
`
`15
`
`20
`
`25
`
`30
`
`One
`
`key
`
`factor
`
`in maximizing cell capacitor
`
`active area is in reducing field oxide encroachment
`
`into active area during field oxidation. Encroachment
`
`can case
`
`a loss of active width up to twice the field
`
`As geometries shrink in more advanced
`ox thickness.
`generation DRAMs,
`this effect
`becomes
`a
`dominant
`factor.
`A common method of approaching this problem
`
`involves use of
`
`some
`
`sort
`
`of
`
`field oxidation
`
`encroachment reduction technique. Several techniques
`are discussed in the
`literature including SWAMI,
`SILO, BOX,
`Poly Buffer, Nitrox,
`trench isolation, and
`others.
`Each has their advantages and disadvantages,
`but all
`involve
`adding
`a great deal of
`added
`
`complexity to the process.
`
`Some prior
`
`art processes
`
`result
`
`in undue
`
`leading to junction leakage to levels
`crystal stress
`DRAM circuits. Others result in large
`intolerable on
`angle abrupt profiles (or even re-entrant profiles in
`some cases), making anisotropic etch of subsequent
`
`*
`
`Page 4 of 24
`
`

`

`WO90/05377
`
`PCT/US88/03841
`
`Prior art proposed solutions
`thin films difficult.
`strip and
`regrow (or double
`require a gate oxide
`strip and
`regrow)
`to form the final gate oxide. This
`has a disadvantage of
`thinning the
`field isolation
`oxide
`and
`adds
`extra process
`steps.
`Some of the
`other methods involve a Si
`etch into Si substrate,
`which
`requires
`extra precaution during subsequent
`process steps
`to avoid generation of stacking faults
`and other crystal defects.
`
`Other
`encroachment
`reduction schemes are more
`susceptible to isolation leakage due to the reduction
`in the active area N+ space.
`Increasing the standard
`field implant
`has
`other
`performance degradation
`is
`implications
`and
`therefore not desirable. These
`degradations
`include
`increased
`N+
`junction
`capacitance
`and
`aggravated
`transistor
`narrow W
`effects.
`The LER approach embodied here suffers from
`none of the above limitations.
`
`The purpose of this invention is to describe a
`simple yet
`extremely effective means of increasing
`cell
`capacitor
`area
`in an
`advanced
`DRAM process
`called "local encroachment reduction"
`"LER".
`It
`or
`involves
`reducing the
`encroachment
`of the field ox
`into the cell active area
`only
`locally in the cell
`active regions.
`It
`avoids all the pitfalls of prior
`art encroachment reduction schemes.
`
`Summary of the Invention
`
`The invention utilizes
`photomasking
`to define
`only the
`regions where
`the capacitor active area is
`to be
`and all field ox isolation regions between cell
`capacitor active
`regions.
`A wet oxide etch is then
`
`10
`
`15
`
`20,
`
`25
`
`30
`
`Page 5 of 24
`
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`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-4-
`
`a pre-determined fraction of the
`timed to remove
`field oxide present.
`
`A high energy boron implant is used to maintain
`adequate active area isolation after the removal of a
`fraction of
`field oxide.
`This
`implant also doubles
`as a cell high capacitance implant for increasing the
`junction capacitance
`and provides
`a barrier
`to
`minority substrate electrons.
`The dose here
`is
`maximized but kept
`safely
`below
`the
`point of
`increasing junction leakage.
`The energy is optimized
`for penetration through the remaining field ox, while
`locating the active area peak distribution just below
`the junction depth of
`the subsequent N+ cell bottom
`plate formation.
`
`After the high energy boron implant, resist is
`removed
`and
`an N-type bottom plate Capacitor
`is
`implanted.
`This
`implant
`can be masked or blanket
`implanted depending on
`the application's
`specific
`process flow.
`The N-type bottom plate implant dose
`is high enough to significantly compensate the boron
`implant,
`thus
`insuring proper bottom plate junction
`formation.
`
`that point,
`At
`existing techniques.
`
`the wafer
`
`is
`
`completed by
`
`results in a dramatic decrease in
`This process
`field isolation width obtainable,
`thus adding
`the
`directly to the cell capacitor total active area.
`
`adequate cell poly
`process maintains
`The
`The boron implant
`parasitic device
`field threshold.
`acts
`to
`increase
`the cell poly field threshold
`countering the effects of
`the
`field oxide thinning.
`
`fp
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Page 6 of 24
`
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`

`

`WO 90/05377
`
`PCT/US88/03841
`
`The
`
`amount
`
`of oxide
`
`removal
`
`is
`
`set mainly by
`
`considerations of leakage from closely spaced N+ to
`
`N+ junctions
`
`and can typically be greater than 50% of
`
`the field ox
`
`thickness with guardband.
`
`Parasitic
`
`field device
`
`leakage is generally not
`
`a problem due
`
`to the
`
`raised threshold resulting from the boron
`
`implant.
`
`The
`
`LER process
`
`requires only one extra wet
`
`etch step and perhaps a modification or addition of a
`
`10
`
`boron
`
`implant masking
`
`step.
`
`Due to the isotropic
`
`15
`
`20
`
`nature of the wet HF
`
`etch,
`
`the
`
`resulting isolation
`
`oxide profile remains gentle,
`
`easing subsequent thin
`
`film photomasking
`and
`etch steps.
`With
`the LER
`process, a
`strip and regrow of the initial oxide from
`the
`local
`oxidation oxide/nitride
`stack is not
`
`necessary.
`
`This
`
`is because the LER process can be
`
`added (though not mandatory)
`
`to the process flow after
`
`transistor formation and prior to cell poly formation.
`
`This approach
`
`avoids thinning the field oxide in all
`
`isolation regions outside
`peripheral
`array.
`It also eliminates
`the
`need
`
`of the memory
`for
`the extra
`
`strip and
`
`regrow process
`
`steps. This invention does
`
`not require any etch into the silicon substrate. This
`
`avoids the possibility of crystal fault generation and
`
`25
`
`propagation that
`
`could occur
`
`in the etch step or
`
`subsequent processing steps.
`
`The
`
`LER process provides
`
`no
`
`added Silicon
`
`stress and
`The process
`
`thus no added associated junction leakage.
`is applicable
`to grounded or Vec/2 field
`
`30
`
`plate designs.
`
`Major advantages
`
`of
`
`this
`
`invention over known
`
`prior art
`
`include:
`
`no added Si crystal stress at the
`
`isolation edges;
`
`simple process
`
`steps promoting good
`
`Page 7 of 24
`
`Page 7 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`invention can be performed with
`the
`wafer yield;
`standard fabrication equipment
`and
`can be easily
`
`retrofitted into most
`
`DRAM process
`
`flows;
`
`boron
`
`implant
`
`improves
`
`the
`
`isolation integrity between
`
`cells.
`
`Isolation region width reduction can be selected
`
`considerations of
`the electrical
`limited only by
`This limitation
`closely spaced N+ to N+ junctions.
`is much less
`than
`the
`encroachment
`aggravated
`photolithographic minimum of prior art schemes. Due
`to the
`isotropic nature of
`the wet
`HF etch,
`the
`resulting isolation oxide profile remains gentile,
`easing subsequent
`thin film photomasking and etch
`
`steps.
`
`a strip and regrow of the
`With the LER process,
`initial oxide
`from the
`local oxidation oxide/nitride
`stack is not necessary.
`This
`is because the LER .
`process can be added
`(though not mandatory)
`to the
`process flow after transistor
`formation and prior to
`cell poly formation.
`This
`approach avoids thinning
`the field oxide in isolation regions outside of the
`memory array.
`It also eliminates
`the need
`for the
`extra
`strip
`and
`regrow
`process
`steps.
`This
`
`embodiment does not require any etch into the Silicon
`
`10
`
`15
`
`20
`
`25
`
`substrate.
`
`This
`
`avoids
`
`the possibility of crystal
`
`fault generation and propagation that could occur in
`
`the etch step or subsequent processing steps.
`
`Brief Description of the Drawings
`
`30
`
`a wafer
`a cross-section of
`Figure ia shows
`during the
`fabrication of
`a
`semiconductor circuit
`
`device,
`
`in which active area
`
`is defined and the
`
`growth of field ox for isolation is completed;
`
`Page 8 of 24
`
`Page 8 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`shows the patterning of
`Figure 1b
`into photoresist;
`
`the LER mask
`
`shows a cross-section of a wafer which
`Figure 1c
`is oxide etched in order
`to reduce
`encroachment of
`
`silicon oxide into active cell area;
`
`Figure 1d
`
`shows the application of a high-energy
`
`boron implant;
`
`Figure ie shows
`resist strip;
`
`the wafer cross-section after
`
`10
`
`the cross-section of the wafer
`shows
`if
`Figure
`at the point of N+ cell bottom plate implantation;
`
`shows a cross-section of a wafer during
`Figure 2.
`the fabrication of a semiconductor circuit device,
`in
`
`which active area is defined;
`
`15
`
`shows the
`Figure 3
`wafer of Figure 2;
`
`growth of
`
`field ox onto the
`
`example of a
`top view of one
`shows a
`Figure 4
`repetitive cell layout on the wafer of Figure 3;
`
`20
`
`cross-section of a wafer which
`shows a
`Figure 5
`is dipped
`in order
`to reduce encroachment of silicon
`dioxide into active area;
`
`shows the cross-section of the wafer of
`Figure 6
`with
`subsequent
`N+ cell
`bottom plate
`Figure
`5,
`formation; and
`
`Page 9 of 24
`
`Page 9 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-8-
`
`Figure 7 shows the wafer of Figure
`
`6, witha
`
`dielectric layer
`formed over the active area and cell
`_ polysilicon formed over the dielectric layer.
`
`tap
`
`Detailed Description of the Preferred Embodiment
`
`This invention describes a technique to maximize
`capacitor area
`in a high density/high volume
`cell
`DRAM (dynamic
`random access
`memory)
`fabrication
`
`process in a sequence
`
`shown in Figures 1a - 1f.
`
`In
`
`Figures
`
`1,
`
`the left
`
`side shows
`
`a
`
`representative
`
`10
`
`device
`
`in the periphery of a dynamic random access
`
`memory
`
`(DRAM)
`
`chip,
`
`and
`
`the right
`
`side
`
`shows
`
`a
`
`portion of a memory array of the DRAM.
`
`The "local
`
`encroachment reduction" (LER) process
`
`flow just prior to an
`to the DRAM process
`is added
`N-type bottom plate capacitor implant step. Figure 2
`
`15
`
`shows
`
`a cross-section of
`
`during its fabrication.
`
`a
`
`A
`
`semiconductor circuit
`
`silicon wafer
`
`13
`
`is
`
`prepared by
`
`forming a
`
`thin film of oxide 15 and then
`
`depositing nitride 17
`
`over
`
`the thin oxide 15.
`
`The
`
`20
`
`nitride is masked
`
`and
`
`etched in order
`
`to define
`
`active area.
`
`The
`
`unmasked portions of the wafer 13
`
`are then implanted with boron
`
`in order
`
`to forma
`
`field implant of P-type material.
`
`25
`
`30
`
`After
`
`the
`
`field implant,
`
`a
`
`thick layer of
`
`silicon oxide
`
`21 is
`
`grown onto the wafer 13 to form
`
`field ox,
`
`as
`
`shown
`
`in Figure 3.
`
`The
`
`growth of
`
`Silicon oxide occurs in areas which
`
`are not covered
`
`by the nitride mask
`17, but tends to encroach on the
`active area, marked AA.
`The encroachment is present
`around the
`edges of
`the nitride 17, as indicated by
`dashed lines
`23, where
`the oxide
`21 begins to "buck
`up" or lift the nitride 17.
`
`Page 10 of 24
`
`Page 10 of 24
`
`

`

`WO90/05377
`
`PCT/US88/03841
`
`The
`top view of the wafer 13.
`shows a
`Figure 4
`includes word lines 33 which
`active area, marked 31,
`coincide
`in
`location to access
`transistors
`(not
`separately shown)
`on the
`active areas 31.
`The wafer
`13 is masked over the word lines 33 in order that the
`integrity of
`these word
`lines 33 not be affected by
`subsequent
`etching.
`This
`step, referred to as LER
`photomasking, defines
`the regions where the capacitor
`active area
`is
`to be
`35.
`This photo level also
`defines all field ox
`isolation regions
`between cell
`
`capacitor active regions.
`
`13 is
`the wafer
`LER photomasking,
`the
`After
`a top portion 41 of
`oxide etched in order
`to remove
`the field ox 21,
`as shown in Figure 5. This reduces
`the encroachment of
`the
`silicon oxide
`21
`into the
`active area
`31 by reducing the thickness of the field
`oxide 21
`in the regions of encroachment.
`
`top layer, referred to as
`This stripping of the
`dilute buffered hydrofluoric acid wet oxide etch, is
`timed to remove
`a pre-determined fraction of the
`field oxide.
`This wet oxide
`etch step also reduces
`the total thickness of the
`field oxide
`21,
`but the
`masking of
`the word
`lines 33 prevents this top layer
`41
`from being stripped at
`the
`location of
`the word
`
`10
`
`15 .
`
`20
`
`25
`
`lines.
`
`Prior to the dipping of the wafer to remove the
`top layer
`41,
`the nitride mask
`17
`is
`stripped.
`Preferably, this
`is accomplished prior to the masking
`of the word lines 33.
`
`30
`
`The
`reduced
`thickness
`of
`the
`field oxide 21
`adjacent to the active area 31 establishes an active
`
`Page 11 of 24
`
`Page 11 of 24
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`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-10-
`
`MOS transistor device in the completed wafer. This
`active parasitic MOS transistor device could result in
`
`shunting between adjacent active areas 31.
`
`7.
`
`od8
`
`referred to as a "LER boron
`step,
`implant
`An
`implant" step increases the threshold voltage (V ) of
`these active junction devices between active areas.
`In the LER boron implant
`step,
`a high energy boron
`implant
`is used to establish a higher concentration
`P-type region.
`The dose here
`is maximized but kept
`safely below the point of increasing junction leakage.
`The energy is optimized for penetration through the
`remaining field ox, while
`locating the active area
`peak distribution just below the junction depth of the
`subsequent N+ cell bottom plate formation.
`The high
`energy boron implant causes the boron to penetrate the
`oxide
`21
`and active area
`31. Where the oxide 21
`covers the wafer 13,
`the boron establishes a P-type
`region,
`shown
`in Figure
`6.
`The P-type region is
`directly below the field ox 21.
`In the active area,
`the boron penetrates deeply into the wafer 13. This
`becomes a high capacitance implant, which will extend
`beneath N+ material
`and
`raise the
`capacitance of
`active area capacitors.
`
`the
`Subsequent to the high capacitance implant,
`mask protecting the word
`lines 35 is stripped and an
`arsenic implant is applied throughout
`the wafer, as
`shown in Figure 6.
`The arsenic implant results in n+
`material extending beneath the active area,
`but not
`as
`deep as
`the high C
`implant.
`This becomes an
`N-type bottom plate capacitor
`implant. This implant
`can be masked or
`a blanket implant, depending on the
`application's
`specific
`process
`flow.
`In the
`preferred embodiment,
`the bottom plate capacitor
`implant is masked, but the bottom plate capacitor may
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Page 12 of 24
`
`Page 12 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-11-
`
`‘be blanket
`
`applied
`
`(without
`
`a mask).
`
`The N-type
`
`bottom plate implant
`
`dose
`
`is
`
`high
`
`enough
`
`to
`
`significantly compensate
`
`the LER boron implant,
`
`thus
`
`insuring proper
`
`bottom plate junction formation.
`
`The
`
`arsenic does not penetrate the field ox 21.
`
`Following the arsenic
`
`implant,
`
`a dielectric
`
`layer 51 is formed over
`
`the active area,
`
`and cell
`
`polysilicon 53
`
`is
`
`formed over the dielectric layer
`
`51. This results in the structure shown in Figure 7.
`
`10
`
`While the
`
`invention is described in terms of
`
`DRAMs,
`
`this
`
`is merely
`
`the preferred embodiment for
`
`which the inventive techniques were developed.
`
`The
`
`local
`
`encroachment
`
`reduction
`
`process
`
`is
`
`also
`
`applicable to related semiconductor circuit devices,
`
`15
`
`including video random access memories (VRAMs) and
`
`other multiport
`
`RAMS,
`
`and
`
`other
`
`semiconductor
`
`devices.
`
`Clearly,
`
`other
`
`steps may
`
`be taken within the
`
`scope of
`
`the invention in order to accomplish either
`
`20
`
`same or different circuit
`
`results. Accordingly,
`
`the
`
`invention should be
`
`read only as
`
`limited by the
`
`claims.
`
`Page 13 of 24
`
`Page 13 of 24
`
`

`

`-WO 90/05377
`
`PCT/US88/03841
`
`-12-
`
`Claims
`
`i. Method of
`
`forming semiconductor circuit devices
`
`as a part of each device, a plurality
`which include,
`of cells
`and active circuit
`elements
`to control
`
`the cells and active circuit elements forming
`signals,
`a
`repeating
`pattern on
`the device,
`the method
`comprising:
`,
`
`preparing a silicon wafer
`a)
`the wafer as a substrate;
`
`and establishing
`
`b)
`
`forming oxide
`
`on the wafer to define field
`
`10
`
`oxide and active areas;
`
`to define regions of
` photomasking
`c)
`isolation oxide to be reduced in thickness;
`
`field
`
`etching
`d)
`isolation oxide
`
`said
`to be
`
`field
`defined regions of
`reduced in thickness to remove
`
`15
`
`a pre-determined fraction of field oxide present; and
`
`implanting the wafer with a boron implant
`e)
`wherein the boron
`is
`implanted with energy levels
`which are optimized for penetration through the field
`oxide
`remaining after
`said etching of said defined
`regions of field isolation oxide
`to be
`reduced in
`thickness.
`
`20
`
`2.
`Method
`of
`forming
`semiconductor devices
`described in claim 1, further characterized by:
`
`as
`
`bottom plate capacitor
`implanting an N-type
`implant at an implant dose sufficient to significantly
`compensate the boron implant so as to insure a desired
`
`bottom plate junction formation.
`
`Page 14 of 24
`
`Page 14 of 24
`
`

`

`WO90/05377
`
`PCT/US88/03841
`
`-13-
`
`semiconductor devices
`forming
`of
`3. Method
`described in claim 2, further characterized by:
`
`as
`
`the N-type
`
`bottom plate capacitor implant being
`
`arsenic.
`
`4,
`
`Method
`
`of
`
`forming semiconductor devices
`
`as
`
`described in claim 1, further characterized by:
`
`the optimization of
`
`the
`
`energy
`
`levels
`
`for the
`
`implantation of
`
`the wafer with a boron implant after
`
`said etching
`
`of
`
`said
`
`defined regions of
`
`field
`
`isolation oxide
`
`to be reduced in thickness,
`
`including
`
`locating the active area peak distribution just below
`
`a junction depth of
`
`subsequent N+ cell bottom plate
`
`formation.
`
`semiconductor circuit memory
`forming
`Method of
`5.
`as
`a part of each device, a
`include,
`devices which
`plurality of memory cells and active circuit elements
`to control
`signals,
`the cells
`and active circuit
`
`elements forming a repeating pattern on
`
`the device,
`
`the method comprising:
`
`a)
`
`preparing a
`
`silicon wafer and establishing
`
`the wafer as a substrate;
`
`b)
`
`forming oxide
`
`on the wafer to define field
`
`10
`
`oxide and active areas;
`
`ey
`
`c)
`
`photomasking with
`
`photoresist
`
`to define
`
`local encroachment reduction regions where capacitor
`active area
`is to be, said photoresist defining field
`ox isolation regions
`between cell
`capacitor active
`
`15
`
`regions;
`
`Page 15 of 24
`
`Page 15 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-14-
`
`timing said
`and
`applying an oxide etch,
`d)
`etch to remove a pre-determined fraction of the field
`
`oxide;
`
`Mk
`
`we
`
`20
`
`25
`
`30
`
`e)
`implanting the wafer with boron at
`an
`implantation dose which is optimized,
`below a point
`of
`increasing
`junction leakage,
`for penetration
`through the remaining field oxide, while locating the
`active area peak distribution just below a junction
`depth of
`the
`subsequent
`N+
`cell
`bottom plate
`formation;
`
`£)
`
`removing said photoresist; and
`
`implanting an N-type bottom plate capacitor
`g)
`at
`an
`implant
`dose
`sufficient
`to
`implant
`significantly compensate
`the boron implant so as to
`insure a desired bottom plate junction formation.
`
`forming semiconductor memory devices
`6. Method of
`as described in claim 5, further characterized by:
`
`oxide
`field
`the
`etching
`isotropically
`etch to remove
`application of
`a wet oxide
`pre-determined fraction of the field oxide.
`
`by
`said
`
`forming semiconductor memory devices
`7. Method of
`as described in claim 5, further characterized by:
`
`buffered hydrofluoric
`using dilute
`oxide etch as said oxide etch.
`
`acid wet
`
`me
`
`forming semiconductor memory devices
`8. Method of
`as described in claim 5, further characterized by:
`
`Page 16 of 24
`
`Page 16 of 24
`
`

`

`WO90/05377
`
`PCT/US88/03841
`
`-15-
`
`the N-type bottom plate capacitor
`blanket application.
`
`implanted by
`
`semiconductor memory devices
`forming
`9, Method of
`as described in claim 5, further characterized by:
`
`masking the wafer subsequent said removal of
`a)
`said photoresist,
`in order to apply photoresist for
`defining said N-type bottom plate capacitors; and
`
`the N-type bottom plate capacitor implanted
`b)
`into regions defined by said photoresist.
`
`10. Method of
`
`forming
`
`semiconductor memory devices
`
`as described in claim 5, further characterized by:
`
`removed
`oxide
`said predetermined fraction of
`being greater than 50% of the field ox thickness.
`
`semiconductor memory devices
`forming
`11. Method of
`as described in claim 10, further characterized by:
`
`said predetermined fraction of
`being determined by
`considerations
`closely spaced N+ to N+ junctions.
`
`removed
`oxide
`of leakage from
`
`12. Method of
`
`forming
`
`semiconductor memory devices
`
`as described in claim 11, further characterized by:
`
`said implanting the wafer with boron at
`
`an
`
`implantation dose being
`transistor
`formation
`
`and
`
`performed
`prior
`
`to
`subsequent
`to
`cell poly
`
`formation.
`
`13. Method of
`
`forming semiconductor memory device as
`
`described in claim 5, further characterized by:
`
`Page 17 of 24
`
`Page 17 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`-16-—
`
`removed
`said predetermined fraction of oxide
`being determined by
`considerations of
`leakage from
`closely spaced N+ to N+ junctions.
`
`forming semiconductor memory devices
`14. Method of
`as described in claim 13, further characterized by:
`
`an
`said implanting the wafer with boron at
`to
`implantation
`dose
`being performed
`subsequent
`transistor
`formation
`and
`prior
`to
`cell poly
`formation.
`
`forming semiconductor memory devices
`15. Method of
`as described in claim 5, further characterized by:
`
`an
`said implanting the wafer with boron at
`to
`implantation
`dose
`being performed
`subsequent
`transistor
`formation
`and
`prior
`to
`cell poly
`formation.
`
`semiconductor memory devices
`forming
`16. Method of
`as described in claim 5, further characterized by:
`
`said
`of
`forming each
`devices with a Vcec/2 field plate.
`
`semiconductor memory
`
`forming semiconductor memory devices
`17. Method of
`as described in claim 5, further characterized by:
`
`semiconductor memory
`said
`of
`forming each
`devices with a grounded field plate.
`
`‘pe
`
`Page 18 of 24
`
`Page 18 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`1/4
`
`Periphery
`
`Memory
`
`ISOLATION OX
`
`Figure IA
`ISOLATION OX
`
`ROTRee
`P-
`CELL—~m!
`|
`P=} <_
`ACTIVE AREA }
`!
`to
`ENCROACHMENT
`
`LER Mask Figure 1B
`Photo Deposit
`
`P-
`
`P-
`
`Figure IC
`—~— OXIDE
`ROT P
`P-
`
`P-
`
`SUBSTITUTE SHEET ©
`
`Page 19 of 24
`
`Page 19 of 24
`
`

`

`WO 90/05377
`
`2/4
`
`Periphery
`|
`, Figure ID
`
`PCT/US88/03841
`
`Memory
`
`Bhbohe|
`
`Tre
`
`P-
`
`OXIDE
`aKe
`P-
`
`Figure lE
`—Z¥” KS. ,
`RTO ROS_
`
`P-
`
`Pp
`
`
` _YY Vvdf
`OT V
`f
`P
`pi
`INCREASED
`
`CELT
`AREA
`
`SUBSTITUTE SHEET
`
`Page 20 of 24
`
`Page 20 of 24
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`Figure 2
`
`3/4
`
`17
`
`13
`
`o+@S23,3SoaL.i
`Cha0550P005999880
`
`OGODAS¢afOfFDVYVVWAVNANASVVAN
`adft4bbtdce009988
`
`7NNSAatgtaggafatSaag
` ORBESRSPIBIBO9505050taperQPPC5PHP525505COPOCE
`
`
`CROPSSTSBCSF05050522eeee
`
`CROPeohoeoePovoPooh
`OPOSEB65505052SO5P55580559BICBeBCG
`SREBRESEENOS
`SRBERICBBIB00505050
`
`CORDODDOIOSDOOPPOOOOoooone
`RS5a25,2eeee
`OOOODOKTECBOICBOICDseRPoesCoSqDBRPh5050
`
`eePGEO? SSTSeoeieoeBeeeoeeeeeaeeeaeeeoeSoo)KO9S525B50erstDeOCF860525750RSSDOOCSSSCSCCBCCICICCHIC
`
`85250505RATNERKALKIERRERIIOP5585CFI5BoBC
`
`
`
`
`
`BCRC5CSBiBSB505.05
`CMSBciseSEPP580505.05
`
`SPEERPoopSREoESS
`BPSCCOICISCOCHRCOCR8B09090509
`
`
`DSSSCEOSSCOPCNHBOICI
`PORNNN
`TABESIISSHORII
`PKKDEKPKCI
`SOPPOKBKB50eeSee
`meaner}:Cj——
`scatmannpptetere
`}RORORS.,C2
`
`PSOESBS5505OSISBOPPHB50505
`egpeMhrnmeaeenssahserene)
`0a40525.05
`
`35
`
`33
`
`7|r
`
`RHRATITUTE SHEET
`Page 21 of 24
`
`Page 21 of 24
`
`
`
`
`

`

`WO 90/05377
`
`PCT/US88/03841
`
`4/4
`
`Figure 6
`
`Figure 5
`
`
`
`Figure 7
`
`SVimMeTrrire CHEeT
`Page 22 of 24
`
`Page 22 of 24
`
`

`

`INTERNATIONAL SEARCH REPORT
`International Application No. PCT/US88/03841
`|, CLASSIFICATION OF SUBJECT MATTER Uf several classification symcols apply, incicate all) &
`Accaraing to International Patent Classification (IPC) of to voth National Classification and IPC
`INT.
`CL
`HOLL
`21/265; HOLL
`29/96
`437/52
`437/28:
`437/30;
`437/473
`I. FIELOS SEARCHED
`
`Minimum Documentation Searched 7
`
`Classification System|
`Classification Symbols
`437/28;
`437/30; 437/47;
`
`437/70;
`437/69;
`437/63;
`437/52;
`
`Documentation Searched other than Minimum Oocumentation
`to the Extent that such Documentsare Included in the Fields Searched §i
`
`%
`
` a US
`
`437/29}.
`
`437/48;
`
`357/23.6
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Y
`
`Y
`
`
`
`13
`
`
`
`Relevant to Claim No. ‘3
`Category °
`
`
`
`
`C.tation of Document, " with indication, where appropriate, of the relevant passages ‘2
`
`
`
`1-8,10,11,
`US,A,
`X
`4,414,058
`(Mueller),
`08 November 1983,
`See figures 1-4.
`
`
`
`US, A,
`4,352,236
`(McCollum),
`
`
`
`05 October 1982,
`See figures 3-6.
`
`
`
`US, A,
`4,240,092
`(Kuo),
`16 December 1980,
`See figures 4b~4d.
`
`
`
`
`
`US, A,
`4,366,613 (Ogura et al.)
`
`04 January 1983,
`See figures 2E-2G.
`12,14,15
`
`
`
` epr SSil. DOCUMENTS CONSIDERED TO BE RELEVANT 9
`
`Yy
`
`
`
`* Special categories of cited documents: '0
`wat
`A“ document defining the general state of the art which is not
`considered to be of particular retevance
`“E" earlier document but published on orafter the international
`filing date
`“L" document which may throw doubts on priority claim(s) or
`which is cited to establish the publication date of another
`citation or other special reason (as specified)
`“O" documentreferring to an oral disclosure, use, exhibition or
`other means
`"“P" document published prior to the internationalfiling date but
`later than the priority date claimed
`WV. CERTIFICATION
`Date of the Actuai Completion of the International Search
`
`,
`
`t
`
`“T" later document published alterthe internationalfiling date
`ty date and nat in conflict with the apo ication Bu
`oF prior
`heory
`underlying
`the
`citedtounderstand the principle or t
`y
`ying
`“X"" document of particular relevance:
`the claimed invention
`cannot be considered novel or cannot be considered to
`involve an inventive step
`the claimed invention
`“¥" document of particular relevance;
`cannot be considered to involve an inventive step when the
`document 1s combined with one or more other such docu-
`ments, such combination being obvious to a person skilled
`in the art.
`“&" document member of the same patent family
`
`Date of Mailing of this international Search Report
`
`1
`
`vo
`
`mew
`
`JUL 1989
`Signature ot Authorized ‘Officer ;
`International Searching Authority
`Cah iAttwuehana
`Olik Chaudhuri-Primary Examine
`ISA/US
`
`Form PCTASA/210 (second sheet) (Rev. 11-87)
`
`Page 23 of 24
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 23 of 24
`
`

`

`r ®
`
`»
`
`oS
`
`International Anplication No. Pct /US88/03 841ee
`FURTHER INFORMATION CONTINUED FROM THE SECOND SHEET
`
`Y
`
`(Teng et al),
`4,686,552
`US,A,
`ii August 1987, See column 5,
`lines 22-29.
`
`16, 17
`
`Vv. OBSERVATIONS WHERE CERTAIN CLAIMS WERE FOUND UNSEARCHABLE'!
`
`
`This international search report has not been established in respect of certain claims under Article 17(2) (a) for the following reasons:
`4 Claim numbers
`. because they relate to subject. matter !* not required to be searched by this Authority, namely:
`
`, becausetheyrelate to parts of the international application that do not comply wilh the prescribed require-
`20] Claim numbers
`ments to such an extent that no meaningful international search can be carried out '3, specifically:
`
`
`
`30 Claim numbers
`because they are dependentclaims not drafted in accordance with the second and third sentencesof
`PCT Rule 6.4(a).
`
`
`vi OBSERVATIONS WHERE UNITY OF INVENTION IS LACKING?
`
`This International Searching Autharity found multiple inventions in this international application as follows:
`
`in| As all required additional search fees were timely paid by the applicant, this international search report covers all searchable claims
`of the international application.
`2C] As only some of the required additional search fees were timely paid by the applicant, this international search report covers only
`those claims ofthe international application for which fees were paid, specifically claims:
`
`30] No required additional search fees were timely paid by the applicant. Consequently, this international search report is restricted to
`the invention first mentioned in the claims; il is covered by claim numbers:
`
`4.
`
`As all searchable claims could be searched without effort justifying an additional fee, the International Searching Authority did not
`invite payment of any additional fee.
`Remark onProtest
`
`T The additiona! search fees were accompanied by applicant's protest.
`C] No protest accompanied the paymentof additional search fees.
`
`Form PCTASA/210 (supplemental shest (2 (Rev. 11-87)
`
`Page 24 of 24
`
`Page 24 of 24
`
`