STEEP SUBTHRESHOLD CHARACTERISTIC AND ENHANCED TRANSCONDUCTANCE
`OF
`FULLY-RECESSED OXIDE (TRENCH) ISOLATED 1/4 pm WIDTH MOSFETS
`
`N. SHIGYO, T. WADA, S. FUKUDA, K. HIEDA, T. HAMAMOTO,
`H. WATANABE, K. SUNOUCHI and H. TANGO
`
`VLSI Research Center, Toshiba Corporation
`1, Komukai-Toshiba-cho, Kawasaki-shi, 210 Japan
`
`ABSTRACT
`This paper describes the dependence of MOSFET gate-
`controllability on the field isolation scheme. It is found that
`a fully-recessed oxide (trench) isolated MOSFET has a sharp
`cutoff characteristic and high transconductance in comparison
`with a non-recessed one. These features of the fully-recessed
`oxide MOSFET are due to the crowding of the gate’s fring-
`ing field at the channel edge. It is also found that the gate
`and diffused line capacitances for the fully-recessed oxide
`isolation are small so that high switching speed operation can
`be expected.
`
`INTRODUCTION
`Reduction of the field isolation area is a major concern in
`achieving a high performance and high packing density
`VLSI. Several bird’s-beak free isolation methods have been
`proposed, e.g., BOX [1],[2] and SWAMI [31. However,
`lower submicron device characteristics in relation to the field
`isolation scheme have been seldomly reported.
`In previous works [1]-[lo], attention has been paid mainly
`to the threshold voltage dependence on the field isolation
`scheme. It was found that the MOSFET threshold voltage
`and subthreshold characteristic strongly depended on the field
`isolation scheme. In a non-recessed oxide MOSFET shown
`in Fig. 1 (a), the threshold voltage becomes higher with de-
`creasing channel width, the so-called narrow-channel effect
`[4],[5]. This results from the extra bulk charge stored under
`a thick oxide region. In a fully-recessed oxide MOSFET
`shown in Fig. 1 (b), however, the threshold voltage becomes
`lower for the narrower width case, which is referred to as the
`inverse narrow-channel effect [6]-[9]. This phenomenon
`is
`explained by the crowding of the gate’s fringing field at
`the
`channel edge due to its convex shape, as shown in Fig, 1 (b).
`It was also reported that an anomalous subthreshold current
`hump can be
`observed for a fully-recessed oxide MOSFET
`due to the parasitic edge MOSFET [1],[3],[10]. However,
`there has been no publication concerning the dependence of
`gate-controllability on the field oxide scheme,
`The purpose of this paper is to investigate which field
`isolation scheme is advisable for 1/4 pm feature size VLSIs
`from the viewpoint of device performance, such as the
`subthreshold swing S and the transconductance gm, using a
`
`three-dimensional
`[61,[71,~101,~111.
`
`device
`
`simulator
`
`TOPMOST
`
`EXPERIMENTAL RESULTS
`A series of trench and LOCOS isolated MOSFETs have
`been fabricated.
`Figure 2 shows the experimental results of the subthres-
`S which is defined by dVG/d(logID). The
`hold swing
`effective channel length Leff is 10 pm and drain voltage VD
`is 0.05 V to eliminate the short-channel effect. For LOCOS
`isolation, the subthreshold swing is almost constant for chan-
`nel widths down to the submicron region. On the other hand,
`the subthreshold swing of the fully-recessed oxide (trench)
`MOSFET is decreased with a reduction of the channel width,
`Le., the fully recessed oxide MOSFET has a steep subthres-
`hold characteristic.
`
`THREE-DIMENSIONAL ANALYSIS
`Two typical isolation schemes shown in Fig. 1 are used
`to analyze the field
`isolation scheme dependent MOSFET
`characteristics.
`Subthreshold Swing S
`Figure 3
`three-dimensionally simulated
`the
`shows
`subthreshold swing dependence on the channel width. Simu-
`lations are carried out for the effective channel length Leff =
`0.05 V to eliminate the short-
`2um and drain voltage V
`P.=
`channel effect. It is exhlblted that the
`fully-recessed oxide
`MOSFET has a small subthreshold swing, Le., a sharp cutoff
`characteristic. This is due to the large depletion layer at the
`channel edge, as schematically illustrated in Fig. 1 (b), which
`results from the gate’s fringing field. A small depletion
`capacitance Cd results in a small subthreshold swing S, since
`the subthreshold swing S is approximately proportional to
`l+C /Cox [12], as shown in Fig. 4 (a).
`gigure 5 shows the dependence of the subthreshold swing
`S on the gate oxide thickness tox. This figure suggests that,
`for a 0.25 pm channel width, a 12 nm gate oxide fully-
`recessed MOSFET is equivalent to a 6 nm gate oxide non-
`recessed one in regard to the subthreshold swing. It should
`be noted that the subthreshold swing S linearly depends on
`the gate oxide thickness tox in accordance with the equation
`shown in the inset of Fig. 5.
`
`636-IEDM 87
`
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`
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`~~2515-5~8710000-0636
`
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`A short-channel MOSFET with Leff = 0.3 pm is exam-
`ined, as shown in Fig. 6. Even for the short-channel case,
`the subthreshold swing of the fully-recessed MOSFET is
`smaller than that of
`the non-recessed one. The slope of the
`S-tox characteristic becomes steeper mainly due to an in-
`crease in substrate concentration, i.e., an increase of Cd. No
`significant short-channel effect is observed for the fully-
`recessed oxide MOSFET, because the influence of the drain
`to the channel is weakened by its high gate-controllability.
`
`Transconductance gm
`Figure 7 shows the gm-VG characteristics, which are
`simulated using the
`field dependent mobility model [13].
`The gm peak value of the fully-recessed oxide MOSFET is
`higher than that
`of the non-recessed one. The reason for a
`high gm peak is the small Cd of the fully-recessed oxide
`MOSFET, which can be explained by an analytical model of
`over
`gm as shown in Fig. 4 (b). A hump of gm for t
`QX
`20nm can be seen, which corresponds to the parasitlc
`edge
`MOSFET [lo].
`
`Countermeasures for the Low Threshold Voltage Vth
`A drawback of the fully-recessed oxide MOSFET is its
`low threshold voltage, which may cause a leakage drain
`current at VG = 0 V. However, the leakage current is not as
`large as that inferred from the inverse narrow-channel effect,
`because of its steep subthreshold characteristic. In addition,
`the threshold voltage can be improved by sidewall implanta-
`tion [l], [lo],
`tapering the sidewall [7] and rounding the
`so
`corner edge. However, these approaches cause high Cd
`that the gate-controllability is reduced.
`An appropriate
`choice of the gate material, e.g., tungsten, is most
`favorable,
`since its midgap work
`function results in a desired threshold
`voltage without the need for channel implant into n- and p-
`channel devices
`[14] without losing
`its high gate-
`controllability. It should be noted that the
`origin for the
`lower threshold voltage of an n-channel MOSFET is the use
`of an n+ poly-si gate.
`
`Circuit Operation Speed
`the fully-recessed oxide
`The gate capacitance CG of
`MOSFET is about 20 % smaller than that of the non-recessed
`one due to the smaller Cd. Furthermore, as shown in Fig. 8,
`the diffused line capacitance Cdiffused line of the fully-
`recessed oxide isolation is also 20 % smaller than that of the
`non-recessed one, which agrees with the
`experiments [2].
`These small C and Cdiffused line with a high transconduc-
`G
`result in 40 % higher circuit operation compared
`tance gm
`with the non-recessed case, when the operation speed is sim-
`-1
`(CG + Cdiffused line).
`ply estimated by gm
`
`CONCLUSION
`The dependence of gate-controllability on the field isola-
`tion scheme has been
`analyzed. Advantages of the fully-
`recessed oxide isolation are summarized in Fig. 9. Small de-
`
`due to the gate’s fringing field,
`pletion capacitance C
`results in small S, higf gm and
`small CG. Because of its
`structure, Cdiffu e
`line is also small. These lead to excel-
`lent gate-controflaklity and high speed circuit operation.
`These features push a fully-recessed oxide isolation to the
`main stream for lower submicron VLSIs.
`A drawback of the fully-recessed oxide MOSFET is its
`low threshold voltage. However, the origin for the lower
`threshold voltage of an n-channel MOSFET is the use of an
`n+ poly-Si gate. Owing to the high gate-controllability, the
`threshold voltage strongly reflects the gate material. The use
`of an tungsten gate realizes the desired threshold voltage
`without the need for channel implant into n- and p-channel
`devices while preserving the high gate-controllability. The
`adoption of the fully-recessed oxide (trench) isolation with
`tungsten gate CMOS is one of the most promising device
`features for the 1/4 pm VLSI era.
`
`ACKNOWLEDGMENTS
`The authors wish to thank Y. Oowaki, H. Ishiuchi, M.
`Kakumu, Dr. T. Iizuka and Prof. R. Dang for their helpful
`discussions on this work. Appreciation is extended to M.
`Kashiwagi for his support and encouragement.
`
`REFERENCES
`[l] K-Kurosawa, TShibata and H.Iizuka, IEDM Tech. Dig.,
`pp. 384-387, 1981.
`[2] TShibata, et al., IEDM Tech. Dig., pp. 27-30, 1983.
`[3] T.Iizuka, K.Y.Chiu and J.L.Mol1, IEDM Tech. Dig., pp.
`380-383, 1981.
`[4] K.O.Jeppson, Electronics Letters, 11, pp. 297-299, 1975.
`[SI L.A.Akers and J.J.Sanchez, Solid-St. Electron., 25, pp.
`621-641, 1982.
`[6] N.Shigyo, M.Konaka and R.Dang, Electronics Letters,
`18, pp. 274-275, 1982.
`[7] N.Shigyo, M.Konaka and R.Dang, IECE Japan, J66-C,
`pp. 1035-1040, 1983 (in Japanese).
`[8] M.Sugino and L.A.Akers, IEEE Trans. Electron Device
`Letters, EDL-4, pp. 114-1 15, 1983.
`[9] P.T.Lai and Y.C.Cheng, Solid-St. Electron., 28, pp. 551-
`554, 1985.
`[lo] N.Shigyo and R.Dang, IEEE Trans. Electron Devices,
`ED-32, pp. 441-445, 1985.
`[ 111 N.Shigyo and R.Dang, in: Process and Device Modeling
`(W.L.Eng1, Ed.), North-Holland, 1985, pp. 301-327.
`[12] S.M.Sze, Physics of Semiconductor Devices (2nd Ed.),
`1981.
`[13] K.Yamaguchi, IEEE Trans. Electron Devices, ED-30,
`pp. 658-663,1983.
`[14] B.Devari, et al., Roc. VLSI Symp., pp. 61-62, 1987.
`
`28.3
`
`IEDM 87-637
`
`Page 2 of 4
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`

`

`-W-
`
`+W-
`
`I
`
`Non - Recessed
`
`I
`
`Si
`
`Fully-Recessed
`
`Fig. 1 (a) Non- and (b) fully-recessed oxide MOSFETs. The depletion capa-
`citance Cd of the fully-recessed oxide MOSFET is small due to the
`gate's fringing field.
`
`100
`
`I \
`
`- - - Non-Receered
`
`- o- Semi-Recessed (LOCOS)
`Experiments [
`-*-Fully-Recessed (TRENCH)
`
`I
`0
`
`I
`1
`
`I
`2
`
`I
`I
`4
`3
`Weff (pm)
`Fig. 2 Experimental results of subthreshold swing for trench
`and LOCOS isolations. The trench isolated MOS-
`E T has a small subthreshold swing, i.e., a steep
`subthreshold characteristic.
`
`A
`
`"
`
`I
` 10
`
`Vo
`
`*O.O5V
`I
`3
`
`I
`4
`
`0
`
`I
`I
`
`I
`2
`W (prn)
`Fig. 3 Dependences of subthreshold swing on channel
`width and substrate bias.
`
`Linear Region
`
`VG
`
`Subthreshold Region
`
`ID : 90-
`
`01 q D L
`nS
`
`d (log 1,)
`-I
`= [ T I
`
`
`
`I
`
`I
`
`kT
`
`=,In
`
`where
`
`cd
`IO (I+-)
`cox
`q
`where nS =ni eiiT"**-+n#'
`(a>
`Fig. 4 Analytical model of (a) subthreshold swing and (b) transconductance.
`Both S and gm depend on Cd. Small Cd results in small S and high gm.
`
`(depletion)
`
`(strong inversion)
`
`638-IEDM 87
`
`28.3
`
`Page 3 of 4
`
`

`

`s 120
`8
`
`/
`
`80
`5 70
`f 60
`
`v)
`
`50
`
`,
`
`0
`
`20
`30
`IO
`Gate Oxide Thickness tox (nm)
`Fig. 6 Dependence of subthreshold swing on oxide thick-
`ness for Leff = 0.3 pm.
`
`3
`
`--- Non-Recessed
`- Fully-Recesmd
`
`'\
`
`N ~ D m 5 X 10'o~-'
`
`I
`
`I
`
`I
`
`( c ) O
`
`I
`
`I
`
`I
`I
` 3 4
`2
`5
`6
`Reverse Bias Voltage VR ( V I
`(a) Non- and (b) fully-recessed oxide
`diffused line and (c) its capacitances.
`
`P
`
`isolated
`
`Fig. 8
`
`50
`
`0
`
`Fig. 5 Dependence of subthreshold swing on oxide thick-
`ness for Leff = 2 pm.
`
`0
`
`I
`
`- Fully-Recessed
`--- Non-Recessed
`W = 0.25prn
`L e f f = 0.3pm
`X j =0,15prn
`Nsu~=2xlO'~cm-'
`VD *O.O5V
`
`0
`
`0.5
`
`1.5
`
`2
`
`I
`VG (v)
`Fig. 7 Field isolation scheme dependent transconductance
`for Leff = 0.3 pm. The gm peak value of the fully-
`of the
`recessed oxide MOSFET is higher than that
`non-recessed one.
`
`Fig. 9 Advantages of fully-recessed oxide isolation.
`
`28.3
`
`IEDM 87-639
`
`Page 4 of 4
`
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