UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-012461
`Patent 7,126,174 B2
`
`
`
`
`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`
`
`
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`
`
`
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`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-012461
`Patent 7,126,174 B2
`
`
`
`
`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`In accordance with 37 C .F.R. § 42.63(e), Petitioner hereby submits a current
`
`listing of Taiwan Semiconductor Manufacturing Company, Ltd.’s exhibits to the
`
`Board and counsel for Patent Owner.
`
`LIST OF EXHIBITS
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhibit 1001 US. Patent No. 7,126,174 to Segawa et al.
`
`Exhibit 1002 US. Patent No. 5,153,145 to Lee et a1.
`
`Exhibit 1003 US. Patent No. 3,617,824 to Shinoda et a1-
`
`Exhibit 1004 Corrected Declaration of Dr. Sanjay Kumar
`
`Banerjee, Ph.D. in Support of Petition for Inter
`
`Partes Review of United States Patent No.
`
`7,126,174 (IPR2016—01246). X
`
`X
`
`X
`
`x
`
`x
`
`x
`
`x
`
`x
`
`Exhibit 1005 J.A. Appels et al-, “Some Problems of MOS
`
`Technology,” Philips Tech. Rev. vol. 3] nos. 7—9,
`
`pp. 225—36, 276 (1970).
`
`Exhibit 1006 US. Patent No. 4,110,899 to Nagasawa et a1.
`
`Exhibit 1007 US. Patent No. 3,787,251 to Brand et al.
`
`Exhibit 1008 B.B.M. Brandt et al., “LOCMOS, a New
`
`Technology for Complementary MOS Circuits,”
`
`Philips Tech. Rev. vol. 34 no. 1, pp. 19—23 (1974).
`
`Exhibit 1009 U S Patent No 5 702 976 to Schuegraf et al
`.
`.
`.
`,
`,
`
`.
`
`Exhibit 1010 US. Patent No. 4,506,434 to Ogawa et a1.
`
`Exhibit 1011 US Patent No 4 957 590 to Douglas
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhibit 1012 US. Patent No. 5,976,939 to Thompson et a1 .
`
`X
`
`x
`
`x
`
`7,126,174 (IPR2016-01247).
`
`Exhibit 1019 Japanese Patent Application No. 7-1921 81 to
`
`Segawa et al.
`
`Exhibit 1020 Certified Translation of Japanese Patent
`
`Application No. 7-192181 to Segawa et al.
`
`Exhibit 1021 File History of US. Patent No. 7,126,174 to
`
`Segawa et al.
`
`Exhibit 1022 File History of Japanese Patent Application No. 7
`
`330112 to Segawa et a1.
`
`Exhibit 1023 Certified Translation of Portions of the File
`
`History of Japanese Patent Application No. 7
`
`330112 to Segawa et a1.
`
`Exhibit 1024 Corrected Declaration of Dr. Sanjay Kumar
`Banerjee, PhD. in Support of Petition for Inter
`Partes Review of United States Patent No.
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhibit 1025 E. Adler et al., “The Evolution of IBM CMOS
`
`DRAM Technology,” IBM J. Res. Develp., vol.
`
`39, no. 1/2, pp. 167-88 (Jan/Mar. 1995).
`
`Exhibit 1026 Japanese Patent Application No. H03-379033 to
`
`Sumi et al.
`
`Exhibit 1027 Certified Translation of Japanese Patent
`
`Application No. H03-379033 to Sumi et a1.
`
`Exhibit 1028 Japanese Patent Application No. S59-181062 to
`
`Horiguchi.
`
`Exhibit 1029 Certified Translation of Japanese Patent
`
`Application No. 859-181062 to Horiguchi.
`
`Exhibit 1030 Japanese Patent Application No. H07-1 835 18 to
`
`Ueda et al.
`
`Exhibit 1031 Certified Translation of Japanese Patent
`
`Application No. H07-183518 to Ueda et al.
`
`Exhibit 1032 US. Patent No. 4,651,411 to Konaka et al.
`
`Exhlblt 1033 Japanese Patent Application No. $58-73 163 to
`
`Konaka et al.
`
`
`
`US. Patent No. 6,218,266 to Sato et al.
`US. Patent No. 5,445,996 to Kodera et al.
`US. Patent No. 4,511,430 to Chen et al.
`US. Patent No. 4,599,789 to Gasner.
`
`Exhibit 1038 US. Patent No. 4,855,247 to Ma et al.
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhibit 1039 US. Patent No. 5,102,816 to Manukonda et a1.
`
`x
`
`Exhibit 1040 US. Patent No. 5,512,771 to Hiroki et al.
`
`Exhibit 1041 US. Patent No. 5,648,284 to Kusunoki et al.
`
`Exhibit 1042 S. Deleonibus et al., “Optimization of a Shallow
`
`x
`
`x
`
`Trench Isolation Refill Process for High Density
`
`Non Volatile Memories Using 100% Chemical-
`
`Mechanical Polishing: The BOX-ON Process,”
`
`Extended Abstracts of the Spring 1994
`
`Electrochem. Soc. Meeting, abstract no. 171, vol.
`
`94-1, pp. 267-77 (May 22-27, 1994).
`
`CDD—t Em 3E(D F‘? 3O0(DU}U} 5fig05 A _l \O\OOV
`
`Exhibit 1043 J.M. Pierce et al., “Oxide-Filled Trench Isolation
`
`Planarized Using Chemical/Mechanical
`
`Polishing,” Proceedings of the Third International
`
`Symposium on Ultra Large Scale Integration
`
`Science and Technology, vol. 91-11, pp. 650—56
`
`(1 99 l ).
`
`Exhibit 1044 Excerpts from C Y Chang & S M Sze ULSI
`
`x
`
`Technology” (1996)
`
`Exhibit 1045 Excerpts from S. Wolf, “Silicon Processing for the
`
`VLSI Era: Volume 1: Process Technology” (1986).
`
`Exhibit 1046 Excerpts fi'om S. Wolf, “Silicon Processing for the
`'
`,,
`
`Exhibit 1047 H.W. Fry et al., “Applications ofAPCVD
`
`x
`
`TEOS/O3 Thin Films in ULSI IC Fabrication,”
`
`Solid State Tech., pp. 31-40 (Mar. 1994).
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhlblt 1048 S. Poon & C. Lage, “A Trench Isolation Process
`
`for BiCMOS Circuits,” Proceedings of the 1993
`
`IEEE Bipolar Circuits & Tech. Meeting 3.3, pp.
`
`45—48 (Oct. 4—5, 1993).
`
`Exhlblt 1049 L. Clement et al., “Microscopy Needs for Next
`
`Generation Devices Characterization in the
`
`Semiconductor Industry,” J. Physics: Conference
`
`Series, vol. 326, conf. 1, 17th International
`
`Conference on Microscopy of Semiconducting
`
`Materials, pp. 1—14 (Apr. 4-7, 2011).
`
`I I
`
`
`
`Exhibit 1050 R. Pantel et al., “Physical and Chemical Analysis
`
`x
`
`of Advanced Interconnections Using Energy
`
`Filtered Transmission Electron Microscopy,”
`
`Microelectronic Engineering, vol. 50, nos. 1—4, pp.
`
`277-84 (Jan. 2000).
`
`Exhibit 1051 G. Servanton & R. Pantel, “Arsenic Dopant
`
`i I
`
`Mapping in State-of-the -Art Semiconductor
`
`Devices Using Electron Energy-Loss
`
`Spectroscopy,” Micron, vol. 41, no. 2, pp. 118-22
`
`(Feb. 2010).
`
`Exhiblt 1052 K. Kurosawa et al., “A New Bird’s-Beak Free
`
`Field Isolation Technology for VLSI Devices,”
`
`Proceedings of the 1981 International Electron
`
`Devices Meeting, pp. 384-87 (Dec. 7-9, 1981).
`
`Exhibit 1053 H.K- Kang et al., “Highly Manufacturable Process
`
`Technology for Reliable 256 Mbit and 1 Gbit
`
`DRAMs,” Proceedings of the 1994 International
`
`Electron Devices Meeting, pp. 635-38 (Dec. 11-
`
`14, 1994).
`
`
`
`IPR2016-01246, IPR2016-01247
`
`Patent 7,126,174 B2
`
`Exhibit No.
`
`Description
`
`Previously
`
`Submitted
`
`Exhlblt 1054 Semiconductor Industry Association, “The
`
`National Technology Roadmap for
`
`Semiconductors” (1994).
`
`Exhlblt 1055 B. Davarik et al., “A New Planarization
`
`Technique, Using a Combination of RIE and
`
`Chemical Mechanical Polish (CMP),” Proceedings
`
`of the 1989 International Electron Devices
`
`Meeting, pp. 61-64 (Dec. 3-6, 1989).
`
`Exhlblt 1060 Petitioner’s Demonstratives. Exhibit 1056 Deposition Transcript of E. Fred Schubert, PhD.
`
`dated May 25, 2017.
`
`x
`
`Exhlbit 1057 Declaration of Dr. Sanjay Kumar Banerjee, Ph.D_
`
`in Support of Petitioner’s Reply.
`
`Exhlblt 1058 US. Patent No. 5,173,439 to Dash et a1.
`
`Exhiblt 1059 Errata Sheet (dated June 6, 2017) from the
`
`Deposition of E. Fred Schubert, Ph.D.
`
`
`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`Petitioner hereby certifies that copies of all listed documents above have
`
`been served on counsel for Patent Owner.
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`Respectfully submitted
`
`Dated: August 3, 2017
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`
`
`By: /Darren M. Jiron/
`
`Darren M. Jiron
`Reg. No. 45,777
`
`Lead Counsel for Petitioner
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`8
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. § 42.6(e), this is to certify that I served true and
`
`correct copies of the PETITIONER’S UPDATED EXHIBIT LIST and TSMC
`
`EXHIBIT 1060 by electronic mail, on this 3rd day of August, 2017, on counsel
`
`of record for the Patent Owner as follows:
`
`Neil F. Greenblum
`ngreenblum@gbpatent.com
`
`Michael J. Fink
`mfink@gbpatent.com
`
`Arnold Turk
`aturk@gbpatent.com
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`Dated: August 3, 2017
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`By: /Lauren K. Young/
`Lauren K. Young
`Litigation Legal Assistant
`FINNEGAN, HENDERSON, FARABOW,
`GARRETT & DUNNER, L.L.P.
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`9
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