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`US005539229A
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`{11] Patent Number:
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`[45] Date of Patent:
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`5,539,229
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`Jul. 23, 1996
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`FOREIGN PATENT DOCUMENTS
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`55454767 12/1980
`Japan ................................... .. 257/396
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`3—191574
`Japan ...... ..
`... . . . ... . ..257/384
`8/1991
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`OTHER PUBLICATIONS
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`T. Furukawa et 21]., “Process and Device Simulation of
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`Trench Isolation Comer Parasitic Device”, Proceedings of
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`the Electrochemical Society Meeting, Oct. 9-14, 1988.
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`A. Bryant et al., “The Current—Carrying Comer Inherent to
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`Trench Isolation”, IEEE Electron Device Letters, vol. 14,
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`No. 8, Aug. 1993.
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`D. Foty et al., “Behavior of an NMOS Trench—Iso1ated
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`Comer Parasitic Device at Low Temperature”, Proceedings
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`of the Electrochemical Society Meeting, Oct. 1989.
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`T. Ishijima et al., “A Deep—Submicron Isolation Technology
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`with T—shaped Oxide (TSO) Structure”, Proceedings of the
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`IEDM, 1990, p. 257.
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`Primary Examiner~DonaId L. Monin, Jr.
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`Attorney, Agent, or Fz'rmAJames M. Leas
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`ABSTRACT
`[57]
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`A semiconductor structure comprising at transistor having a
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`gate conductor that has first and second edges bounded by
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`raised isolation structures (e.g. STI). A source diffusion is
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`self-aligned to the third edge and a drain diffusion is
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`self—a1igned to the fourth edge of the gate electrode.
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`19 Claims, 5 Drawing Sheets
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`MOSFET WITH RAISED STI ISOLATION
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`SELF-ALIGNED TO THE GATE STACK
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`Inventors: Wendell P. Noble, Jr, Milton, Vt.;
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`Ashwin K. Ghatalia; Badih El-Kareh,
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`both of Hopewell Junction, N.Y.
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`International Business Machines
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`Corporation, Armonk, N.Y.
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`Assignce:
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`Appl. No.: 365,729
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`Filed:
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`Dec. 28, 1994
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`Int. Cl.“ ........................... H01L 27/08; H0lL 29/76;
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`I-IOlL 29/00
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`257/301; 257/305; 257/397;
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`257/623
`Field of Search
`257/301, 304,
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`257/305, 395, 396, 397, 398, 383, 385,
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`586, 587, 619, 623, 384
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`US. Cl.
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`[75]
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`References Cited
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`U.S. PATENT DOCUMENTS
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`2/1976 Dingwall ............................... .. 257/396
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`8/1987 Joy ct 211.
`. 257/398
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`12/1992 Dash et al. .
`437/67
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`11/1993 Kenney ................................. .. 257/301
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`FIG. 9
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`''/flv?//5V//fl-W%5V///'/I0WA
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`1
`MOSFET WITH RAISED STI ISOLATION
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`SELF-ALIGNED T0 THE GATE STACK
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`FIELD OF THE INVENTION
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`This invention generally relates to semiconductor isola-
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`tion techniques. More particularly,
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`trench isolation (STI) in which the insulating material is
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`raised above the surface of the semiconductor. Even more
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`particularly it relates to an isolation structure for a transistor
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`in a DRAM cell that provides reduced leakage.
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`BACKGROUND OF THE INVENTION
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`Contemporary CMOS technologies employ field effect
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`transistors that are adjacent or bounded by trenches. The
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`trenches are used for shallow trench isolation (STI) or they
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`provide a location for trench capacitors.
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`Parasitic leakage paths have been created by the proxim-
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`ity of a semiconductor device to an edge or corner of either
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`type of trench. In one leakage mechanism, described in a
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`paper, “Process and Device Simulation of Trench Isolation
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`Comer Parasitic Device,” by T. Furukawa and J. A. Man-
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`delman, Proceedings of the Electrochemical Society Meet-
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`ing, Oct. 9—l4, 1988, the parasitic leakage path results from
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`an enhancement of the gate electric field near the trench
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`comer. The electric field is enhanced by the corner’s small
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`radius of curvature and the proximity of the gate conductor.
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`Processing can exacerbate the problem by sharpening the
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`corner and thinning the gate dielectric near the corner. In
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`addition, in a worst case scenario for corner field enhance-
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`This happens when the oxide fill in the isolation trench is
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`recessed below the silicon surface during oxide etches
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`threshold voltage (Vt) than the planar portion of the device.
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`Thus, a parallel path for current conduction is formed.
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`However, for device widths used in contemporaW technolo-
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`gies, the top planar portion of the device carries most of the
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`on-current. Trench corner conduction is a parasitic which
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`usually contributes appreciably only to sub-threshold leak-
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`easily seen as a hump in the subthreshold current curve of a
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`narrow MOSFET.
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`As described in a paper, “The Current-Carrying Comer
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`Inherent to Trench Isolation,” by Andres Bryant, W. Haen-
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`seh, S. Geissler, Jack Mandelman, D. Poindexter, and M.
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`Steger,
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`the corner device can even dominate on-
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`currents in applications such as DRAM that require narrow
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`channel widths to achieve high density. This parallel current-
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`carrying corner device becomes the dominant MOSFET
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`contributor to standby current in low standby power logic
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`applications and to leakage in DRAM cells. Furthermore,
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`there exists concern that the enhanced electric fields due to
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`field crowding at the comer impact dielectric integrity.
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`A paper, “Behavior of an NMOS Trench—Isolated Comer
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`Parasitic Device at Low Temperature,” by D. Foty, J. Man-
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`delman, and T. Furukawa, Proceedings of the Electrochemi-
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`cal Society Meeting, October, 1989, suggests that the corner
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`parasitic device does not improve with decreasing tempera-
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`the comer parasitic device may be more of a problem at low
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`temperature than the planar device.
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`This corner leakage problem has commonly been con-
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`trolled with an increased threshold tailor implant dose, but
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`this can degrade device performance. Thus, alternate
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`schemes for controlling the corner are needed.
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`A paper, “A Deep-Submicron Isolation Technology with
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`T-shaped Oxide (TSO) Structure,” by T. Ishijima et al.,
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`Proceedings of the IEDM, 1990, p. 257, addresses the
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`problem of trench sidewall inversion. This paper teaches the
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`use of a pair of aligned photomasks to form a T-shaped oxide
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`adjacent the corner of an isolation trench and the use of a
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`channel stop boron implant along sidewalls of the trench.
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`sidewall and provides boron to raise the Vt along that
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`alignment tolerances are included in this two-mask-and-
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`implant scheme, making this solution undesirable. While
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`cornmonly assigned copending patent application, “A
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`M. Armacost et al., provides a scheme to protect the corner
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`while not enlarging the isolation, the root problem of corner
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`sharpening and oxide thinning remains. Thus, an improved
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`means to control
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`provided by the following invention.
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`SUMMARY OF THE INVENTION
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`It is therefore an object of the present invention to avoid
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`corner leakage without degrading device performance.
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`It is another object of the present invention to prevent the
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`gate conductor from wrapping around the trench corner.
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`It is another object of this invention to avoid gate dielec-
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`tric thinning adjacent the corner.
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`It is another object of this invention to avoid sharpening
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`It is a further object of the present invention to provide a
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`transistor with an individual segment gate conductor and a
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`spacer rail gate connector formed on a separate wiring level.
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`is a further object of this invention that
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`isolation is self-aligned to the gate conductor.
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`wiring level interconnecting individual gate segments of the
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`minimurn dimension conductive spacer rail.
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`These and other objects of the invention are accomplished
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`by a semiconductor structure comprising a transistor with a
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`thin dielectric. The gate conductor is substantially coexten-
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`surface having opposed first and second edges and opposed
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`third and fourth edges. Raised isolation bounds the first and
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`second edges of the gate conductor. A source is self-aligned
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`to the third edge and a drain is self-aligned to the fourth
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`edge. A conductive wiring level is in contact with the top
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`surface.
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`Another aspect of the invention provides a method of
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`forming an FET comprising the steps of providing a sub-
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`strate having a gate stack comprising a layer of gate dielec-
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`tric and a layer of gate conductor, the gate stack having a top
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`surface; removing first portions of the gate stack and etching
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`a trench in the substrate thereby exposed for raised isolation;
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`depositing insulator and planarizing to the top surface of the
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`gate stack; removing second portions of the gate stack for
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`source/drain regions and to expose sidewalls of the gate
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`stack adjacent the source/drain regions; forming spacers
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`Page 7 of 10
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`4
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`5,539,229
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`3
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`adjacent the exposed sidewalls of the gate stack; and form-
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`ing source/drain diffusions in exposed portions of the
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`source/drain regions.
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`These and other objects, features, and advantages of the
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`invention will become apparent from the drawings and
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`description of the invention.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The foregoing and other objects, features, and advantages
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`of the invention will be apparent from the following detailed
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`description of the invention, as illustrated in the accompa-
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`nying drawings, in which:
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`FIGS. 1-8 are cross sectional views showing the structure
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`at several steps in the process for making a semiconductor
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`structure of a first aspect of the present invention; and
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`FIGS. 9-13 are cross sectional views showing the struc-
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`ture at several steps in the process for making a semicon-
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`ductor structure of a second aspect of the present invention.
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`DETAILED DESCRIPTION‘ OF THE
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`INVENTION
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`The present invention provides a transistor having a gate
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`formed from an individual segment of gate conductor. The
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`gate conductor is confined to the active device area, that is
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`the region having thin gate dielectric. STI is self-aligned to
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`the gate conductor. Gate dielectric and gate conductor are
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`formed as blanket layers on the wafer before the isolation
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`trench is etched, and hence sharpening of the comer and
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`thinning of the gate dielectric are avoided. A conductive
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`wiring level contacts this segment gate, and the wiring level
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`can have a subrninimum dimension as a result of being
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`formed by a directional etch of a conductor along a sidewall.
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`STI and processes for forming STI are described in
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`commonly assigned U.S. Pat. No. 5,173,439, by Dash et al.,
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`incorporated herein by reference.
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`The term “horizontal” as used in this application is
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`defined as a plane parallel to the conventional planar surface
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`of a semiconductor chip or wafer, regardless of the orien-
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`tation the chip is actually held. The term “vertical” refers to
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`a direction perpendicular to the horizontal as defined above.
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`Prepositions, such as “on,” “side,” (as in “sidewall”),
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`“higher,” “lower,” “over,” and “under” are defined with
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`respect to the conventional planar surface being on the top
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`surface of the chip or wafer, regardless of the orientation the
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`chip is actually held.
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`Single crystal semiconducting wafers used in the process
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`steps illustrated in FIGS. 1-13 are formed from materials
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`such as silicon, germanium, and gallium arsenide. Because
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`silicon is most widely used and the most is known about its
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`etch properties, silicon will be used for illustration herein-
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`below. The wafer may have had implants, diffusions, oxi-
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`dations, and other process steps completed before embark-
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`ing on the process sequences described hereinbelow.
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`FIGS. 1—8 show steps in the process of fabricating a
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`transistor or a DRAM cell according to one aspect of the
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`present invention. Referring now to FIG. 1, a “blanket” Vt
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`channel implant is performed on substrate 10 in a region that
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`may encompass an extended portion of the chip or substan-
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`tially the entire chip. If an array of devices is being formed,
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`for example, the region of the blanket implant encompasses
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`substantially the entire area of the array. Then gate stack 12
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`is formed in the same region from a sequence of layers,
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`including gate dielectric 14, gate conductor 16, and gate cap
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`dielectric 18. First, a layer of blanket gate dielectric 14 is
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`Page 8 of 10
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`thermally grown or deposited. Next a layer of gate conductor
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`16 is blanket deposited. Gate conductor 16 is formed of
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`polysilicon. It can be in-situ doped during the deposition or
`it can be implanted after deposition to provide the appro-
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`priate gate doping. Finally, blanket Si3N4 cap 18 is deposited
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`on top of the gate conductor 16 to a thickness suitable for use
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`as a planarization etch stop layer.
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`In the next step, photoresist is applied, exposed, and
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`developed to define areas in which the trenches will be
`formed. The trenches can be STI or storage capacitors. This
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`pattern is first etched in gate cap dielectric 18. The resist may
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`then be stripped, and the pattern in nitride gate cap dielectric
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`18 is used to continue the etch in gate conductor 16 and
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`exposed gate dielectric 14. Finally, the etch is extended into
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`silicon substrate 10 to form raised deep trench 20 for a
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`capacitor, as shown in FIG. 2, or raised shallow trench 30 for
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`STI, as illustrated in FIG. 4. The term “raised trench” refers
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`to the fact that the trench extends beyond the surface of
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`substrate 10 to the top of the gate stack. In this process, a
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`single masking step defines the edge between the trench and
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`gate stack and provides perfect alignment therebetween.
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`Thus, the gate is bounded by a raised trench on two opposite
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`sides. However, since the gate dielectric and gate conductor
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`were formed as blanket layers before the trench was etched,
`there is no comer sharpening, no gate dielectric thinning,
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`and no gate wrap around.
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`As shown in FIG. 3, storage node insulator 22 and storage
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`electrode 24 are formed in raised deep trench 20 as described
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`in commonly assigned U.S. Pat. No. 5,264,716 (“the ’7l6
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`patent”), issued to D. M. Kenney, entitled “Diffused Buried
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`Plate Trench Dram Cell Array,” incorporated herein by
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`reference. In brief, storage node insulator 22 is a formed by
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`growing thermal oxide, depositing silicon nitfide, and oxi-
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`dizing a surface layer of the nitfide. Raised deep trench 20
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`is then filled with doped polysilicon for storage electrode 24
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`of the capacitor. This polysilicon may be recessed to form
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`insulating collar 26. FIG. 3 illustrates the cell at this step in
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`the process.
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`In a similar process to that described above for the raised
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`deep trench, raised shallow trench isolation (raised STI) 30
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`is formed. Referring to FIG. 4, after the photomasking and
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`gate stack etching steps as described above, a silicon etch is
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`used in silicon substrate 10 to form shallow trenches for
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`‘raised STI 30. Then a passivation oxide is thermally grown
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`along surfaces of the silicon thereby exposed. TEOS is then
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`deposited to fill the shallow trenches (and the top of deep
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`trench 20). Next, a planarization step is implemented stop-
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`ping on the nitfide cap of the gate stack. Thus, raised STI is
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`provided adjacent a sidewall of the gate stack. Of course,
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`raised STI 30 can intersect deep trench 20 in a manner
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`similar to that shown for standard STI in the ’716 patent.
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`Next, source/drain regions of the active area are defined
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`using a process similar to that described above for raised
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`deep trench 20 and raised STI 30. Referring to FIG. 5, a
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`cross section orthogonal to the cross section of FIG. 4,
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`photomasking and gate stack etching steps as described
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`above are used to form the desired pattern of gate segments
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`32. This etch leaves polysilicon only over channel region 34,
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`on which there is gate dielectric 14, and defines the channel
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`length of the transistor in the process of being fabricated.
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`Silicon on the two sides of the gate stack thereby exposed
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`will be diffused for the source/drain. The other two sides of
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`the gate stack are bounded by raised storage trench 20 or
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`raised STI 30.
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`In the next step, illustrated in FIG. 6 dielectric sidewall
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`spacers 36 are grown or deposited on the two exposed edges
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`Page 8 of 10
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`5,539,229
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`5
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`of gate stack 32. Spacers 36 are typically formed of a
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`thermally grown oxide along sidewalls of gate conductor 16
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`and a deposited silicon nitride that is directionally etched to
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`remove nitride along horizontal surfaces while leaving
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`nitride spacers along sidewalls. After spacers 36 are formed,
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`source/drain regions 38 of transistor 39 are formed by
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`diffusion or ion implant. The diffusion or implant is self-
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`aligncd to spacers 36 formed along edges of gate stack 32
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`and is bounded by raised STI 30 or raised storage trench 20.
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`The diffusion for source/drain regions 38 may be provided
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`by depositing a doped glass or a doped polysilicon layer. The
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`doped layer is planarized, and may be masked and etched to
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`define the NMOS and PMOS regions. Wafers are then
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`subjected to an activation, drive-in thermal cycle. Diffused
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`regions or the doped polysilicon can be silicided to lower
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`resistance. The use of doped polysilicon as a doping source
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`for source/drain regions 38 provides the advantage of allow-
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`ing the formation of shallow junctions while providing a
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`large volume of material for source/drain regions 38. The
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`shallow junctions reduce short channel effects. The large
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`volume of material allows siliciding without danger of high
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`junction leakage.
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`The next steps provide a node strap, wordline connector,
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`and bitline contact, and these steps are described in copend-
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`ing patent application “A Five Square Folded-Bitline
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`DRAM Cell,” by Wendell Noble, (“the Noble patent appli-
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`cation”) incorporated herein by reference. Briefly, an intrin-
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`sic polysilicon mandrel is deposited and a contact opening
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`formed therein. Heavily doped polysilicon is then deposited
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`forming the strap between node polysilicon and the node
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`diffusion. A selective etch is then used to remove the
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`intrinsic polysilicon, leaving the heavily doped strap.
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`Subminimum dimension wordline interconnect wiring 40
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`is formed as a spacer along sidewall 42 of groove 44 in
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`second intrinsic polysilicon mandrel 46, as illustrated in
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`FIGS. 7 and 8. Alter insulator 48 is deposited and planarized,
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`stopping on cap 18,
`intrinsic polysilicon mandrel 46 is
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`deposited (FIG. 7). Groove 44 in mandrel 46 is formed
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`photolithographically aligned so that sidewall 42 extends
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`over a portion of gate conductor 16. The etch to form groove
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`44 extends through mandrel 46 down to expose nitride cap
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`18 over gate segment. A directional etch removes the portion
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`of nitride cap 18 from gate conductor 16 that is exposed
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`within groove 44. A conductor, such as tungsten, aluminum,
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`or doped polysilicon is deposited and directional etched,
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`leaving subminimum dimension conductive sidewall spacer
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`rail 40 contacting gate conductor 16 along sidewall 42 (FIG.
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`8).
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`FIGS. 9-13 show steps an alternate aspect of the inven-
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`tion in which conductive wiring level 140 interconnects gate
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`segments 132 of transistor 139 that is isolated by raised STI
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`30. Transistor 139 may be part of a logic circuit, SRAM, or
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`other semiconductor circuit. In this aspect of the invention,
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`conductive wiring level 140 is formed before the step
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`illustrated in FIG. 5. Alter the dielectric of raised STI 30 is
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`planarized (FIG. 4), planarization continues, stopping on the
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`surface of gate conductor 116 as shown in FIG. 9. A second
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`layer of conductor for conductive wiring level 140, such as
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`doped polysilicon or tungsten, is then deposited as illus-
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`trated in FIG. 10. Conductive wiring level 140, is formed of
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`a low resistivity material such as a metal or a metal silicide.
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`Metals such as tungsten, molybdenum, titanium, or alumi-
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`num, are suitable. The low resistivity material can be depos-
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`ited by methods known in the art, such as chemical vapor
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`deposition. It can also be formed from heavily doped poly-
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`silicon. A layer of insulator 150 may also then be deposited.
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`The source/drain defining mask is then used as described
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`Page 9 of 10
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`6
`above (FIG. 5) and the two layers of conductor (gate
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`conductor 116 and conductive wiring level 140) are etched
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`such that gate conductor 116 is substantially confined to the
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`active area of each transistor and conductive wiring level
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`140 extends over STI 30 to interconnect transistors or cells,
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`as shown in FIG. 11. Dielectric spacers 152 formed in the
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`next step (FIG. 12), coat both gate segments and conductive
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`wiring level interconnects. While the interconnect wiring in
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`this aspect of the invention is not subminimum dimension,
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`this aspect provides a simpler manufacturing process and
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`still provides the other advantages of the invention described
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`below.
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`In the aspect of the invention illustrated in FIGS. 9-13 a
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`source/drain extension is first formed by implanting a
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`medium dose (less than 1><lO‘4 cm‘2) of a dopant such as
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`arsenic or boron, for source/drain 138 before spacers 152 are
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`formed (FIG. 11). Then, after spacers 152 are formed (FIG.
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`12), intrinsic polysilicon (or intrinsic amorphous silicon) is
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`deposited or selective silicon is growth for raised sourcel
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`drain 154 as shown in FIG. 13. Dopant for the raised
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`source/drain is implanted at low energy so as to avoid
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`damage to the single crystal silicon below. Then the dopant
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`is diffused from the polysilicon to form ultrashallow junc-
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`tions 156 without damage. A refractory metal, such as
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`titanium is then deposited and annealed to form silicide 158
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`in polysilicon raised source/drain 154. Thus, ultrashallow
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`junctions 156 are formed that have both the low resistance
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`associated with a silicide and very low leakage. The junc-
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`tions so formed can have a depth of as little as about 500 A.
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`Of course, other methods of doping the polysilicon of raised
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`source/drain 154 can be used, such as in-situ doping.
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`The device and isolation structure of the invention
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`described hereinabove offers several key advantages. First,
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`STI and storage trench comer parasitic problems are reduced
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`because (1) comer sharpening and gate dielectric thinning
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`are eliminated (since the gate dielectric is formed on a planar
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`surface before device edges are defined); and (2) gating of
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`the sidewall of the channel or its corner by the gate is
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`eliminated since the gate is bounded by raised isolation—thc
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`gate does not wrap around the corner.
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`Second, because polysilicon gate 116 does not extend
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`over field regions under STI 30, field doping under STI 30
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`and STI thickness requirements can be relaxed.
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`Third, as described in the Noble patent application, layout
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`distance between individual device gates can be substan-
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`tially reduced when the wordline conductor interconnecting
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`gate segments is a subminimum dimension spacer rail. In the
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`DRAM cell described in the Noble application, for example,
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`savings in DRAM cell area of up to 37.5% is achieved.
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`While several embodiments of the invention,
`together
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`with modifications thereof, have been described in detail
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`herein and illustrated in the accompanying drawings, it will
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`be evident that various further modifications are possible
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`without departing from the scope of the invention. For
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`example, a wide range of materials can be used for mandrel
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`46, and for rail 40 or conductive wiring level 140. The
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`invention can be practiced with n- or p—channel transistors
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`with corresponding changes in the doping of the polysilicon
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`strap and node polysilicon. Nothing in the above specifica-
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`tion is intended to limit the invention more narrowly than the
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`appended claims. The examples given are intended only to
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`be illustrative rather than exclusive.
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`What is claimed is:
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`1. A semiconductor structure, comprising
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`a transistor having a gate, said gate comprising a thin
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`dielectric and an individual segment of gate conductor,
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