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`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
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`A Trench Isolation Process for BiCMOS Circuits
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`Stephen Poon and Craig Lage
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`Advanced Products Fiesearch and Development Laboratory, Motorola Inc.,
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`3501 Ed Bluestein Blvd., Austin, Texas 78721
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`ABSTRACT
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`A new isolation process using 1 pm deep trench is
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`developed for BiCMOS circuits. Well behaved
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`MOSFETs and NPN devices with excellent parasitic
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`performance were achieved. Low leakage diodes with
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`butted junctions were demonstrated by inclusion of an
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`oxidation barrier in the trench liner and utilizing a Ge02
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`doped oxide with matched thermal coefficient of
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`expansion to the silicon substrate for trench fill.
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`Planarity for arbitrary width isolation was obtained by
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`using oxide FtlE followed by chemical-mechanical
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`polishing.
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`INTRODUCTION
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`Trench isolation has been reported since the early
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`1980's as a replacement for LOCOS isolation for VLSI.
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`However, process complexity associated with french
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`technology has restricted its appeal to a limited number
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`of circuit applications while continuous modifications
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`and improvements to LOCOS has enabled its
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`implementation in a proposed 16 Mbit fast SRAM cell
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`with 1 pm active pitch [1]. Nevertheless, LOCOS is not
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`expected to scale significantly beyond 1 pm pitch due
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`to its intrinsic limitations such as field oxide thinning,
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`bird's beak encroachment,
`lack of planarity, and
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`punchthrough. As a result, trench isolation is required
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`to meet the demands of ULSI. However, a relatively
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`simple process with sufficient benefits must be
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`developed to gain wide acceptance.
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`In this paper, a single isolation process utilizing a 1
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`pm deep trench with arbitrary width is proposed for
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`BiCMOS circuits to avoid the complexity of shallow and
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`deep trench isolation typically employed in high
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`performance BiCMOS technology [2]. A schematic
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`representation of the structure is shown in Figure 1.
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`Latchup immunity,
`intrawell and interwell isolations,
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`reduced parameter capacitance, as well as bipolar
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`parasitic reduction are simultaneously satisfied with the
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`proposed structure. The processing technique used
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`to fabricate this structure and the electrical results
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`achieved are described.
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`FABRICATION
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`The process platform was adopted from a 0.5 pm
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`BiCMOS technology developed for 4 Mbit fast SRAMs
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`[3]. Epi thickness is optimized to ensure up—diffusion
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`from the buried layers to merge with the trench bottom
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`to obtain the desired isolation and parasitic
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`characteristics. A hard mask is used to protect the
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`active regions for etching of a 1 pm depth trench into
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`the substrate. Both thermal oxide and composite
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`thermal oxide/deposited nitride trench liners were
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`evaluated along with several chemical vapor deposited
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`oxides to determine the most suitable combination of
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`CH3315-9/93/0000(0045)$1.00 © 1993 IEEE
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`processes to minimize defect generation in the
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`substrate and to minimize seam or void formation in
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`narrow width trenches.
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`A combination of oxide RIE and chemical
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`mechanical polishing process [4,5] is used for the
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`planarization of arbitrary width trench. A schematic
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`cross section of the planarization process sequence is
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`shown in Figure 2. Compared to [4], this planarization
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`sequence has a reduced number of process steps and
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`has replaced the more complex planarization etchback
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`process with an oxide RlE process. At this point, M08
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`and bipolar devices were fabricated using previously
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`reported processes [3] to evaluate the merit of the
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`proposed structure.
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`RESULTS AND DISCUSSION
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`Transistor characteristics were measured on both
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`CMOS and non-self—aligned NPN devices. Typical 0.5
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`pm Wdrawn subthreshold characteristics are shown in
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`Figure 3. Both n- and p- channel devices exhibit ideal
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`behavior with no degradation of the subthreshold
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`slope. A Gummel plot for 0.8 um emitter NPN is shown
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`in Figure 4.
`Functional BiCMOS and ECL ring
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`oscillators were also achieved.
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`Field punchthrough voltage on intrawell and
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`interwell isolation structures are shown in Figure 5.
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`Flesults measured on trench isolated structures were
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`independent of field width and are well above 10 volts.
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`Holding voltage for latchup and parasitic bipolar gain
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`are improved compared to a PBL isolation control
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`because current path in the substrate is interrupted by
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`the trench bottom reaching into up-diffusion from the
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`buried layer. These results are shown in Figures 6 and
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`7. respectively. A SEM micrograph which illustrates this
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`is shown in Figure 8.
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`Deposited oxides are typically known to create
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`voids and weak seams in narrow width and high aspect
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`ratio trenches after wet strips/cleans due to poor step
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`coverage. However, this problem is improved with
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`ozone enhanced depositions
`[6,7] and ECR
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`deposited films. Leakage current measured between
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`gate poly combs in an on-pitch array for two different
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`oxide trench fill is shown in Figure 9. A TEM cross
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`section micrograph showing planar and defect-free
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`isolation trench is shown in Figure 10.
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`in order to alleviate stress induced leakage caused
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`by substrate defects due to oxidation and other
`thermal processes in 1 pm deep oxide filled trench,
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`composite thermal oxide/CVD nitride trench liner [8,9]
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`and trench fill with matched thermal coefficient
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`expansion to the substrate [6] were evaluated. Stress
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`Page 1 0f 4
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`TSMC Exhibit 1048
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 4
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`TSMC Exhibit 1048
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

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`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
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`[6] J. Bell, 8. Fisher, K. Maeda, and S. Poon,
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`'Characterization of Germanium Doping in
`
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`TEOS/Ozone Films for Trench Fill Applications',
`Schumacher Dielectrics and CVD Metallization
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`Symp. Proceedings, February,1993.
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`[7] J.P. West, H.W. Fry, and S. Poon, 'The Application
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`of APCVD/Ozone Thin Films in S 0.5 pm lC
`Fabrication: Trench and Inter-metal Isolation and
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`Gap Fill', SPIE International Symposium on
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`Microelectronic Processing, September, 1993.
`
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`[8] CW. Teng, C. Slawinski, and W.R. Hunter, 'Defect
`Generation in Trench isolation“,
`lEDM Technical
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`Digest, pp. 586 ~ 589, 1984.
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`[9] SR. Stiffler, J.B. Lasky, C.W. Koburger, and W.S.
`
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`Berry,
`'Oxidation-lnduced Defect Generation in
`Advanced DRAM Structures', lEEE Trans. Electron
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`Devices, vol. 37, no. 5, pp. 1253 - 1258, 1990.
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`[1] JD. Hayden, M.P. Woo, R.C. Taft, P. Pelley, B.-Y.
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`Nguyen, C. Mazure, P.U. Kenkare, K. Kemp, R.
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`Subrahmanyan, A.R. Sitaram, J-H. Lin, J. K0, C.
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`King, C. Gunderson, and H.C. Kirsch,
`'A High-
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`
`Performance Quadruple Well, Quadruple Poly
`
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`
`
`BiCMOS Process for Fast 16Mb SRAMs',
`IEDM
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`Technical Digest, pp. 819 - 822, 1992.
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`[2] G.G. Shahidi, J. Warnock, B. Davari, B. Wu, Y. Taur,
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`C. Wong, CL. Chen, M. Rodriguez, D.D. Tang, K.
`Jenkins, P.A. McFarland, R. Schulz, D. Zicherman,
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`P. Coane, D. Klaus, J.Y.C. Sun, M. Polcari, and TH.
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`
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`
`
`Ning,
`'A High Performance BiCMOS Technology
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`Using 0.25 pm CMOS and Double Poly 47 GHz
`
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`Bipolar', VLSl Tech. Symp. Digest, pp. 28 - 29,
`1992.
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`[3] TC Mele, J. Hayden, F. Walczyk, M. Lien, Y.C.
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`See, D. Denning, S. Cosentino, and AH. Perera, 'A
`
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`High Performance 0.5 pm BiCMOS Triple
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`
`Polysilicon Technology for 4Mb Fast SRAMs', IEDM
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`Technical Digest, pp. 481 - 484, 1990.
`
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`[4] B. Davari, C.W. Koburger, R. Schulz, J.D. Warnock,
`T. Furukawa, M. Jost, Y. Taur, W.G. Schwittek, J.K.
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`DeBrosse, M.L. Kerbaugh, and J.L. Mauer, 'A New
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`Planarization Technique, Using a Combination of
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`RIE and Chemical Mechanical Polish (CMP)‘ lEDM
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`Technical Digest, pp. 61 — 64, 1989.
`[5] S. Poon, A. Gelatos, A.H. Perera, and M. Hoffman,
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`'A Manufacturable Chemical-Mechanical Polish
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`
`
`Technology with a Novel Low-Permittivity Stop—
`
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`
`Layer for Oxide Polishing', VLSl Tech. Symp.
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`Digest, pp. 115 - 116, 1993.
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`measurement obtained on oxide trench fill film doped
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`with Ge02 is shown in Figure 11. Leakage measured
`on butted diodes with and without nitride liner are
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`compared in Figure 12.
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`Gate oxide thinning at the trench corner which can
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`degrade intrinsic dielectric breakdown was avoided by
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`careful optimization of the process module. The
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`results are shown in Figure 14.
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`SUMMARY
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`A simple trench isolation process that can
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`simultaneously satisfy several
`requirements for
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`submicron BiCMOS circuits
`is proposed and
`described. Well-behaved devices with excellent
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`isolation and parasitic characteristics are demonstrated.
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`ACKNOWLEDGEMENTS
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`The authors wish to thank Phil Tobin, Asanga
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`Perera, Fred Walczyk, David Burnett, Hsing Tseng,
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`Jeff Lutze, and Jerry Sebek for technical discussions
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`and measurements. Process support from Jung-Hui
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`Lin, Kent Cooper, and the pilot
`line personnel of
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`APRDL. Vendor support
`from Mel Hoffman of
`Westech, Jeff Bell of QTl, Todd Curtis of Watkins-
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`Johnson, and the ECR process engineering team of
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`Lam Research are sincerely appreciated. Rick Sivan
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`and Lou Parrillo are acknowledged for their managerial
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`support.
`
`REFERENCES
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`
`46
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`Page 2 of 4
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`

`

`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
`
`Nitride/Pad Oxide
`l
`I Deposited Oxide l
`
`I
`
`—
`
`Reverse Density
`Photoresist
`
`Oxide RIE
`
`CMP
`
`Fig. 2 Planarization Process Sequence
`
`1E-3
`
`1E-5
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`1E-7
`
`1E—9
`
`1E-1 1
`
`,/
`
`0
`
`-0.3
`
`-0.6
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`-O.9
`
`-1.2
`
`-1.5
`
`VE (V)
`
`Fig. 4 Bipolar Characteristics
`
` (Holding
`
`Voltage
`< 2 V)
`
`Fig. 6 Latch-Up Characteristics
`
`47
`
`PMOS
`
`NMOS
`
`BIPOLAR
`
`Oxide Filed Trench
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`Deep M
`
`P SUBSTRATE
`
`Fig. 1 Trench Isolated BiCMOS Architecture
`
`|D(A)
`
`'
`1E-11
`
`E
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`SLOPE =
`35.3 mV/dec
`
`1E-
`
`13 83.9 mV/dec
`-1.8
`-0.9
`
`‘ y
`0
`VG (V)
`Fig. 3 M08 Subthreshold Characteristics
`
`|VD|=0.1,5 V
`0.9
`1.8
`
`INTERWELL
`
`INTRAWELL
`fig.
`.
`a.
`
`
`
` 3
`
`..u Fo‘ 1.8
`
`VpgncgthroughLV)_#m0:~4Oto
`
`.8
`
`.63 1
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`1
`i
`2
`Field Space (pun)
`Field Space (pmfi
`Fig. 5 Field Punchihrougi Voltage
`
`3
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`Page 3 of 4
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`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
`
`
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`Ozone oxide
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`“IL-nu“
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`I“ I
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`0
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`03a:
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`Percent
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`Percent
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`II‘I‘I‘.“
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`“um
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`“‘““w
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`13““
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`‘2‘.“‘I‘II‘
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`Fig. 9 Leakage between Gale Poly Combs
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`1E-2
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`0
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`0.3
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`Trench
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`0.6
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`vs (V)
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`0.9
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`1.2
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`1.5
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`Fig. 7 Parasitic PNP Bipolar Gain
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`Fig. 13 Gate Oxide Breakdown (Perim. = 78 cm)
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`-
`.e-12-10
`12.10.13
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`Log Current
`Log Current
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`Fig. 12 N+ Junction Leakage (Perim.= 40 cm)
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`80
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`Optlmlzed Proces
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`ungfgtmelgd
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`TEM micrograph showing planar and detect tree trench
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`Stress(MPa)
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`NitrideLiner
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`NoNitride Liner
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`___-__.___—__.—_.__.__.____—.__
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`Percent e.o
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`I.““““_““““
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`m1-
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`0309121
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`Vonage (Vi
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`0369121510
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`Vonage (V)
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`nu.““-L‘“u
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`—‘—‘_‘--‘1—_“‘
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`4:.o
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`Percent g
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`8001000
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`200
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`400
`000
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`Temperature (“0)
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`Fig. 11 ln-situ Stress vs. Temp
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`Page 4 of 4
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