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`United States Patent
`4,855,247
`[11] Patent Number:
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`Ma et a1.
`[45] Date of Patent:
`Aug. 8, 1989
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`119]
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`[54] PROCESS FOR FABRICATING
`SELF-ALIGNED SILICIDE LIGHTLY DOPED
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`DRAIN MOS DEVICES
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`_
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`Inventors: Di Ma, Syosset; David H. Hoffman,
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`Hauppauge, both of N.Y_
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`[75]
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`Microsystems Corporation,
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`prpauge’ N-Y'
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`[21] APPI- N0-= 291,541
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`[22] Flled:
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`Dec. 29, 1988
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`Related 115- Application Data
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`Division of Ser. No. 145,390, Jan. 19, 1988.
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`[62]
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`[51]
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`Int. Cl.4 ................. .. H01L 21/265; HOIL 21/44;
`H01L 21/48
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`[52] US. Cl. ...................................... 437/44; 437/200;
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`437/202; 437/41; 437/931; 156/643; 156/653;
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`357/233; 148/DIG. 147; l48/DIG. 105
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`[58] F‘eld‘gggggchlrsgé/
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`’
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`’
`’
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`23.4, 23.9, 23.11; 156/643, 650, 651, 652, 653;
`l48/DIG. 131, DIG. 147, DIG. 105
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`[56]
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`References cued
`U.S. PATENT DOCUMENTS
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`437/200
`3/1986 Peterson ..........
`4,577,392
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`437/200
`,,,,,,..
`4,587,718 5/1986 Haken et a1,
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`437/200
`4,593,454 6/1986 Baudrant et a1.
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`..-.u 4347/“
`4,599.789 7/1986 Gamer ----.---.-.-
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`.... 437/200
`4,622,735 11/1986 Shibata ................
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`437/200
`4’657’628 4/1987 H°n°way at al- "
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`'''”
`$23k itjl'
`''''‘
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`437/41
`4:735:62“) 4/1988 Yen
`’
`
`
`
`
`
`..... 437/41
`. ....... ..
`5/1988 Hu et a1.
`4,744,859
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`..
`437/200
`4,746,219 ' 5/1988 Holloway et a1.
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`4,788,160 11/1988 Havetnann et a1. ................... 437/44
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`FOREIGN PATENT DOCUMENTS
`............ 437/200
`0091775 10/1983 European Pat. Off.
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`0157024 12/1981 Japan ................................... 437/200
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`0111706 6/1984 Japan ................................... 437/200
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`0200418 11/1984r Japan .
`0128659 7/1985 Japan ................................... 437/200
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`...................................
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`5/1986 Japan .
`0097975
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`5/1986 Japan .
`0101075
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`0144069 7/1986 Japan .
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`0214474 9/1986 Japan .
`0258447 11/1986 Japan ................................... .. 437/44
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`0287227 12/1986 Japan ........................... 437/200
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`9/1986 World Int. Prop. 0. ..
`8605321
`437/200
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`8700967
`2/1987 World Int. Prop. 0. .......... 437/200
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`OTHER PUBLICATIONS
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`Wang, “Lithographically Defined Self-Aligned Dou-
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`
`
`ble-Implanted Doped FET Device”, IBM Technical
`
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`
`
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`
`
`Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp.
`
`4629—4631.
`Primary Examiner_01ik Chaudhuri
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`
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`Assistant Examiner—M. Wilczewski
`
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`
`Attorney, Agent, or Firm—Hopgood, Calimafde, Kalil,
`B1austein & Jud1owe
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`
`
`ABSTRACT
`[57]
`In a method for fabricating an MOS structure, in accor-
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`dance with one embodiment, a layer of material that
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`serves as an etching stop during the side wall spacer
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`etch, is inserted between the silicon substrate and the
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`S}de wall Spacer-_ 11} another enxbodlment 0f the men-
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`tion, after establishing differential layer thicknesses on
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`the source/drain surface, the side wall spacer is com-
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`pletely removed and light and heavy ion implantation
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`steps are performed sequentially with one single lithe-
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`graphic step. In a further embodiment of the invention,
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`after the self-aligned silicide is formed, the side wall
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`spacer is removedéfind ligfht ant:lheavy ion implantation
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`Steps are sequentl Y Per “me -
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`12 Claims, 2 Drawing Sheets
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`34
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`Page 1 “8
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`TSMC Exhibit 1038
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 8
`
`TSMC Exhibit 1038
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

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`US. Patent
`
`Aug. 8, 1989
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`Sheet 1 of2
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`4,855,247
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`41L,
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`Page 2 of 8
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`US. Patent
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`Aug. 8, 1989
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`Sheet 2 of2
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`4,855,247
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`Page 3 0f 8
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`Page 3 of 8
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`1
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`4,855,247
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`PROCESS FOR FABRICATING SELF-ALIGNED
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`SILICIDE LIGHTLY DOPED DRAIN MOS
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`DEVICES
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`5
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`This is a divisional of Ser. No. 145,390, filed Jan. 19,
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`1988.
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`10
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`15
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`25
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`3O
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`2
`effect on the electrical characteristics of the device.
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`This is a particular concern from the reliability stand-
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`point since the longer the drain-to-source voltage is
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`applied, the more charges are trapped.
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`This phenomenon can be alleviated by using a lightly,
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`doped drain (LDD) structure in which a lightly doped
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`region is inserted between the channel and the heavily
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`doped source/drain regions. The lightly doped region
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`has the effect of reducing the peak electric field in the
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`channel region, thereby alleviating the hot carrier injec-
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`tion problem. One common way of implementing an
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`LDD structure requires the formation of a side wall
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`spacer, and hence is called a SWS-LDD (side wall
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`spacer lightly doped drain) structure.
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`The construction of the SWS-LDD device requires
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`the formation of a side wall spacer that is adjacent to the
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`polysilicon gate. This side wall spacer is formed be-
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`tween two ion implantation steps; the first is a light
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`implant, the second is a heavy implant to define the
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`lightly and heavily doped regions, respectively. When
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`the SWS-LDD structure is implemented in CMOS
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`(complementary MOS) technology, two lithographic
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`steps are required for each dopant polarity, one for each
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`' of the implants. For the non-LDD structure, only one
`such lithographic step is required since only one implant
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`is needed.
`As a result of the junction integrity problem de-
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`scribed above, it has been proposed that the junctions be
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`formed after silicidation, so that the impurities are im-
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`planted into or through the silicide. During the subse-
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`quent heat treatment, impurities in the silicide diffuse
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`into the silicon to form the junctions. In addition, it is
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`desirable to combine the self-aligned silicide feature
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`with the LDD structure for advanced MOS device
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`imple-
`applications. When a self-aligned silicide is
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`mented with an SWS-LDD structure on a CMOS de-
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`vice, one additional lithographic step is required for
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`each dopant polarity to fabricate the device.
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`In summary, the following three problems or disad-
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`vantages are recognized with regard to the fabrication
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`of self-aligned silicide and lightly doped drain MOS
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`structures:
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`(1) in the implementation of a self-aligned silicide
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`structure, the side wall spacer etching has to be criti-
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`cally controlled;
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`(2) in the implementation of an SWS-LDD structure
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`in CMOS, an additional lithographic step is required;
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`LDD structure in which the junctions are formed after
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`metal deposition or silicide formation, an additional
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`lithographic step is required.
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`SUMMARY OF THE INVENTION
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`It is a general object of the present invention to pro-
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`vide an improved process for fabricating MOS devices
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`having reduced dimensions in which one or more of the
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`aforesaid problems are alleviated or eliminated.
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`It is also an object of the invention to provide a pro-
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`cess for fabricating a self-aligned silicide MOS structure
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`in which far greater processing latitude in side wall
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`spacer etching is allowed.
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`It is another object of the invention to provide a
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`process for fabricating a CMOS structure with a side
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`wall spacer and lightly doped drain (SWS-LDD) fea-
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`tures, which requires only one lithographic step for
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`each source/drain dopant polarity.
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`BACKGROUND OF THE INVENTION
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`1. Field Of The Invention
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`This invention relates generally to the fabrication of
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`metal-silicon dioxide semiconductor (MOS) devices,
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`and more particularly to the fabrication of self-aligned
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`silicide and lightly doped drain MOS device structures.
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`2. Description Of The Related Art
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`Recent developments in MOS fabrication techniques
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`have produced MOS devices in which ever-decreasing
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`device dimensions are realized in order to achieve
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`greater device density and increased Operating speeds.
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`This decrease in MOS device dimensions has, however,
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`created a concern over the high sheet resistance in the
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`source/drain regions and hot carrier injection.
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`That is, as device dimensions continue to decrease,
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`the junction depths of the source/drain regions are
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`reduced so as to minimize parasitic effects. One direct
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`result of this reduction in the source/drain junction
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`depth is an increase of the sheet resistance of the sour-
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`ce/drain regions. Another result of decreasing device
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`dimensions bears on the junction integrity when a metal
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`layer is applied to make a contact to the source/drain
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`regions. The shallower the junction, the more difficult it
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`is to reduce the leakage current of the source/drain
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`regions to the substrate.
`In order to reduce the sheet resistance of the source/-
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`drain regions, a device structure has been developed,
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`known as a self-aligned silicide structure, in which a
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`metal silicide film is formed at the source/drain regions
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`as well as at the polysilicon gate. In a conventional
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`method for fabricating a self-aligned silicide structure, a
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`silicon dioxide side wall spacer is formed before the
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`source/drain and polysilicon regions are silicided. In
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`this conventional process the side wall spacer etch has
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`to clear the source/drain regions that are not intended
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`to be covered by the side wall spacer so that these re-
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`gions can be silicided. However, since the junctions are
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`already formed, any significant etch into the silicon of
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`the source/drain regions will reduce the junction depth.
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`This is compounded by the fact that during the silicide
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`formation,
`the top silicon layer of the source/drain
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`regions is consumed by the silicide, thus further reduc-
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`ing the junction depth. As a result, in order to success-
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`fully fabricate a self-aligned silicide MOS device by the
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`conventional fabrication process, all the silicon dioxide
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`in the desired silicon region must be cleared without
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`etching significantly into the junctions.
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`The performance of MOS integrated circuits is also
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`enhanced by decreasing the separation between the
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`source and drain of an MOS transistor, also known as
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`the effective channel
`length. However,
`the applied
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`drain-to-source voltage is kept at a constant level irre-
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`spective of reductions in channel length which results in
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`a higher electric field being established across the chan-
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`nel region. This elevated electric field has the ability to
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`inject the carriers (electrons or holes) in the channel
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`region across the silicon and silicon dioxide interface
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`and to trap the carriers in the oxide. Since the silicon
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`dioxide layer forms the gate insulator of the MOS de-
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`vice, the trapped charges in the gate oxide have an
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`35
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`Page 4 of 8
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`4,855,247
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`3
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`It is a further object of the invention to provide a
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`process for fabricating a CMOS self-aligned silicide
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`lightly doped drain structure in which the silicide is
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`formed or the metal
`is deposited which eventually
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`forms silicide before the junction formation with one
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`lithographic step for each source/drain dopant polarity.
`In one embodiment of the invention, a layer of mate-
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`rial is grown or deposited before the deposition of the
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`side wall spacer material. The material of this layer has
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`a different etching characteristic than that of the side
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`wall spacer material and the silicon substrate. During
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`the subsequent side wall spacer etch,
`this material
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`serves as an etching stop. A second and different etch
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`that has a substantially lower etch rate of the silicon
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`substrate and side wall spacer material is then applied to
`remove the material in areas not covered by the side
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`wall spacer.
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`In a second embodiment of the invention, a polysili-
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`con gate is defined and a first layer is grown before the
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`deposition of the side wall spacer material. The material
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`of the first layer has a different etching characteristic
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`than that of the silicon substrate and side wall Spacer
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`material. During the subsequent side wall spacer etch,
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`this material serves as an etching stop. A second and
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`different etch that has a substantially lower etch rate of
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`the silicon substrate and side wall spacer material is then
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`applied to remove the first layer of material in areas not
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`covered by the side wall spacer. A second layer of
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`material is grown over the exposed silicon substrate to
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`a thickness whose ion implantation stopping power is
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`less than that of the first layer. The side wall spacer is
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`then removed, and two sequential ion irnplantations of
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`the same polarity are performed after a lithographic
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`step to define the regions that are to receive such im-
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`plants. These two implants define, respectively,
`the
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`lightly and heavily doped regions.
`In a third embodiment of the invention, after a
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`polysilicon gate is defined, a first layer of material is
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`deposited before the deposition of the side wall spacer
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`material. This first layer of material has a different etch-
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`ing characteristic than that of the silicon substrate and
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`side wall spacer material. During the subsequent side
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`wall spacer etch, this material serves as an etching stop.
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`A second and different etch that has a substantially
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`lower etch rate of the silicon substrate and side wall
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`spacer material is applied to remove this material in the
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`area not covered by the side wall spacer. Silicide is
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`formed selectively over the silicon and polysilicon re-
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`gions and the side wall spacer is etched away. For cer-
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`tain silicides that cannot withstand this etching environ-
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`ment, a layer of a second material may be selectively
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`grown or deposited over the silicide but not on the side
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`wall spacer. In addition, this second material has a dif-
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`ferent etching characteristic than that of the side wall
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`spacer material. During the etching to remove the side
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`wall spacer, this second material serves as an etching
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`stop to protect the formed silicide layer. A lithographic '
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`step is performed to define the proper regions, and two
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`sequential ion implants of the same dopant polarity are
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`applied to form the lightly and heavily doped regions,
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`respectively.
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`To the accomplishment of the above and such further
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`objects as may hereinafter appear, the present inventi n
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`relates to an improved process for fabricating M S
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`devices substantially as defined in the appended claims
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`and as described in the following specification as con-
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`sidered with the accompanying drawings in which:
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`10
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`4
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. 1(a)-1(2) are cross sections of a self-aligned
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`silicide MOS device at various stages in its fabrication in
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`accordance with a first embodiment of the invention;
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`FIGS. 2(a)—2(c) are cross sections of an SWS-LDD
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`MOS device at various stages of its fabrication in accor-
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`dance with a second embodiment of the invention; and
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`FIGS. 3(a)—3(c) are cross sections of a self-aligned
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`silicide LDD MOS device at various stages of its fabri-
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`cation in accordance with a third embodiment of the
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`invention.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`Referring to the figures, there is shown in FIG. 1(a)
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`a self-aligned silicide MOS integrated circuit in an early
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`stage of its fabrication in accordance with one embodi-
`ment of the invention. As therein shown, a silicon diox-
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`ide film 12 is grown over the upper surface of a silicon
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`substrate 10. As is per se conventional, a polysilicon
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`gate 14 is defined over the film 12 and source/drain
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`regions 16 are formed in the substrate 10 such as by
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`diffusion or ion implantation. The silicon dioxide film 12
`sandwiched between the substrate 10 and polysilicon
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`gate 14 is to serve, in a known manner, as the gate insu-
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`lation of the completed MOS device.
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`A layer of silicon dioxide 20 is then grown over the
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`exposed surface of the substrate 10 and over the
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`polysilicon gate 14; Although in FIG. 1(a) only a con-
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`ventional singly implanted/diffused junction is shown,
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`the method of the invention can be applied as well to
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`other types of junctions. The silicon dioxide layer 20
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`may be either thermally grown or deposited by a chemi-
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`cal vapor deposition (CVD) method. The thickness of
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`the silicon dioxide layer 20 is such that it does not con-
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`sume too much polysilicon and the silicon substrate if it
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`is thermally grown, but thick enough to be a good etch
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`stop for the subsequent side wall spacer etch. If the
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`silicon dioxide layer 20 is deposited by a CVD method,
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`there is no concern for polysilicon and silicon consump-
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`tion. A thickness of the silicon dioxide layer 20 between
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`150 A and 2000 A is sufficient for this purpose.
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`A layer of silicon nitride 23 is subsequently deposited
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`by a CVD method, which later in the process forms the
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`side wall spacer. The thickness of the silicon nitride
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`layer 23 is determined by the desired width of the side
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`wall spacer, which also depends on other factors such as
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`the angle of the polysilicon side wall profile and the
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`thickness of polysilicon. A thickness of silicon nitride
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`layer 23 of 1000A or greater is needed for practical
`applications.
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`Subsequent to the silicon nitride deposition, as shown
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`in FIG. 1(b), a directional silicon nitride etch is per-
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`formed to form the silicon nitride side wall spacer 24.
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`This is done preferably in a plasma etcher or in a reac-
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`tive ion etcher. The etching process should have a suffi-
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`ciently high silicon nitride etch rate and a sufficiently
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`low oxide etch rate (good silicon nitride-to-silicon diox-
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`ide selectivity). The etch should stop when the silicon
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`nitride in the planar surface is completely removed.
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`Such an etch could be accomplished in a planar
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`plasma etcher with a two-step etch technique. The first
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`step has the following conditions: pressure: 325 mtorr;
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`power: 175 watt; with a gas flow of 10 sccm of argon
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`and 60 sccm of sulfur hexafluoride (SFa) The second
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`step consists of: pressure: 325 mtorr; power: 100 watt;
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`5
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`gas flow: 6 seem of argon, 30 sccm of SF5 and 5 sccm of
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`chlorodifluoromethane (CHCle)
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`A silic0n dioxide etch is then performed. This etch
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`should have a very high silicon dioxide—to-silicon and
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`silicon dioxide-to-silicon nitride selectivity such as can 5
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`be achieved by the use of wet buffered hydrofluoric
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`acid. The etch, as shown in FIG. 1(e), completely re-
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`moves the silicon dioxide 20 over the polysilicon gate
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`14 as well as over the source/drain regions 16 that are
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`not covered by the silicon nitride side wall spacer 24. 10
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`As shown in FIG. 1(e), a portion 22 of the silicon diox-
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`ide layer covered by the silicon nitride side wall spacer
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`(24) remains after the etch.
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`A silicide forming metal 25 such as titanium (al-
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`though other metals such as tungsten and cobalt can 15
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`also be used) is then deposited by conventional means
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`over the structure of FIG. 1(a) to produce the structure
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`shown in FIG. 1(a). The metal is then thermally reacted
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`with the silicon underlying the metal layer 25, and a
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`selective etch that removes the unreacted metal but
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`removes little reacted silicide is applied. In the final
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`structure shown in FIG. 1(e) a silicide layer 26 is formed
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`over the polysilicon gate 14 and the source/drain re-
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`gions 16 that are not covered by the silicon nitride side
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`wall spacer 24.
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`In the process illustrated in FIGS. 1(a) to 1(e), as
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`compared to the conventional self-aligned silicide pro-
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`cess, an additional silicon dioxide layer 20 is grown and
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`a silicon nitride rather than a silicon dioxide side wall
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`spacer is used. During the side wall spacer etch, in the
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`conventional process, one has to optimize the silicon
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`dioxide-to-silicon etch selectivity and uniformity as
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`well as the deposited silicon dioxide uniformity. In the
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`process of FIG. 1, due to the presence of the additional
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`silicon dioxide layer, being a material of different etch-
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`ing characteristics than the silicon and the silicon nitride
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`that forms the side wall spacer, selectivity and unifor-
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`mity can be independently controlled. Although rea-
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`sonable silicon nitride-to-silicon dioxide etch selectivity
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`should be maintained, which is a commonly known
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`technique in silicon device fabrication, there is greater
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`latitude in the silicon nitride side wall spacer etching
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`process, since one has only to concentrate mainly on the
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`uniformity of the etch. As long as sufficient silicon
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`dioxide is grown in the first place, the silicon nitride-to-
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`silicon dioxide selectivity is not as important since the
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`silicon dioxide layer eventually is removed. This is true,
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`in particular, since this subsequent silicon dioxide etch
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`can be made to have very high silicon dioxide-to-silicon
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`selectivity by the application of such chemicals as buff- 50'
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`ered hydrofluoric acid.
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`In the present invention, as in the embodiment of
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`FIGS. 1(a) to 1(e), the amount of top layer of silicon
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`removed in the source/drain junction area is deter-
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`mined by the thermally grown silicon dioxide layer 20, 55
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`which can be very accurately controlled. The growing
`of the silicon oxide has the additional benefit of driving
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`in the source/drain junction. If the silicon dioxide layer
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`20 is deposited by a CVD method, no such silicon loss
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`is encountered. On the other hand, the silicon layer
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`removed in the conventional process is determined by
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`the side wall spacer etch which has to be compromised
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`with respect to the uniformity of the silicon dioxide
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`deposited and the uniformity of the side wall spacer
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`etch. As a result, it is not as easily controlled.
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`The method of the invention illustrated in FIG. 2
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`may be used to fabricate a CMOS SWS-LDD structure
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`with one lithographic step for each source/drain dopant
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`20
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`25
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`30
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`35
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`45
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`65
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`4,855,247
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`’
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`6
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`polarity. The objective in this method is to create two
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`different layer thicknesses over the source/drain re-
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`gions before they receive the implants. The process
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`sequence is identical to the first method illustrated in
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`FIG. 1 up to the side wall spacer formation except that
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`in the method of FIG. 2, the source/drain dopants are
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`not introduced before the side wall spacer formation.
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`The MOS device in an early stage of its fabrication in
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`accordance with the method of FIG. 2 is illustrated in
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`FIG. 2(a) As therein shown, a layer of insulating mate-
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`rial 12, such as silicon dioxide, is formed on a silicon
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`substrate 10 and separates the substrate 10 and a
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`polysilicon gate 14. The silicon dioxide layer 20 and the
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`silicon nitride side wall spacer 24 are formed as in the
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`first method.
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`A silicon dioxide etch that has a high selectivity over
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`silicon nitride is then performed, preferably with a
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`plasma etching or reactive ion etching technique be-
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`cause of their superior etch rate control. The etch re-
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`moves part of the silicon dioxide that is not protected by
`the silicon nitride to leave a silicon dioxide layer 28
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`having a reduced thickness between 100 A and 1800 A,
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`as shown in FIG. 2(b). Alternatively, the silicon dioxide
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`that is not covered by the silicon nitride can be com-
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`pletely removed by a wet chemical such as a buffered
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`hydrofluoric acid etching technique. Subsequently, a
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`thin layer of silicon dioxide may be regrown to a thick-
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`ness between 100 A and 1800 A to produce the same
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`structure as in FIG. 2(b). The first layer of material
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`deposited before the side wall spacer deposition and the
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`regrown layer need not be the same material.
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`Between the etch back and the regrown methods, the
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`latter approach is preferable since the thickness of the
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`silicon dioxide 28 not covered by the silicon nitride side
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`wall spacer can be more precisely controlled. As a re-
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`sult of this step, another layer of silicon dioxide 30 is
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`formed on top of polysilicon gate 14. At this stage of the
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`process, as shown in FIG. 2(b), two different thick-
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`nesses of silicon dioxide are present over the source/-
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`drain regions that are to be formed. One silicon dioxide
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`layer is under the silicon nitride side wall spacer 24
`whose thickness is the same as silicon dioxide layer 20 in
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`FIG. 2(a) and is determined by the initial growth/depo:
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`sition conditions. The other silic0n dioxide layer 28 is
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`not covered by the silicon nitride side wall spacer. Sili-
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`con dioxide layer 28 should be thinner than layer 22 and
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`its thickness is controlled by either the etching process
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`or the regrowth process described above.
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`The wafer is then subjected to a silicon nitride etch
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`that completely removes the silicon nitride side wall
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`spacer. This can be accomplished in hot phosphoric
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`acid etch or a plasma etch. A lithographic step is per-
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`formed (not shown in the figure) to define the proper
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`regions to receive the subsequent implants, and two
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`separate, sequential source/drain ion implants are then
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`performed. After a thermal anneal of the implant, the
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`device structure is in the form shown in FIG. 2(c). One
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`of the ion implants is a light implant to dope both the
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`lightly doped region 32 and heavily doped region 34.
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`The other ion implant is a heavy implant to define pri-
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`marily the heavily doped region 34. The implant condi-
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`tions are optimized to utilize the different silicon diox-
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`ide thicknesses over the source/drain regions. This
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`selection can be accomplished by using two different
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`species of the same polarity (such as arsenic and phos-
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`phorus for the n-type dopant) that have significantly
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`different penetration depths (projected ranges). It can
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`also be accomplished by using the same species but with
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`Page 6 of 8
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`5
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`15
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`7
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`different implant energies resulting in different penetra-
`tion depths.
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`The actual implant conditions are su