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`United States Patent
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`Gasner
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`[19]
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`[11]
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`[45]
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`Patent Number:
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`Date of Patent:
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`4,599,789
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`Jul. 15, 1986
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`4,453,306
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`........................ .. 29/571
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`6/1984 Lynch et a1.
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`OTHER PUBLICATIONS
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`“Fabrication of High-Performance LDDFET’s with
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`Oxide Sidewall—Spacer Technology”; Tsang et al.;
`
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`
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`IEEE; vol. ED-29, No. 4, Apr. 1982, pp. 590—596.
`
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`
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`“An Optimally Designed Process for Submicrometer
`
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`
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`MOSFET’s”; Shibata et a1.; IEEE, vol. ED—29, No. 4,
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`Apr. 1982, pp. 531—535.
`
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`“Twin—Tub CMOS—A Technology for VLSI Cir—
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`
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`cuits"; Parrillo et al.; IEDM, 1980, pp. 752-755.
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`“Twin—Tub CMOS II—-—An Advanced VLSI Technol.
`
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`
`
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`ogy”; Parrillo et al.; IEDM 1982, pp. 706—709.
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`“Quadruple—Wall CMOS—A VLSI Technology”;
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`Chen; IEDM 1982, pp. 791-792.
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`Primary Examiner—Upendra Roy
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`Attorney, Agent, or Firm—Barnes & Thornburg
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`ABSTRACT
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`[57]
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`CMOS devices are formed in self-aligned wells in a
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`substrate produced by a two mask, one photolitho-
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`graphic step process wherein the first mask is used as a
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`template to form the second inverse mask of substan-
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`tially equal thickness. The gates are used as alignment
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`mask for shallow source and drain regions and subse-
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`quently formed lateral gate spacers are used as align-
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`ment mask for deep source and drain regions. Exposed
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`source and drain regions and silicon gates have silicide
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`formed thereon by a non-selective process.
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`14 Claims, ‘20 Drawing Figures
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`[54] PROCESS OF MAKING TWIN WELL VLSI
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`CMOS
`'
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`Inventor:
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`John T. Gasner, Melbourne, Fla.
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`[75]
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`[56]
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`[73] Assignee: Harris Corporation, Melbourne, Fla.
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`[21] Appl. No.: 620,835
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`[22] Filed:
`Jun. 15, 1984
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`[51]
`Int. Cl.4 .................... .. H01L 21/265; BOIJ 17/00
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`[52] US. c1. .................................. .. 29/571; 29/576 B;
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`148/15; 148/187; 156/643; 357/42; 357/91
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`[58] Field of Search ................. .. 148/15, 187; 29/571,
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`29/576 B; 156/643; 357/91, 42
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`References Cited
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`U.S. PATENT DOCUMENTS
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`9/1973 Wang ................................ .. 148/188
`3,759,763
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`......... ..
`4,209,350 6/1980 Ho et al.
`.. 148/188
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`7/1981 Egawa et a1.
`4,280,272
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`29/571
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`3/1982 Lund et a1.
`. . ..
`. . . .. 29/571
`4,319,395
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`..
`4,333,099
`6/1982 Tanguay et a1.
`357/67
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`.
`4,343,082
`8/1982 Lepselter et a1.
`. 29/576 B
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`4,356,040 10/1982 Fu et a1.
`.......... ..
`148/l.5
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`29/571
`4,356,623 11/1982 Hunter ..............
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`. . . .. .. .. .
`4,366,613
`1/1983 Ogura et al.
`. .. .. 29/571
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`4,385,947
`5/1983 Halfacre et a1.
`.. 148/187
`.... ..
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`4,411,058 10/1983 Chen .................
`29/571
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`4,420,344 12/1983 Davies
`148/15
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`4,434,543 3/ 1984 Schwabe et a1
`. 29/576 B
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`4,435,896
`3/1984 Parrillo et al.
`29/571
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`4/1984 Haken ............. ..
`4,442,591
`29/571
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`4,444,605 4/ 1984 Slawinski
`.......................... .. 148/187
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`Page 1 of 11
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`TSMC Exhibit 1037
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`TSMC v. IP Bridge
`IPR2016-01246
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`Page 1 of 11
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`TSMC Exhibit 1037
`TSMC v. IP Bridge
`IPR2016-01246
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`20 F176
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`-U.S. Patent
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`PROCESS OF MAKING TWIN WELL VLSI CMOS
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`4,599,789
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`BACKGROUND AND SUMMARY OF THE
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`INVENTION
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`The present invention relates generally to integrated
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`circuits and method of manufacturing and more specifi-
`cally to a method of manufacturing self-aligned junction
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`isolated complementary insulated gate field effect tran-
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`sistors.
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`The industry is constantly working toward increasing
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`the device density on a wafer or chip. The number of
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`devices that can be placed on a chip is limited by the
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`size of the device and the electrical interaction. These
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`place restraints on the spacing between devices. Further
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`limitation are in the processing steps dealing with pho-
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`tolithography and the ability to form doped regions of
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`the controllable size and impurity concentration. For
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`junction isolated insulated gate field effect transistors,
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`the design must minimize device latch-up resulting from
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`parasitic bipolar devices. It is also desirable to reduce
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`the capacitance of the device as well as the contact and
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`interconnect system. Hot electron and the substrate
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`current injection is another problem which must be
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`faced for insulated gate field effect transistors as well as
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`reducing the resistance of the contacts and junctions.
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`Although all of these problems have been addressed
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`singly by the prior art,
`the industry is continuously
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`searching for complete process flows which address as
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`many of these problems as possible. Thus, it is an object
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`of the present invention to address as many of the de-
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`sign restraints as possible while increasing the density of
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`the devices on a chip.
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`Another object of the present invention is to provide
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`a process flow with a minimum number of masking
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`Still another object of the present invention is to
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`provide a unique process for forming a reverse image
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`mask.
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`Yet another object of the present invention is to mini-
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`mize latch-up.
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`A further object of the present invention is to provide
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`‘ a process which allowstailoring of the threshold of the
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`devices.
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`An even further object of the present invention is to
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`inhibit hot electron and substrate current injection.
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`A still even further object of the present invention is
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`to provide a reduced resistance of junction in contacts.
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`Another object of the present invention is to lower
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`the overall capacitance of the integrated circuit.
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`These and other objects of the invention are attained
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`by forming a first mask on a substrate of a first conduc-
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`tivity type and introduction of second conductivity
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`type impurities to form a second conductivity type well.
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`This is followed by a second mask which is the reversed
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`image of the first mask and introduction of a first con-
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`ductivity type impurities to form a first conductivity
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`processes. It is preferred that the second mask edges be
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`self-aligned to the first mask. A gate insulative layer and
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`gate materials are formed on the two well areas. This is
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`followed by forming shallow source and drain regions
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`using the gate as a mask in each of the wells. Next,
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`insulative spacers are formed extending laterally from
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`the first and second gates over the source and drain
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`regions and impurities are introduced to form deeper
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`source and drain regions using the gate and the spacers
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`contacts to the respective layers. The gate material is
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`polycrystalline silicon and the impurity introduction
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`steps are carried out by ion implantation. A metal sili-
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`cide step is performed to reduce the contact resistance
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`by forming metal silicide over the source and drain
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`regions as well as the gate. Insulative inserts are formed
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`between the device regions by etching and filling by
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`deposition to form planar oxide inserts separating the
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`A method of forming self-aligned well regions includ-
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`ing the inverse image masking step includes forming the
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`the first well region. The inverse mask is formed by
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`applying a second mask layer overfilling the openings in
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`the first mask and covering the first mask. The second
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`mask layer is removed sufficiently to expose at least a
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`layer and any first mask layer superimposed thereon is
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`selectively removed to iorm the second mask having the
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`introducing the impurities of the opposite conductivity
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`type to form a second well.
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`Other objects, advantages and novel features of the
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`present invention will become apparent from the fol-
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`lowing detailed description of the invention when con-
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. 1—3 illustrate a portion of the process incorpo-
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`rating the principles of the present invention.
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`FIGS. 4—6 illustrate a first method of forming an
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`invention.
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`FIGS. 7 and 8 illustrate a second method of forming
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`an inverse mask according to the principles of the pres-
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`ent invention.
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`FIGS. 9—16 illustrate the remainder of the process
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`incorporating the principles of the present invention.
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`FIGS. 17—20 illustrate of a modification of the pro-
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`cess of FIGS. 10—13.
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`DETAILED DESCRIPTION OF TH
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`DRAWINGS
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`The process of fabrication begins as illustrated in
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`FIG. 1 with a substrate 20 which for purposes of exam-
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`impurity concentration in the range of 1015 atoms per
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`cubic centimeter. The substrate 20 may be an original
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`substrate or may be an epitaxial layer formed on another
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`eral dielectric isolation regions. This results in mesa
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`An insulative layer, for example silicon dioxide 22, is
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`formed on the silicon substrate 20 and a photoresist
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`layer 24 is formed on the oxide layer 22. The photoresist
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`layer is then patterned by the well—known technique to
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`form openings and act as a mask. The photoresist layer
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`24, the oxide layer 22 and the substrate 20 are then
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`etched to form trenches 26. The etchant may be a wet
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`etch or a dry etch. When using the wet etch, the angle
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`the walls form with respect
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`that
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`should be between 60° and 90°. The steeper walls are
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`preferred since it creates devices with effectively wider
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`channels.
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`The photoresist layer 24 and oxide layer 22 are re-
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`moved immediately after etching the trenches. Then the
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`Page 8 of 11
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`3
`entire surface is thermally oxidized to form a thin oxide
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`region 28. An insulative material, for example oxide, is
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`then chemically vapor deposited to back fill
`the
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`trenches 26. The excess chemical vapor deposited oxide
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`are then removed in a planarization process to provide
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`inserts 30 planar with the top of the substrate 20. The
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`inserts 30 have, for example, a depth of 5000 Angstroms
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`from the surface. The substrate 20 is then oxidized to
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`provide a thin oxide coating 32. The resulting structure
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`is illustrated in FIG. 2. The inserts 30 may be formed by
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`other processes and it
`is preferred that an insulator
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`insert be used to provide lateral dielectric isolation.
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`The next sequence of steps produce self-aligned twin
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`wells in which the field effect transistor devices are to
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`be formed. This process involves using a first mask and
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`then forming a second mask which is the inverse image
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`of a first mask. A first masking material 34, for example
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`a photoresist or a polyimide, is formed on the surface of
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`the substrate 20. An opening 36 is formed in the mask 34
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`to expose the areas in which the P-wells are to be
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`formed. A P-type impurity, for example boron, is ion
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`implanted at sufficient energy level and dose to form the
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`P— well 38 illustrated in FIG. 3 having an impurity
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`concentration greater or equal to 1016 atoms per cubic
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`centimeter and a depth of, for example, 15,000 Ang-
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`stroms in mesa areas and 5000 Angstroms in oxide filled
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`areas. The photoresist layer 34 generally has a thickness
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`in the range of 10,000 to 20,000 Angstroms. Additional
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`boron implants can optionally be done at this time, using
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`different doses and energies, to create a tailored impu-
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`rity doping concentration for the P— for device re-
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`.
`quirements.
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`The formation of the second mask includes applying
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`a metal layer 40 which fills the previous opening 36 in
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`the first mask layer 34. The metal layer 40 is then plana-
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`rized by applying a planarization layer 42 which may
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`be, for example a photoresist or polyimide layer. By
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`way of example, the metal layer 40 which may be alumi-
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`num, is formed to have a thickness of 10,000 to 20,000
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`Angstroms on the surface of the first masking layer 34
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`and the planarization layer 42 has a thickness above the
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`planar part of the metal layer in the range of 10,000 to
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`20,000 Angstroms. The resulting structure is illustrated
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`in FIG. 4. The planarization process includes etching
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`the planarization layer 42 and the metal layer 40 at
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`appropriate rates such that the resulting metal layer 40
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`is planar with the top of the first mask layer 34 as illus—
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`trated in FIG. 5. This may be accomplished by reactive
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`ion etching using the appropriate gas and energy level
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`to accomplish planarization. Planarization techniques
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`are well known in the prior art and thus will not be
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`described herein in detail. The first mask layer 34 is then
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`selectively removed by an appropriate wet or dry etch-
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`ant. This results in a mask layer 40 of metal which is the
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`inverse image of the original mask layer 34 as illustrated
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`in FIG. 6.
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`An alternative method of forming the second mask
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`layer which is the inverse of the first mask layer in-
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`cludes forming the second mask layer or metal layer 40
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`to a sufficient depth to fill the opening 36 in the first
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`mask layer 34 as illustrated in FIG. 7. For a first mask
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`layer 34 having a thickness of 10,000 to 20,000 Ang-
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`stroms,
`the second masking layer 40 would have a
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`thickness on the first mask layer 34 of 10,000 to 20,000
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`Angstroms. The metal layer 40 is then etched using
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`either wet or dry etch until a portion of the first mask
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`layer 34 is exposed. Since only a single layer is being
`etched, the etch rate is uniform and the corners of the
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`5
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`4,599,789
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`4
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`opening 36 will become exposed because of the topol—
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`ogy of the metal layer 40. As illustrated in FIG. 8, edge
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`44 of mask layer 34 is exposed and partially etched. A
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`first mask layer 34 is then selectively removed using a
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`wet etchant which not only removes the first mask layer
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`34, but also removes the portions of the metal layer 40
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`which are superimposed thereon. This lift—off technique
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`results in the same mask layer 40 of FIG. 6 having in-
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`verse image of the mask layer 34 of FIG. 3.
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`Since the alternative inverse mask forming process
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`does not attempt to form a planar surface before etch—
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`ings, the deposited second layer may be substantially
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`thinner with a pronounced indenture. This reduces the
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`time and cost of applying and etching the second mask
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`layer.
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`Although two techniques are described for forming
`an inverse mask, other methods may be used to form the
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`second mask. As will be described below, the edges of
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`the mask openings should be aligned so as to form self-
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`aligned wells with little if any overlap. Any dual photo-
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`lithic techniques requires lateral spacing because of the
`tolerances of the lithographic processes to assure no
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`overlap of the formed regions. Similarly, prior single
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`lithographic techniques could not truly form inverse
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`mask, and, thus, lateral spacing or guard rings were also
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`required.
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`N-type impurities, for example phosphorous, are then
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`introduced for example, by ion implantation to form the
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`N~ well 46. The N— well which is aligned with the
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`previously formed P-well 38 has an impurity concentra-
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`tion of equal to or greater than 1016 atoms per cubic
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`centimeter and a depth of 15,000 Angstroms. The sec-
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`ond mask layer 40 is removed and the substrate is an=
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`nealed. The resulting structure is illustrated in FIG. 9.
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`The self-aligned dual well 38 and 46 remove the need
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`for separate guard rings. Thus, removing additional
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`steps to form the guard rings. It should be noted that by
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`using ion implantation to form the wells, very little side
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`diffusion occurs and therefore the spacing between the
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`devices may be reduced. Similarly, very high peak dop-
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`ing results which reduces the latch-up problem by form-
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`ing high threshold parasitic field effect transistors. The
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`resulting well’s surface doping also results in relatively
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`low junction capacitance.
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`Complementary insulated gate field effect transistors
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`are formed by forming a gate oxide layer 48 on the
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`surface of the substrate by, for example, exposing the
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`substrate to an oxidizing atmosphere followed by the
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`application of a gate material and delineation to form
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`gate regions 50 and 52. In the preferred embodiment,
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`the gates 50 and 52 are made from polycrystalline sili-
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`con. A first type P impurity, for example boron, is ion
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`implanted non-selectively using the gates 50 and 52 and
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`the oxide inserts 30 as a mask to produce shallow re-
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`gions 56 in well 38 and shallow regions 54 in well 46 as
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`illustrated in FIG. 10.
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`A mask is formed by applying photoresist layer 58
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`and delineating to mask the N— well region 46 and
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`expose the P—- well region 38. N-type impurities, for
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`example arsenic, are implanted using the mask 58 and
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`the gate 50 in combinationwith oxide inserts 30 to form
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`shallow N+ source and drain regions 60. The ion im-
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`plantation is carried out at a sufficient level to overcome
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`the original P+ regions 56 in well 38. The initial intro-
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`duction of P+ impurities into the P — well 38 allows for
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`greater range for the formation of the N+ source and
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`drain regions 60. The resulting structure is illustrated in
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`FIG. 11. The mask layer 58 is removed. The structure at
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`Page 9 of 11
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`5
`this point has shallow source and drain regions formed
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`in each of the complementary field effect transistor
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`wells having a depth in the range of 1000 to 2000 Ang-
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`stroms and an impurity concentration in the range of
`
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`1018 to 1019 atoms per cubic centimeter.
`
`
`The next sequence of operation form the deep source
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`and drain region portions. This process begins with the
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`formation of spacers extending laterally from the gate
`regions 50 and 52. These spacers are formed by deposit-
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`ing an insulative layer, for example chemical vapor
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`deposition of silicon dioxide over the surface of the
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`substrate. The oxide layer is then reactive ion etched to
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`form the spacer regions 62 extending from gate 50 and
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`spacers 64 extending from gate 52. These spacers result
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`from the uneven topology of the deposited silicon oxide
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`layer. This process is well known in the prior art and,
`
`
`
`
`
`
`
`
`
`
`
`thus, is not described in detail.
`
`
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`
`
`After formation of the spacers, a masking layer 66 is
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`applied over the substrate and delineated to mask N—
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`well region 46 and exposed P— well region 38. N+
`
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`impurities, for example phosphorous, are ion implanted
`
`
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`
`using the mask layers 66, the gate 50 and the spacers 62
`
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`as well as inserts 30 as a mask. This results in deep N+
`
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`source and drain regions 68 extending laterally from the
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`shallow N+ source and drain regions 60 as illustrated in
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`
`FIG. 12. The masking layer 66 is removed and a new
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`masking layer 70 is applied and delineated to expose
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`well 46 and mask well 38. P-type impurities, for exam-
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`ple boron, are ion implanted using the mask layer 70, the
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`gate 52, spacers 64 and the oxide inserts 30 as alignment
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`mask. This results in the deep P+ source and drain
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`regions 72 extending laterally from the shallow source
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`and drain regions 54 as illustrated in FIG. 13 having a
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`depth in the range of 3000 to 4000 Angstroms and an
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`impurity concentration in the range of 1018 to 1020
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`atoms per cubic centimeter. The photoresist layer 70 is
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`removed. This completes the device formation steps.
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`It is evident from FIG. 13 that the polycrystalline
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`gates 50 and 52 are of a lower resistance and are doped
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`as N+ and P+ respectively having an impurity con-
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`centration in the range of 1018 to 1020 atoms per cubic
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`centimeter.
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`The formation of the field oxide and the contacts is
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`the final processing sequence. In order to reduce the
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`junction resistance and provide barrier metal for shal-
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`low junctions, a silicide forming metal layer 74 is ap—
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`plied to the substrate as illustrated in FIG. 14. This layer
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`may be, for example platinum. The wafer is then heated
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`to cause platinum silicide to form in those regions where
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`the platinum contacts the polycrystalline silicon gate or
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`the silicon substrate. As illustrated in FIG. 15, this in-
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`cludes the platinum silicide regions 76 on deep source
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`and drain regions 68, region 78 on gate 50, regions 80 on
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`deep source and drain regions 72 and region 82 on gate
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`52. No platinum silicide is formed over the oxide inserts
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`30 or the spacers 62 and 64. The portions of the plati-
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`num which should not form platinum silicide is easily
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`selectively removed using, for example, hot concen-
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`trated Aqua Regia.
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`The use of the oxide spacers inhibit hot electron and
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`substrate current injection as well as providing better
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`gate oxide reliability. Used in combination with the
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`metal forming silicides, a self-alignment technique for
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`the silicide formation without a mask results. The spac-
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`ers also smooth out the sharp edges of the gate material
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`for better contact metal coverage.
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`A field oxide layer 84 is then formed over the wafer
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`by chemical vapor deposition for example and vias are
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`Page 10 0f 11
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`6
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`etched to provide contacts to the platinum silicide por-
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`tion of the source and drain regions and the gate re-
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`gions. A layer of contact metal is then applied and delin-
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`eated to form contacts 86. The resulting structure is
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`illustrated in FIG. 16. An insulative layer may be pro-
`vided over the first metal layer 86 and a second layer of
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`metal provided.
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`An alternative method for forming the shallow and
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`deep source and drain regions includes, as illustrated in
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`FIG. 17, forming the masking layer 58 blocking the N——
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`well region 46 and exposing the P— well region 38. The
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`N+ arsenic implant
`is performed to form shallow
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`source and drain regions 60. The photoresist layer 58 is
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`removed and a photoresist layer 88 is applied and delin-,
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`eated to form a mask layer blocking the P~ well region
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`38 and exposing the N— well region 46. P+ type impu-
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`rities are implanted to form the P+ source and drain
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`regions 54. The masking layer 88 is removed and a
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`non-selective P-type boron implant is performed form—
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`ing deep P+ source and drain regions 72 and P+
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`source and drain regions 90 in wells 46 and 38 respec-
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`tively. A masking layer 66 is applied and delineated to
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`expose the P— well region 38 and block the N— well
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`region 46. N-type impurities, for example phosphorous,
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`are implanted to form the deep N+ source and drain
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`regions 68. This implantation must be carried out at
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`sufficient power levels to overcome the P+ regions 90
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`originally formed in the prior step. The resulting struc-
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`ture is illustrated in FIG. 20. The mask layer 66 is re-
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`moved and the process is continued as previously de-
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`scribed for FIGS. 14-16.
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`The process of FIGS. 17—20 are substantially similar
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`to the process steps of FIGS. 10—13 in that three mask-
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`ing steps are used for four implantations to form the two
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`part source and drain regions for complementary insu-
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`lated gate field effect transistors. This results since one
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`of the implantation or doping step is performed non-
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`selectively. The difference is, in FIGS. 10—13, the non-
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`selective implantation is at the beginning of the process,
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`whereas in the process of FIGS. 17—20, the non-selec-
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`tive implantation is in the middle of the process. As can
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`be noted, the implantation of the P and N source and
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`drain regions have been reversed in the two process
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`flows. Since all the impurity introduction is by low
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`temperature ion implantation, it is not critical that the N
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`implantation precede the P implantation. The impor-
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`tance of the sequence of steps is that the shallow source
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`and drain regions are formed using the gate as the align-
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`ment mask and that the deeper regions are formed using
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`the spacer as the alignment mask.
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`From the preceding description of the preferred em.
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`bodiments, it is evident that the objects of the invention
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`are attained, and although the invention has been de-
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`scribed and illustrated in detail, it is to be clearly under-
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`stood that the same is by way of illustration and exam-
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`ple only and is not to be taken by way of limitation. The
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`spirit and scope of the invention are to be limited only
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`by the terms of the appended claims.
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`What is claimed is:
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`1. A method for forming complementary insulated
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`gate field effect transistors comprising:
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`forming at least one insulative insert in a substrate of
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`a first conductivity type to form at least a first and
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`second mesas in said surface separated laterally by
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`said insert;
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`forming a first mask layer having a first opening on
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`said substrate;
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`5
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`15
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`55
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`60
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`65
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`Page 10 of 11
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`‘7
`introducing second conductivity type impurities op-
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`po