USOOS445996A
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,445,996
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`Aug. 29, 1995
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`4,735,679 4/1988 Laske .................................... 437/62
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`4,879,258 11/1989 Fisher ....... ..
`.437/225
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`3/1990 Cote et a1.
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`4,940,507
`7/1990 Harbarger . .. .. .
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`5,036,015 7/ 1991 Sandhu et a1.
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`5,064,683 11/ 1991 Poon et a1.
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`1/1992 Malik ....................... 437/225
`5,078,801
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`1/1992 Neuadic et a1.
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`5,084,071
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`5,110,428
`5/1992 Prigge et a1.
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`437/195
`5,166,096 11/1992 Cote et a1. ......
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`8/1993 Otsu . .. . . .. .. ..
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`5,262,346 11/1993 Bindal et a1.
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`5,272,117 12/1993 Roth et al.
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`FOREIGN PATENT DOCUMENTS
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`0272531Al 6/ 1988 European Pat. Off.
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`0403287A2 12/1990 European Pat. Off.
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`63-266830 11/1988 Japan .
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`Primmy Examiner—011k Chaudhuri
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`Assistant Examiner—H. Jey Tsai
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`Attorney, Agent, or Firm—Finnegan, Henderson,
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`Farabow, Garrett & Dunner
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`ABSTRACT
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`[57]
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`To planarize an insulating film formed on a semiconduc-
`tor substrate, a polishing slurry containing cerium oxide
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`is used to polish the surface of the insulating film. Using
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`the cerium oxide included slurry as a polishing agent,
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`the insulating film is not contaminated by alkali metals
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`during the polishing process. Furthermore, the insulat-
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`ing film is polished at an enhanced polishing rate.
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`1 Claim, 41 Drawing Sheets
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`United States Patent
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`Kodera et a1.
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`[19]
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`[54]
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`[75]
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`METHOD FOR PLANARIZING A
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`SEMICONDUCTOR DEVICE HAVING A
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`AMORPHOUS LAYER
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`Inventors: Masako Kodera, Kawasaki, Japan;
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`Hiroyuki Yano, Wappingers Falls,
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`N.Y.; Atsushi Shigeta, Yamato,
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`Japan; Riichirou Aoki, Tokyo, Japan;
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`Hiromi Yajima, Yokohama, Japan;
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`Haruo Okano, Tokyo, Japan
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`[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
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`Japan
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`[21] Appl. No.: 66,375
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`[22] Filed:
`May 25, 1993
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`Foreign Application Priority Data
`[30]
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`‘ May 26, 1992 [JP]
`Japan ................................ .. 4-132978
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`Japan
`Sep. 25, 1992 [JP]
`4-256889
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`Oct. 20, 1992 [JP]
`4-281194
`Japan
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`Nov. 30, 1992 [JP]
`4.319175
`Japan
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`Dec. 11, 1992 [JP]
`Japan ................................ .. 4—331945
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`Int. Cl.6 ................. .. H01L 21/302; H01L 21/463
`[51]
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`[52] US. Cl. .................................. .. 437/225; 437/ 101;
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`437/966; 437/235
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`[58] Field of Search .............. .. 156/636; 437/228, 966,
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`437/960, 225, 101, 637
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`[56]
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`References Cited
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`U.S. PATENT DOCUMENTS
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`3,715,842 2/1973 Tredinnick et al.
`.................. 51/303
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`6/1987 Beyer et a1.
`4,671,851
`......................... 156/645
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`1..“ 33A
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`“M\\‘
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`233A
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`201
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`235
`L
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`Page 1 of 64
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`TSMC Exhibit 1035
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`TSMC v. IP Bridge
`IPR2016-01246
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`TSMC Exhibit 1035
`TSMC v. IP Bridge
`IPR2016-01246
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`US. Patent
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`5,445,996
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`m.“
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`PRIOR ART _ i
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`Aug. 29, 1995
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`5,445,996
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`(Pm)
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`90
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`60
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`POLISHING TIME
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`4
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`PRIOR ART
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`DISTANCE
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`RAISED
`PORTION
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`Sheet 4 of 41
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`5,445,996
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`PRIOR ART
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`PRIOR ART
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`US. Patent
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`Aug. 29, 1995
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`5,445,996
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`{.5
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`PORTION
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`DISTANCE(mm
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`60
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`420
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`POLISHING TlME
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`FIG.
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`PRIOR ART
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`FIG.
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`FIG.
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`5,445,996
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`ART
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`FIG.IOB
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`FIG.IOA
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`FIG. 20A
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`Fifi“ Vt“?
`207
`FIG. 21E m.‘)5‘r‘b‘;}r‘ 202
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`Sheet 17 of 41
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`RMSED
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`PORTION
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`___—_r—————__———\
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`REéESSED
`
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`PORTION
`
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`20
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`DISTANCE(#m)
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`
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`so
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`Page 18 0f 64
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`60
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`{20
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`POLISHING TIME (sec)
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`90
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`150
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`F.
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`I
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`(5.
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`2323
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`Page 18 of 64
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`Sheet 18 of 41
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`RECESSED
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`PORTI 0N
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`
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`
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`POLISHING TIME (sec.)
`
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`FIG. 23
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`0
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`US. Patent
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`POLISHING TIME (560.)
`
`120
`
`
`
`
`
`FIG. 24
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`Page 20 0f 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 20 of 41
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`DISTANCE(pm)
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`
`(sec)
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`F I G.
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`25
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`Page 21 0f 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 21 of 41
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`
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`POLISHING TIME (sec.)
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`FIG.
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`'26
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`Page 22 0f 64
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`US. Patent
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`Aug. 29, 1995 '
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`Sheet 22 of 41
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`.\
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`POLISHING TIME (566.)
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`
`
`
`
`
`FIG. 27
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`Page 23 0f 64
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`Page 23 of 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 23 of 41
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`217
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`FIG.
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`
`28
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`Page 24 0f 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 24 of 41
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`Page 25 0f 64
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`US. Patent
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`Aug. 29, 1995‘
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`Sheet 25 of 41
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`Page 26 0f 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 26 of 41
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`manual;
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`iii-3.51:-?
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`233
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`Page 27 0f 64
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`US. Patent
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`W 203
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`Inn” 202
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`3 3 A
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`III/Illlllllllllllllla 244
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`mm 203
`"um 202
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`FIG.
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`33B
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`FIG. 33F
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`Page 28 0f 64
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`mm
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`31201
`1
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`F I G. 34A
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`FIG.
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`Ifzzfl EZZZZflm E?“
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`F | G. 34E
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`Page 29 0f 64
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`Sheet 29 of 41
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`iOOrpm
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`LOAD 40Kgf
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` ARITHMETIC
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`FIG. 35
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`Page 30 0f 64
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`CURRENT THROUGH MOTOR (AI
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`aegifigmovwo
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`Imin.)
`
`
`160
`
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`owe-two,“
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`02'
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`POLISHING RATE (pm/min.)
`
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`«rev.
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`00
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`Page 31 0f 64
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`FIG.36
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`POLISHINGTIME
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`Page 31 of 64
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`Sheet 31 of 41
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`MOTOR}.
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`(A)
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`CURRENTTHROUGH
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`‘13. N (0
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`POLISHING RATE (pm/min)
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`Page 32 0f 64
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`Sheet 32 of 41
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`0.8
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`9 m
`
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`.0 A
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`
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`
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`
`
`FRICTION BETWEEN TURNTABEL AND
`
`
`
`TO-BE‘POLISHED LAYER (N)
`
`
`
`FIG. 38
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`Page 33 0f 64
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`POLISHINGRATE(Pm/min)
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`Page 33 of 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 33 of 41
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`5,445,996
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`0.8
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`
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`
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`
`
`
`
`
`
`
`NUMBER OF ROTATION OF TURNTABLE AND
`
`
`
`HOLDING DEVICE
`(rpm)
`
`
`
`
`F | G. 39
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`Page 34 0f 64
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`Page 34 of 64
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`Sheet 34 of 41
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`5,445,996
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`FIG.
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`
`41
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`Page 35 0f 64
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`Page 35 of 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 35 of 41
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`5,445,996
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`—
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` 201
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`CONTROLLER
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`
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`
`518
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`
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`501
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`
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`wnnnnnnnn 601, 602
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`Page 36 0f 64
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`Page 36 of 64
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`US. Patent
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`Aug. 29, 1995'
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`Sheet 36 of 41
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`5,445,996
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`
`
`
`
`CONTROLLER 6II
`
`
`
` SETTING OF
`
`
`
`POLISHING
`
`CONDHWONS
`0F F/Fo
`
`
`
`
`
`CALCULATING
`
`
`
`
`
` RE-SETTING
`
`
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`POUSHING
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`CONDHWONS
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`
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`
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`FIG. 45
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`Page 37 0f 64
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`Page 37 of 64
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`

`

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`US. Patent
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`
`
`Aug. 29, 1995
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`Sheet 37 of 41
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`5,445,996
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`
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`
`
`(A)
`
`
`
`CURRENTTHROUGHDRIVINGMOTOR
`
`
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`5000
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`OOOO
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`POLISHING RATE (ii/min)
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`Page 38 0f 64
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`FIG.46
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`Page 38 of 64
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`US. Patent
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`Aug. 29, 1995
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`
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`Sheet 38 of 41
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`5,445,996
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`
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`
`
`POLISHING AMOUNT(
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`
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`A)
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`0
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`POLISHING RATE (A /min)
`
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`coco—
`
`Page390f64
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`
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`t.»6.“.
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`Page 39 of 64
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`US. Patent
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`Aug. 29, 1995'
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`Sheet 39 of 41
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`5,445,996
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`CURRENT THROUGH DRIVING MOTOR (3)
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`POLISHING RATE (IS/min)
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`Page 40 0f 64
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`FIG.48
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`TIMEOFUSINGOFPOLISHINGCLOTH(min)
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`Page 40 of 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 40 of 41
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`5,445,996
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`502
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`FIG. 50
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`Page 41 0f 64
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`503
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`Page 41 of 64
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`US. Patent
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`Aug. 29, 1995
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`Sheet 41 of 41
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`5,445,996
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`OLISHING RATE (ii/min)
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`Page 42 0f 64
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`oil!)
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`Page 42 of 64
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`5,445,996
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`1
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`METHOD FOR PLANARIZING A
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`SEMICONDUCTOR DEVICE HAVING A
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`AMORPHOUS LAYER
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`This invention relates to a polishing apparatus and a
`method for planarizing a layer on a semiconductor wa—
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`fer.
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`2. Description of the Related Art
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`Conventionally, colloidal silica is popularly used as a
`polishing slurry for polishing and planarizing the sur-
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`face of insulating films or the like in the process of
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`manufacturing semiconductor devices.
`There are used colloidal silica granules of a diameter
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`as large as tens of several nanometers. The granules are
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`normally obtained by growing sodium silicate in water.
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`Obtained granulous silica is then mixed with water to
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`form a suspension or colloidal silica, to which KOH or
`NaOH is added to regulate the hydrogen ion concentra-
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`tion of the suspension and at the same time achieve an
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`enhanced polishing efficiency for the slurry.
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`Compol-8O marketed by Fujimi Corporation is one of
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`commercially available polishing slurries of the above
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`described type containing an alkali metal. When a sili-
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`con oxide film is polished or scraped by using the slurry,
`the alkali metal contained in the slurry is at least partly
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`dispersed into the silicon oxide film or the semiconduc-
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`tor deVice. When the device is a MOS device, the dis-
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`persed metal fluctuates the threshold voltage level of
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`the device to significantly reduce the reliability of the
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`semiconductor device.
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`In order to avoid this problem, some preventive mea-
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`sures need to be taken such as additionally forming a
`protective film layer under the silicon oxide film to
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`block dispersion of alkali metal, making the overall
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`process of manufacturing semiconductor devices rather
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`cumbersome and complicated.
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`Now, how a prior art semiconductor device is pro-
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`duced will be briefly described by referring to illustra-
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`tions showing its sectional views in various stages of
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`preparation. FIG. 1A of the accompanying drawings
`illustrates a conventional semiconductor device com-
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`prising a semiconductor substrate 1 and electrode or
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`wire patterns designated by reference numeral 2. To
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`protect the patterns, a protective film 3 is firstly formed
`,on the entire surface area of the semiconductor struc-
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`ture, and subsequently a resist 4 is applied onto the film
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`3 and then the resist 4 is subjected to a patterning opera-
`tion by using a lithographic technique, as illustrated in
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`FIG. 1B. Thereafter, the protective film 3 is selectively
`removed as the resist 4 is used as masks. Thereafter, the
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`resist 4 is removed to produce a patterned protective
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`film as shown in FIG. 1C. Thereafter, as illustrated in
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`FIG. ID, a silicon oxide film 5 is formed on the semi
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`conductor structure, and then its surface is planarized
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`using a polishing method to produce a planar surface, as
`shown in FIG. 1B. However, the above conventional
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`method additionally requires the steps of FIGS. 1A
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`through 1C, thus complicating the entire manufacturing
`process.
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`There is also used another polishing slurry of the
`colloidal silica series containing no alkali metal. The
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`slurry is obtained by performing pyrolysis of silicic acid
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`tetrachloride or hydrolysis of organic silane to grow
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`silica particles, and regulating the hydrogen ion concen-
`tration of the produced silica by means of ammonia or
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`Page 43 0f 64
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`2
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`an amine. This type of polishing slurry is, however,
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`accompanied by a problem of an unpractically low
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`polishing speed if used for silicon oxide films.
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`On the other hand, a well known method of polishing
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`the surface of glass photo-masks comprises steps of
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`primary polishing using a suspension of aluminum oxide
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`and finish polishing using another suspension containing
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`cerium oxide particles having an average particle size of
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`several micrometers. However, such a two-step polish-
`ing operation involved in the process of manufacturing
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`semiconductor devices is not recommendable by any
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`means, considering the fact that an insulating film needs
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`to be polished to reduce its thickness by only several
`micrometers. Furthermore, in the process of manufac-
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`turing semiconductor devices, an insulating film layer is
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`often formed on the surface of a semiconductor sub—
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`strate that carries raised portions (conductive layers)
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`having a height of several hundreds to thousands nano-
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`meters. Such differences in height of the surface of a
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`semiconductor device will be clearly reflected onto the
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`profile of the insulating film formed thereon. The step
`configuration of the surface of the insulating film need
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`to be planarized by polishing. However, it has not at all
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`been known for sure if cerium oxide particles having an
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`average size of several micrometers can successfully
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`polish and planarize the surface that has a configuration
`of different heights of several hundreds to thousands
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`nanometers and if the insulating film will be contami-
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`nated by the alkali metal as in the case where colloidal
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`silica is used. All in all, the above described method of
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`polishing the surface of a glass layer operating as a
`photo-mask has been developed without taking into
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`consideration if it can be applied to the operation of
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`polishing semiconductor devices during the manufac-
`turing process.
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`The above conventional methods of polishing semi-
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`conductor devices, using colloidal silica or the like as a
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`polishing slurry, are accompanied by the problem of
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`contamination by alkali metal and that of a slow polish-
`ing rate.
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`While a method of using a suspension that does not
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`contain cerium oxide particles is also known in the
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`technology of polishing the surface of glass photo-
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`masks, it is not certain at all if such a method can polish
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`and planarize a surface having a profile of steps of sev-
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`eral hundreds to thousands nanometers high and if it is
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`not accompanied by a problem of metal contamination.
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`Again, it is a method that has been developed without
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`taking into consideration if it can be applied to the oper-
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`ation of polishing semiconductor devices during the
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`manufacturing process.
`Now, a typical known polishing and planarizing tech-
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`nique of the category under consideration will be de-
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`scribed by referring to FIGS. 2A through 2C of the
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`accompanying drawings. As illustrated in FIG. 2A, a
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`semiconductor device is prepared by forming an SiOz
`film 12 on an Si semiconductor device 1 and then a
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`metal wires 13 having a thickness of 1.1 pm are appro-
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`priately formed on the SiOz film 12 to produce a given
`pattern of metal wires.
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`Thereafter, another SiOz film 14 is formed on the
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`entire surface of the above intermediate product. Con-
`sequently, the surface of the second SiOz layer shows
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`raised portions and recessed portions, reflecting the
`pattern of metal wires. Then, the surface of the second
`
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`SiOz layer 14 is polished to remove the raised and re-
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`cessed portions. The operation of polishing or scraping
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`Page 43 of 64
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`3
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`the surface of the second SiOz layer 14 will be carried
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`out by using a polishing apparatus as illustrated in FIG.
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`3.
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`5,445,996
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`4
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`Such a method of forming a thick film and polishing
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`off the film is, however, very time consuming and hence
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`increases the manufacturing cost. Moreover, the more
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`the film is polished, the greater becomes the fluctuations
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`in the polishing speed on the film, a phenomenon by no
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`means favorable for the polishing operation.
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`The above described dishing phenomenon for the
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`recessed portions can be prevented by forming, for
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`instance, a silicon nitride film as a “polish stopper” for
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`the recessed portions in order to suppress the rate of
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`polishing the SiOz film 14 at the recessed portions and
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`increase the rate at which the difference in the thickness
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`of the SiOz film 14 at the raised and recessed portions is
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`reduced.
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`This technique is schematically illustrated in FIGS.
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`5A through 5D, which show a semiconductor structure
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`in cross section. Referring firstly to FIG. 5A, an SiOz
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`film 12 is formed on an Si substrate and (1.1 tun thick)
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`metal wires 13 are formed thereon in a manner as de-
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`scribed before.
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`Thereafter, another SiOz film 14 is formed on the
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`entire surface of the intermediate product as shown in
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`FIG. 5B.
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`Then, a silicon nitride film 15 is formed on the SiOz
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`film 14 and subsequently is subjected to a patterning
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`operation, in which, as shown in FIG. 5C, the silicon
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`nitride film 15 is removed except at the recessed por-
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`tions where no metal wires are formed under the $02.
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`film 14.
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`Finally, the surface of the SiOz film 14 is polished by
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`using a polishing apparatus as illustrated in FIG. 3 in a
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`manner same as the one described above.
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`With this technique, the hight difference significantly
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`disappears from the surface of the SiO;;_ film 14 as shown
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`in FIG. 5D, and the dishing of the SiOz film 14 is also
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`reduced. However, the Si02 film 14 shows slight up-
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`ward bulges in areas of the metal wires 13 to provide
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`small increased and recessed portions that are reversals
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`of those of the Si02 film 14 before the SiOz film 14 is
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`polished.
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`The result of an analysis looking into this phenome-
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`non is summarized in FIG. 6. The object of the analysis
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`is a device comprising metal wires 13 have a width of
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`500 pm and arranged with a distance of 1,000 pm sepa-
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`rating adjacent wires. The abscissa of the graph of FIG.
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`6 represents the polishing time (seconds) in the process-
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`ing step of FIG. 5D, while the coordinate represents the
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`distance between the surface of the first SiOz film 12 and
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`the that of the second SiOz film 14.
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`Before the start of the operation of polishing the
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`device, the distance (solid line in FIG. 6) between the
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`areas (raised portions) of the surface of the SiO;;_ film 12
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`carrying a metal wire 13 and the surface of the SiOzfilm
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`l4 and the distance (broken line in FIG. 6) between the
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`areas (recessed portions) of the surface of the Si0212
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`film carrying no metal wire and the surface of the 5102
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`film 14 show a difference of 1.1 pm which is equal to the
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`height of the metal wires 13.
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`As the polishing operation proceeds, the difference
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`between the distance separating the surface of the SiOz.
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`film 12 and that of the SiOz film 14 at the raised portions
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`and the corresponding distance at the recessed portions
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`is reduced because the speed at which the SiOzfilm 14 is
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`polished off for the raised portions is greater than the
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`speed at which it is polished off for the recessed por-
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`tions. The reason for the difference in speed is that the
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`SiOz film 14 is subjected to a greater load at the raised
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`portions. Additionally with this technique, the speed at
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`More specifically, an Si substrate 1 having a configu-
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`ration as described above is set in position on the turnta-
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`ble the apparatus under a holder 501. A polishing slurry
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`feed pipe 503 is disposed above the turntable 502 to feed
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`a polishing slurry onto the truntable during the opera—
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`tion of polishing the substrate. A polishing cloth 504 is
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`disposed between the surface to be polished of the Si
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`substrate 1 and the turntable 502 so that the raised and
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`recessed portions on the surface of the semiconductor
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`substrate are removed by particles of the polishing
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`slurry and the polishing cloth 504 to provide a plana—
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`rized surface of the semiconductor substrate.
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`The holder 501 is subjected to a load of 40 kfg and
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`rotated at a rate of 100 rpm. The turntable is rotated at
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`the same rotation speed.
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`While the above described polishing method using a
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`polishing apparatus can significantly reduce the raised
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`portions on the surface of the second SiOz film 14, it also
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`dish