UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
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`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-012461
`Patent 7,126,174 B2
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`PETITIONER’S OBJECTIONS TO PATENT OWNER’S EVIDENCE
`SUBMITTED IN THE PATENT OWNER’S RESPONSE
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`1 Case IPR2016-01247 has been consolidated with this proceeding.
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-012461
`Patent 7,126,174 B2
`
`
`PETITIONER’S OBJECTIONS TO PATENT OWNER’S EVIDENCE
`SUBMITTED IN THE PATENT OWNER’S RESPONSE
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`1 Case IPR2016-01247 has been consolidated with this proceeding.
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`IPR2016-01246, IPR2016-01247
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`Patent 7,126,174 B2
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`In accordance with 37 C .F-R. § 42-64(b)(1), Petitioner Taiwan
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`Semiconductor Manufacturing Company, Ltd. submits the following list of
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`objections to Patent Owner IP Bridge’s Exhibits 2004, 2012 through 2019, 2021,
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`2026 through 2030, 2032, and 2033 to the Patent Owner’s Response:
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`Exhibit
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`.
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`.
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`Photograph of a Chemical Mechanical Polishing Tool from the
`Applied Materials Company. BusinessWire.com. Accessed October 5,
`2016.
`
`http://www.businesswire.com/news/home/2004071 1005007/en/Applie
`d—Materials-Revolutionizes-Planarization-Technology—Breakthrough-
`Reflexion
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`2012
`
`Declaration of Dr. E. Fred Schubert, PhD. in support of Patent
`Owner’s Response filed in IPR2016-01246 on March 24, 2017.
`
`2013
`
`Thompson, L. F. “An Introduction to Lithography.” Introduction to
`Microlithography, ACS Symposium Ser., American Chemical Society,
`pp. 1—13 (1983).
`
`
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`2014
`
`CA1275846 C to Roland et a1-
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`2015
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`US. Patent No. 5,314,843 to Yu et al.
`
`2016
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`US. Patent No. 5,231,306 to Meikle et al.
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`2017
`
`US. Patent No. 4,529,621 to Ballard.
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`2018
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`US. Patent No. 5,310,624 to Ehrlich.
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`2019
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`US. Patent No. 5,097,422 to Corbin, 11 et al.
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`2021
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`US. Patent No. 4,952,524 to Lee et a1.
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`
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`IPR2016-01246, IPR2016-01247
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`Patent 7,126,174 B2
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`Exhibit
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`.
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`.
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`2026
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`“Structural Analysis Sample Report” downloaded from
`https://www.chipworks.com/TOC/Structural_Analysis_Sample_Repor
`t.pdf (2008)-
`
`2027
`
`US. Patent No. 4,776,922 to Bhattacharyya et al.
`
`
`
`Subbanna, S.; Ganin, E.; Crabbé, E.; Comfort, J.; Wu, S.; Agnello, P.;
`Martin, B.; McCord, M.; Newman, H. Ng. T.; McFarland, P.; Sun, J.;
`Snare, J.; Acovic, A.; Ray, A.; Gehres, R.; Schulz, R.; Greco, S.;
`Beyer, K.; Liebmann, L.; DellaGuardia, R.; Lamberti, A. “200 mm
`Process Integration for a 0.15 pm Channel-Length CMOS Technology
`Using Mixed X-Ray/ Optical Lithography.” Proceedings of1994
`IEEE International Electron Devices Meeting, pp. 695—698 (1994).
`
`Chung, J.; Jeng, M.-C.; Moon, J Wu, A.T.; Chan, T.Y.; K0, P.K.;
`Hu, Chenming. “Deep-Submicrometer MOS Device Fabrication Using
`a Photoresist-Ashing Technique.” IEEE Electron Device Letters, Vol.
`9. No. 4, pp. 186—188(1988).
`
`Tanaka, Tetsu; Suzuki, Kunihiro; Horie, Hiroshi; Sugii, Toshihiro.
`“Ultrafast Low-Power Operation of p+-n+ Double-Gate SOI
`MOSFETS.” 1994 Symposium on VLSI Technology Digest of
`Technical Papers, pp. 11—12 (1994).
`
`Kaufman, F- B.; Thompson, D. B.; Broadie, R- E.; Jaso, M. A.;
`Guthrie, W. L.; Pearson, D. J.; and Small, M. B. “Chemical-
`
`Mechanical Polishing for Fabricating Patterned W Metal Features as
`Chip Interconnects.” Journal of The Electrochemical Society, Vol.
`138, No. 11, pp. 3460—3465 (1991).
`
`Landis, H.; Burke, P.; Cote, W.; Hill, W.; Hoffman, C.; Kaanta, C.;
`
`Koburger, C .; Lange, W.; Leach, M.; and Luce, S. “Integration of
`chemical-mechanical polishing into CMOS integrated circuit
`manufacturing.” Thin Solid Films, Vol. 220, No. 1—2, pp. 1—7 (1992).
`
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`I.
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`Objection to Paragraphs 4–10 and 35–458 of Patent Owner’s Exhibit
`2012—Unreliable “Expert” Testimony
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`Petitioner objects to Exhibit 2012 because it contains unreliable testimony
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`under Fed. R. Evid. 702 and Daubert v. Merrell Dow Pharm., Inc., 509 U.S. 579
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`(1993). Dr. Schubert’s declaration includes numerous opinions on matters for
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`which Dr. Schubert has failed to establish himself as an expert. Dr. Schubert has
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`not established himself as someone possessing sufficient knowledge, skill,
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`experience, training, and/or education regarding LDD (lightly doped drain)
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`MOSFETs. See Ex. 2012, ¶¶ 13–23, App’x A. Although Dr. Schubert may have
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`experience with III-V compound semiconductors and light-emitting devices,2 such
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`devices are vastly different from the LDD Si MOSFET devices at issue in these
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`proceedings.
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`Dr. Schubert does not claim to have significant experience designing or
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`making LDD Si MOSFET devices.3 Nevertheless, Dr. Schubert repeatedly opines
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`2 See, e.g., Ex. 2012 at ¶¶ 14–17; https://www.rpi.edu/dept/cfes/
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`researchers/Fred%20Schubert.html (last visited Mar. 29, 2017).
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`3 Although MOSFETS may be included in some of the subject matter of
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`courses taught by Dr. Schubert, he provides no evidence regarding the type of
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`information taught relative to MOSFETs, the depth of its treatment, or why mere
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`about the understanding of a person of ordinary skill in the art during the relevant
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`period with respect to LDD Si MOSFET devices.
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`II. Objection to Patent Owner’s Exhibits 2004, 2026, 2029, 2030, 2032, and
`2033—Failure to Authenticate
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`Patent Owner fails to provide evidence to authenticate Exhibits 2004, 2026,
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`2029, 2030, 2032, and 2033, making them inadmissible under Fed. R. Evid. 901.
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`III. Objection to Patent Owner’s Exhibit 2021—Incomplete Document
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`Patent Owner’s Exhibit 2021 appears to be an incomplete document, missing
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`at least three pages, in violation of Fed. R. Evid. 106.
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`IV. Objection to Patent Owner’s Exhibits 2004, 2013–2019, 2026–2030,
`2032, and 2033—Irrelevant and Non-Probative Evidence
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`Patent Owner’s Exhibits 2004, 2013–2019, 2026–2030, 2032, and 2033 are
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`irrelevant to any material facts at issue in these proceedings, and any probative
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`value Patent Owner may try to assign them is substantially outweighed by their
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`tendency to confuse the issues, mislead the Board, waste time, and needlessly
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`present cumulative evidence. These exhibits are therefore inadmissible under Fed.
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`R. Evid. 401, 402, and 403.
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`Citations to Exhibits 2004, 2032, and 2033 appear only in footnotes to
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`paragraph 68 of Dr. Schubert’s declaration (Exhibit 2012 ) and page 102 of Patent
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`inclusion of MOSFETs in a course establishes him as an expert relative to the
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`design and fabrication of LDD MOSFETs (or even one of ordinary skill in the art).
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`Owner’s Response (Paper 14). Paragraph 68 of the declaration reads, in its
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`entirety:
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`68. CMP is a process that includes a polishing pad that is soaked with
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`a chemical solution. The semiconductor wafer is slightly pressed onto
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`the polishing pad. The semiconductor wafer and polishing pad are
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`subjected to rotating motions to ensure uniformity of the CMP
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`process. CMP
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`includes a chemical-etching component and a
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`mechanical-polishing component both of which contribute to the
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`planarization (or flattening) of the wafer surface. Two schematics of
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`the CMP process6 and a photograph of a CMP tool7 are shown below.
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`The schematics and photograph show a Si wafer subjected to CMP.
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`Footnotes 6 and 7 cite Exhibits 2004, 2032, and 2033 as the sources of the
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`photographs above. Page 102 of Patent Owner’s Response states, “the CMP
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`process available at the time of the invention of the ‘174 patent would have
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`planarized the Si wafer in its entirety” (Paper 14, at 102), which none of the
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`references state. Moreover, none of the claims at issue, which are all device
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`structure claims, recites CMP or even planarization, making the entire discussion
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`of CMP irrelevant. Exhibits 2004, 2032, and 2033 are equally irrelevant and more
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`likely to confuse the issues than to clarify them.
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`Additionally, Exhibit 2004 is a webpage dated July 12, 2004, published
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`years after the date of invention (December 1995, see Paper 8, at 13 n.5). Because
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`it significantly post-dates the invention and provides only “impermissible . . . later
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`knowledge about later art-related facts,” Exhibit 2004 has no relevance. In re
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`Hogan, 559 F.2d 595, 605 (CCPA 1977).
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`The citations to Exhibits 2013–2019 are cited merely to support the idea that
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`semiconductor fabrication is complex or, as Dr. Schubert puts it, that “the
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`complexity of integrated circuit fabrication was appreciated by the technical
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`community and widely supported by the technical literature.” Ex. 2012 at ¶ 61. The
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`complexity of IC fabrication and the technical community’s recognition of that
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`premise are not at issue in these proceedings, making these references irrelevant.
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`Exhibit 2026 is a “Sample Report” from a company called Chipworks
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`downloaded from the Internet. (See Paper 14, at ix.) Neither Patent Owner’s
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`Response nor Dr. Schubert’s declaration cites to any specific portion of this 161-
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`page document, making it impossible to establish relevance for the document. In
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`addition, because Exhibit 2026 bears a date of January 2008, it is not relevant.
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`Exhibit 2026 significantly post-dates the invention and provides only
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`“impermissible . . . later knowledge about later art-related facts.” In re Hogan, 559
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`F.2d at 605. Exhibit 2026 provides an analysis of a “45 nm process,” which did not
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`exist at the time of alleged invention and included later-developed design
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`constraints.
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`Patent Owner’s Response and Dr. Schubert’s declaration cite Exhibits 2027–
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`2030 to suggest “a microscopic assessment technique such as scanning electron
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`microscopy (SEM) in 1995 would show the two layers as an indistinguishable
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`entity.” (Paper 14, at 103; Exhibit 2012 at ¶ 385; see also Paper 14, at 104.) The
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`poor resolution of the SEM images in Exhibits 2027–2030 renders them unusable
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`and far more likely to confuse the issues than to clarify them. Additionally, neither
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`Patent Owner’s Response nor Dr. Schubert’s declaration cites to any specific
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`portions of Exhibits 2027–2030, making it impossible to establish relevance for the
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`document.
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`V. Objection to Patent Owner’s Exhibits 2004 and 2026—Hearsay
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`Petitioner objects to Exhibits 2004 and 2026 to the extent that Patent Owner
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`relies on their contents for the truth of the matters asserted therein. Exhibits 2004
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`and 2026 constitute hearsay under Fed. R. Evid. 801 and 802, and no exception
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`applies.
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`Exhibit 2004 is a third-party website that bears no discernable relationship to
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`Dr. Schubert and Patent Owner, strongly suggesting that they have no personal
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`knowledge of the contents contained therein.
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`Exhibit 2026, the “Sample Report” from Chipworks that someone
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`downloaded from the Internet (See Paper 14, at ix), has nothing to indicate either
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`Dr. Schubert or Patent Owner provide have personal knowledge of the contents
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`contained therein.
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`Dated: March 31, 2017
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`Respectfully submitted,
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`By: /Darren M. Jiron/
`Darren M. Jiron
`Reg. No. 45,777
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`
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`Lead Counsel for Petitioner
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. § 42.6(e), this is to certify that I served a true and
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`correct copy of the PETITIONER’S OBJECTIONS TO PATENT OWNER’S
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`EVIDENCE SUBMITTED IN THE PATENT OWNER’S RESPONSE by
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`electronic mail, on this 31st day of March, 2017, on counsel of record for the
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`Patent Owner as follows:
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`Neil F. Greenblum
`ngreenblum@gbpatent.com
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`Michael J. Fink
`mfink@gbpatent.com
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`Arnold Turk
`aturk@gbpatent.com
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`
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`Dated: March 31, 2017
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`By: /Lauren K. Young/
`Lauren K. Young
`Litigation Legal Assistant
`FINNEGAN, HENDERSON, FARABOW,
`GARRETT & DUNNER, L.L.P.
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