2.2
`
`Ultrafast Low-Power Operation of p+-n+ Double-Gate SO1 MOSFETs
`
`TetsuTanaka, Kunihiro Suzuki. Huoshi Horie, and Toshihiro Sugii
`Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01. Japan
`
`1. I n t r o d u c t i o n
`Double-gate SO1 MOSFETs don't suffer from the short-
`channel effects that limit the scaling of bulk MOSFETs
`because two gate electrodes jointly control the carriers. The
`excellent short-channel behavior and high transconductance
`has been studied theoretically and experimentally [I -41.
`As the MOSFET technology is extended into the sub-
`quarter-micron range and the supply voltage is scaled to 1-2
`V, it needs to lower the threshold voltage (Vth) less than 0.3
`V to obtain enough drain current. However, the Vth of
`conventional double-gate SO1 nMOSFETs is -0.1 V with n+-
`nf poly Si gate electrodes. and 1 V with pf-p+ poly Si gate
`electrodes. The values are not appropriate for such short gate
`lengths. In this paper, we proposed p+ poly Si for the front-
`gate electrode and n+ poly Si for the back-gate electrode in
`order to optimize the Vth. resulting in small subthreshold
`current and large drain current. A record ring oscillator gate
`delay of 27 ps at 2 V for Lg = 0.19 prn was obtained.
`2. Vth Control
`Figure 1 shows the cross-sectional view of this device.
`Assuming full-depletion of
`the Si layer and charge
`conservation at Si-Si02 interfaces. we found that the nMOS
`threshold voltage. V t S n . with these gate electrodes is :
`
`0.3 V. Both the thin silicon films and the use of two gate
`electrodes suppress short-channel effects for gate length
`below 0.2 p. Figure 5 shows the I-V characteristics of 0.19-
`pn Lg MOSFETs. We used the front-gate poly Si length as the
`gate length for all the devices. We obtained very large drain
`currents and steep subthreshold slope for n- and PMOS with
`front-gate oxide 8.2 nm thick and back-gate oxide 9.9 nm
`thick. The subthreshold slope was about 69 mV/decade for
`nMOS and 7 0 mV/decade for PMOS because of two gate
`electrodes. We extracted capacitance values of equivalent
`circuit parameters for the nMOS device from S-parameter
`measurements (Table 1). The reference bulk MOSFET had a
`gate 0.15 pm long and a gate oxide 4 nm thick [6]. The drain-
`source capacitance, Cds. is remarkably small, which is about
`10% of the reference value, because of thick buried oxide
`under the drain. The gate-drain capacitance, Cgd. is larger
`than the reference value due to the overlap capacitance
`between back-gate and drain. Using these devices, we
`fabricated an unload inverter ring oscillator. We examined the
`dependence of the delay time on the supply voltage and the
`power dissipation normalized to 1 GHz clock-frequency
`(Figs. 6.7). For Lg = 0.19 pm, we obtained an inverter delay
`time of 43 ps at 1 V, and 27 ps at 2 V. These are, to our
`knowledge, the fastest reported values for this gate length
`despite the thick gate oxides. The p+-n+ double-gate SO1
`MOSFETs operate with a faster switching speed especially at
`low supply voltage and lowcr power consumption at the same
`switching speed. This is because low Vth and steep
`subthreshold slope lead large drain currents at low supply
`voltage and because the Cds doesn't increase at low supply
`voltage unlike the bulk MOSFET.
`is the Vth of n+-n+ poly Si gate devices. Vth
`and V%n
`PP
`5. Summary
`are 0.98 V and -0.12 V, respectively [ 5 ] . The
`and Vth,,
`Using direct bonded SO1 wafers just 40 nm thick, we
`PMOS Vth is the same magnitude as the nMOS Vth but the
`fabricated p+-nf double-gate SO1 MOSFETs. These devices,
`opposite polarity because of the symmetrical structure. We
`with an appropriate Vth, have good short-channel behavior
`plotted the dependence of Vthpn on the aspect ratio of
`and a large drive current. For Lg = 0.19 pn, we obtained an
`silicon thickness to gate oxide (Fig. 2). The Vthpn is less
`inverter delay time of 43 ps at 1 V. and 27 ps at 2 V. These are
`than 0.3 V for the aspect ratio more than 2. The experimental
`the fastest reported values for this gate length. The high
`Vth with the aspect ratio of 5 were 0.17 V for nMOS and -
`performance is attributed to the large drain current, the low
`0.24 V for PMOS. which were almost the same as those
`series resistance. and the reduction of the parasitic drain
`expected from our theory.
`junction capacitance.
`A c k n ow I e d g m en t s
`3. Process Technology
`Figure 3 shows a SEM cross section of nMOS device. A
`The authors are thankful to members of device fabrication
`detailed process integration is given in [3]. The key process
`group in our laboratory. The authors are also thankful to Drs.
`were as follows ; we used direct bonded SO1 wafers thinned to
`Arimoto, Hijiya. and It0 for their encouragement.
`4 0 nm by chemical-mechanical polishing (CMP). The n- and
`References
`PMOS gate conductivity types were the same, so the poly Si
`1. T. Sekigawa, et al., Solid-St. Electron. 27, p. 827
`gate doping didn't require a mask process. To minimize the
`(1984).
`series resistance, we used W silicide for the back-gate and CO
`2. H. Horie, et al., SSDM Tech. Dig.. p. 165 (1991).
`salicide for the front-gate, source and drain [6]. The resultant
`3. T. Tanaka, et al.. IEDM Tech. Dig., p.683 (1991).
`sheet resistance of 6-9 R/sq. was achieved.
`4. J. P. Colinge, et al., IEDM Tech. Dig., p595 (1990).
`4. Results a n d Discussion
`5. K. Suzuki. et al., Solid-St. Electron. (in print).
`Figure 4 shows the threshold rolloff. The Vth is less than
`6. T. Yamazaki, et al., IEDM Tech. Dig., p906 (1993).
`11
`1994 Symposium on VLSl Technology Digest of Technical Papers
`0-7803-19212-4/94/$3.00 0 1994 IEEE
`
`whereTsi is the silicon thickness, To, is the gate oxide
`
`thickness, Vthpp is the Vth of p+-p+ poly Si gate devices,
`
`Page 1 of 2
`
`IP Bridge Exhibit 2030
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`Ultrafast Low-Power Operation of p+-n+ Double-Gate SO1 MOSFETs
`
`TetsuTanaka, Kunihiro Suzuki. Huoshi Horie, and Toshihiro Sugii
`Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01. Japan
`
`1. I n t r o d u c t i o n
`Double-gate SO1 MOSFETs don't suffer from the short-
`channel effects that limit the scaling of bulk MOSFETs
`because two gate electrodes jointly control the carriers. The
`excellent short-channel behavior and high transconductance
`has been studied theoretically and experimentally [I -41.
`As the MOSFET technology is extended into the sub-
`quarter-micron range and the supply voltage is scaled to 1-2
`V, it needs to lower the threshold voltage (Vth) less than 0.3
`V to obtain enough drain current. However, the Vth of
`conventional double-gate SO1 nMOSFETs is -0.1 V with n+-
`nf poly Si gate electrodes. and 1 V with pf-p+ poly Si gate
`electrodes. The values are not appropriate for such short gate
`lengths. In this paper, we proposed p+ poly Si for the front-
`gate electrode and n+ poly Si for the back-gate electrode in
`order to optimize the Vth. resulting in small subthreshold
`current and large drain current. A record ring oscillator gate
`delay of 27 ps at 2 V for Lg = 0.19 prn was obtained.
`2. Vth Control
`Figure 1 shows the cross-sectional view of this device.
`Assuming full-depletion of
`the Si layer and charge
`conservation at Si-Si02 interfaces. we found that the nMOS
`threshold voltage. V t S n . with these gate electrodes is :
`
`0.3 V. Both the thin silicon films and the use of two gate
`electrodes suppress short-channel effects for gate length
`below 0.2 p. Figure 5 shows the I-V characteristics of 0.19-
`pn Lg MOSFETs. We used the front-gate poly Si length as the
`gate length for all the devices. We obtained very large drain
`currents and steep subthreshold slope for n- and PMOS with
`front-gate oxide 8.2 nm thick and back-gate oxide 9.9 nm
`thick. The subthreshold slope was about 69 mV/decade for
`nMOS and 7 0 mV/decade for PMOS because of two gate
`electrodes. We extracted capacitance values of equivalent
`circuit parameters for the nMOS device from S-parameter
`measurements (Table 1). The reference bulk MOSFET had a
`gate 0.15 pm long and a gate oxide 4 nm thick [6]. The drain-
`source capacitance, Cds. is remarkably small, which is about
`10% of the reference value, because of thick buried oxide
`under the drain. The gate-drain capacitance, Cgd. is larger
`than the reference value due to the overlap capacitance
`between back-gate and drain. Using these devices, we
`fabricated an unload inverter ring oscillator. We examined the
`dependence of the delay time on the supply voltage and the
`power dissipation normalized to 1 GHz clock-frequency
`(Figs. 6.7). For Lg = 0.19 pm, we obtained an inverter delay
`time of 43 ps at 1 V, and 27 ps at 2 V. These are, to our
`knowledge, the fastest reported values for this gate length
`despite the thick gate oxides. The p+-n+ double-gate SO1
`MOSFETs operate with a faster switching speed especially at
`low supply voltage and lowcr power consumption at the same
`switching speed. This is because low Vth and steep
`subthreshold slope lead large drain currents at low supply
`voltage and because the Cds doesn't increase at low supply
`voltage unlike the bulk MOSFET.
`is the Vth of n+-n+ poly Si gate devices. Vth
`and V%n
`PP
`5. Summary
`are 0.98 V and -0.12 V, respectively [ 5 ] . The
`and Vth,,
`Using direct bonded SO1 wafers just 40 nm thick, we
`PMOS Vth is the same magnitude as the nMOS Vth but the
`fabricated p+-nf double-gate SO1 MOSFETs. These devices,
`opposite polarity because of the symmetrical structure. We
`with an appropriate Vth, have good short-channel behavior
`plotted the dependence of Vthpn on the aspect ratio of
`and a large drive current. For Lg = 0.19 pn, we obtained an
`silicon thickness to gate oxide (Fig. 2). The Vthpn is less
`inverter delay time of 43 ps at 1 V. and 27 ps at 2 V. These are
`than 0.3 V for the aspect ratio more than 2. The experimental
`the fastest reported values for this gate length. The high
`Vth with the aspect ratio of 5 were 0.17 V for nMOS and -
`performance is attributed to the large drain current, the low
`0.24 V for PMOS. which were almost the same as those
`series resistance. and the reduction of the parasitic drain
`expected from our theory.
`junction capacitance.
`A c k n ow I e d g m en t s
`3. Process Technology
`Figure 3 shows a SEM cross section of nMOS device. A
`The authors are thankful to members of device fabrication
`detailed process integration is given in [3]. The key process
`group in our laboratory. The authors are also thankful to Drs.
`were as follows ; we used direct bonded SO1 wafers thinned to
`Arimoto, Hijiya. and It0 for their encouragement.
`4 0 nm by chemical-mechanical polishing (CMP). The n- and
`References
`PMOS gate conductivity types were the same, so the poly Si
`1. T. Sekigawa, et al., Solid-St. Electron. 27, p. 827
`gate doping didn't require a mask process. To minimize the
`(1984).
`series resistance, we used W silicide for the back-gate and CO
`2. H. Horie, et al., SSDM Tech. Dig.. p. 165 (1991).
`salicide for the front-gate, source and drain [6]. The resultant
`3. T. Tanaka, et al.. IEDM Tech. Dig., p.683 (1991).
`sheet resistance of 6-9 R/sq. was achieved.
`4. J. P. Colinge, et al., IEDM Tech. Dig., p595 (1990).
`4. Results a n d Discussion
`5. K. Suzuki. et al., Solid-St. Electron. (in print).
`Figure 4 shows the threshold rolloff. The Vth is less than
`6. T. Yamazaki, et al., IEDM Tech. Dig., p906 (1993).
`11
`1994 Symposium on VLSl Technology Digest of Technical Papers
`0-7803-19212-4/94/$3.00 0 1994 IEEE
`
`whereTsi is the silicon thickness, To, is the gate oxide
`
`thickness, Vthpp is the Vth of p+-p+ poly Si gate devices,
`
`Page 1 of 2
`
`IP Bridge Exhibit 2030
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`NMOS
`
`PMOS
`
`Vthpp (p+-p+ poly Si gates)
`
`a,
`5
`
`0.6
`
`I-
`
`Figure 1 Cross section of CMOS devices
`
`_____-_---------_
`0 Vthnn (n+-n+ poly si gates)
`-0.2
`0
`
`8
`
`1
`
`0
`
`
`
`6
`Tsi I Tor
`Figure 2 Dependence of Vth on aspect ratio
`
`2
`
`4
`
`? 0.251 nMoS
`- F
`g
`o
`
`
`0
`
`Vds (V)
`
`z v)
`
`b-
`
`Figure 3 SEM image
`
`NMOS
`
`PMOS
`
`-0
`
`-0.25
`
`PMOS
`
`-0.05
`Vth : Vgs at Id = 0.1 (rJvpn)
`-0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
`Gate length (p)
`Figure 4 Vth rolloff
`
`Table 1
`DG-SO1
`Cds
`0.40 fF
`I Cgdl 1.98fF
`lCgs I 4.59 fF
`
`Device width is 5 pm.
`
`Bulk MOS"
`3.75fF
`I 1.40fF
`I
`1
`1 6.11 fF
`* Reference [6]
`
`2
`1
`0
`Gate voltage (V)
`Gate voltage (V)
`Figure 5 I-V characteristics of devices with Tsi = 40 run, To, (front) = 8.2 nm,
`and To, (back) = 9.9 nm.
`
`3
`
`
`
`J
`\
`
`-
`
`90
`80
`3 70
`m 2 60
`n
`
`50
`
`
`
`Bulk MOS q, Bulk MOS q,,
`
`DG-SO1
`
`E 40
`>
`2 30
`6 20
`10
`2.5 3
`1.5
`0 0.5 1
`2
`Supply voltage (V)
`
`=-....
`"0 ..._.__
`
`3.5
`
`."
`
`10-5
`
`10-4
`Power dissipation (WIGHzlgate)
`
`10-3
`
`Figure 7 Dependence of delay time on power dissipation
`Figure 6 Dependence of delay time on supply voltage
`12
`1994 Symposium on VLSl Technology Digest of Technical Papers
`
`Page 2 of 2
`
`
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