I86
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 9, NO. 4, APRIL 1988
`
`Deep-Submicrometer MOS Device Fabrication
`Using a Photoresist-Ashing Technique
`
`Abstract-A photoresist-ashing process has been developed which,
`when used in conjunction with conventional g-line optical lithography,
`permits the controlled definition of deep-submicrometer features. The
`ultra-fine lines were obtained by calibrated ashing of the lithographically
`defined features in oxygen plasma. The technique has been successfully
`employed to fabricate MOSFET’s with effective channel length as small
`as 0.15 pm that show excellent characteristics. An NMOS ring oscillator
`with 0.2-pm devices has been fabricated with a room-temperature
`propagation delay of 22 pslstage which is believed to be the fastest value
`obtained for a MOS technology. Studies indicate that the thinning is both
`reproducible and uniform so that it should be usable in circuit as well as
`device fabrication. Since most polymer-based resist materials are etchable
`with an oxygen plasma, the basic technique could be extended to
`supplement other lithographic processes, including e-beam and X-ray
`processes, for fabricating both silicon and nonsilicon devices and circuits.
`
`I. INTRODUCTION
`ECAUSE of the resolution limit of optical lithography,
`
`B e-beam and X-ray lithography have been the principal
`
`means used to fabricate deep-submicrometer devices including
`MOSFET’s [ 11-[3]. However, both techniques are compli-
`cated and expensive. In addition, both techniques require
`exposing the device to varying doses of high-energy radiation
`creating potential reliability problems.
`In this paper, a photoresist-ashing process is presented
`which, when used in conjunction with conventional g-line (A
`= 436 nm) optical lithography, permits the controlled
`definition of deep-submicrometer features. The technique has
`been successfully employed to fabricate MOSFET’s with
`effective channel length as small as 0.15 pm that show
`excellent overall characteristics. Results of evaluation studies
`indicate that the ashing is both reproducible and uniform so
`that it should be usable in circuit as well as device fabrication.
`
`11. FABRICATION
`PROCESS
`Polysilicon-gate NMOS transistors were fabricated as a
`demonstration of this technique. The starting substrates were
`4-in-diameter, 15-30 Q mcm, p-type silicon wafers. Each wafer
`was given a boron field implant of 2.25 x 10I2 cm-2 at 70
`
`Manuscript received November 19, 1987; revised February 5, 1988. This
`work was supported by SRC, Kodak Fellowship, Hughes, and Rockwell
`International under the State of California MICRO program, and the Joint
`Services Electronics Program (JSEP) under Contract F49620-84-C-0057,
`J. Chung, M.-C. Jeng, J. E. Moon, P. K. KO, and C. Hu are with the
`Department of Electrical Engineering and Computer Sciences, Electronics
`Research Laboratory, University of California, Berkeley, CA 94720.
`A. T. Wu and T. Y. Chan were with the Department of Electrical
`Engineering and Computer Sciences, Electronics Research Laboratory,
`University of California, Berkeley, CA 94720. They are now with Intel
`Corporation, Santa Clara, CA 9505 1.
`IEEE Log Number 8820492.
`
`keV. The active regions were then defined using local
`oxidation of silicon (LOCOS). A field oxide of 0.25 pm was
`grown in steam at 950°C. Depending upon the gate oxide
`thickness, a boron threshold/punchthrough implant at 30 keV
`with varying dose from 1.0 x 10l2 to 1.6 x 1013 cm-2 was
`performed. Gate oxides of 3.6,5.6, 7.5, and 8.6 nm were then
`grown at 800°C in dry oxygen. Gate oxide of 15.6 nm was
`grown at 900°C in dry oxygen. All gate oxides were annealed
`in nitrogen at their oxidation temperature for 20 min. In-situ
`doped n+ -polysilicon (0.25 pm) was then immediately depos-
`ited by LPCVD. Up to this point, the process was similar to a
`standard NMOS process.
`Gates with drawn lengths from 0.7 to 1.5 pm were initially
`defined using conventional lithographic methods. Kodak
`Micro Positive Resist 820, a positive photoresist, was spun on
`to a thickness of 1.0 pm and soft-baked for 1 min at 100°C.
`All exposures were performed using a g-line lox wafer
`stepper. In order to obtain optimal after-ashing line shape and
`step coverage for the submicrometer gates, it was necessary to
`reduce the exposure 10-20 percent from the exposure required
`for defining gates longer than 1 pm. After exposure, the
`wafers were developed and given a final hard bake of 15 min
`at 120 ’ C before ashing .
`A low-frequency (30 kHz) plasma etching system was then
`used to ash the patterned photoresist. Optimal controllability
`and uniformity of the ashing process was observed for an
`oxygen pressure of 300 mtorr and an RF power of 50 W. To
`define the gates, the polysilicon was then anisotropically
`etched in C C 4 plasma.
`Self-aligned arsenic source/drain implants of 3.0 x
`cm-2 at 50 keV were then performed. Subsequent thermal
`cycles were less than 60 min at 900°C in order to reduce
`implant diffusion and the junction depth.
`
`111. EXPERIMENTAL RESULTS
`The ashing process was observed to be controllable and
`reproducible. Fig. 1 displays a plot of the SEM-measured gate
`length versus ashing time for four different drawn MOSFET
`gate lengths. A lateral ashing rate of about 0.068 pm/min is
`observed. This rate appears to be relatively independent of the
`ashing time, the initial drawn length, and the original
`photoresist shape. The linear ash rate appears constant down
`to at least 0.2 pm. Narrower lines can be created, but only
`with a lesser degree of control. The difference between the
`drawn lengths and the measured lengths before ashing is due to
`the reduced exposure mentioned above. The polysilicon gate
`width was also determined from the changing resistances of
`
`0741-3106/88/0400-0186$01 .OO O 1988 IEEE
`
`Page 1 of 3
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`

`CHUNG et al.: DEEP-SUBMICROMETER MOS DEVICE FABRICATION
`
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`Ashing Time I min 3
`Fig. 1. SEM measured channel length versus ashing time for four different
`initial mask channel lengths. The net lateral ashing rate is approximately
`680 Almin.
`
`10
`
`12
`
`0.0
`
`0.6
`
`1.8
`1.2
`Drain Vollage I V J
`Characteristic of a deep-submicrometer MOSFET fabricated with
`the photoresist-thinning technique.
`
`2.4
`
`3.0
`
`Fig. 4.
`
`Fig. 2. SEM photograph of the step coverage of a photoresist-covered
`polysilicon gate after 8 min of ashing. The polysilicon line is 0.5 p n wide.
`The profile of the photoresist is preserved after ashing.
`
`Fig. 5. Waveform of a 101-stage enhancementldepletion ring oscillator
`consisting of 0.2-pm MOSFET’s with 75-nm gate oxide at a power supply
`voltage of 3 V. The output signal is 75 mV peak to peak (20 mVldiv).
`
`approximately 0.5 pm. The estimated junction depth is 0.2
`pm. The difference between the measured junction depth and
`the lateral diffusion distance under the gate edge reflects a
`nonequality between the vertical and lateral arsenic diffusion
`rates. From C- I/ profiling measurements and computer
`simulations, the channel doping was estimated to be 2-8 x
`depending upon the threshold/punchthrough im-
`10’’
`plant.
`No process controllability problems were introduced by the
`ashing procedure. Using data obtained from the capacitance
`technique [4], the effective channel length Leff was compared
`with the drawn gate length Lmask. The amount of length
`reduction (AL = Lmask - Leff) was found to be independent of
`Lm&. Statistical measurements were performed on wafer lots
`with varying amounts of ashing time. No significant variability
`in channel length was introduced by the ashing process within
`a particular lot. Any channel length variations observed were
`found to be within the tolerances of the lithographic system
`used.
`Fig. 4 shows the characteristics for a transistor with an
`oxide thickness of 3.6 nm and an effective channel length of
`0.15 pm. The measured transconductance of this device is
`over 630 mS/mm at room temperature. Excellent performance
`and punchthrough control are observed, and no gate-diffusion
`nonoverlap problems were found [ 5 ] .
`Fig. 5 displays the waveform of a 101-stage enhancement/
`
`Fig. 3. SEM photograph of a transistor cross section with Leff = 0.22 pm.
`The junction depth is 0.2 pm. Ashing time is 8 min, and AL due to the
`ashing is approximately 0.5 pm.
`
`polysilicon resistors with varying amounts of ashing time.
`Good agreement between electrical and SEM results was
`observed. Fig. 2 presents an SEM picture of a photoresist-
`covered polysilicon line after 8 min of ashing. Excellent line
`shape and step coverage is observed. No change in the
`photoresist profile was observed during the ashing procedure.
`This ashing procedure was incorporated into a deep-
`submicrometer process. Fig. 3 displays an SEM picture of
`transistor cross sections with an L,ff of 0.22 pm. The ashing
`time was 8 min with a corresponding length reduction of
`
`Page 2 of 3
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`

`

`I88
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 9, NO. 4, APRIL 1988
`
`depletion ring oscillator with an L,ff of 0.2 pm and a 7.5-nm
`ACKNOWLEDGMENT
`gate Oxide. A room-temperature gate
`Of 22 Ps is
`The authors would like to thank K. Voros, R. Hamilton, R.
`at a power
`is Rudell, M. Kushner, and T. Booth from the Micro-Electronics
`Observed
`Of
`believed to be the fastest value reported for a silicon MOS Laboratory, University of California at Berkeley, for their
`technology.
`assistance in the device fabrication process.
`
`”‘ This
`
`Iv . CONCLUSIONS
`A photoresist-ashing process has been developed which
`allows the relatively simple fabrication of deep-submicrometer
`MOSFET’s using only g-line lithography. This process
`appears to be controllable and easily adaptable to most existing
`technologies. Although this technique does not inherently
`improve circuit density, by increasing the gain and driving
`capability of the MOSFET, the potential of improving digital
`and analog circuit speed is significant. Since most polymer-
`based resist materials are ashable with an oxygen plasma, the
`basic technique could be extendible to supplement other
`lithographic processes, including e-beam and X-ray processes,
`for fabricating both silicon and nonsilicon devices and circuits.
`
`[2]
`
`[3]
`
`REFERENCES
`[l] W. Fichtner et al., “High-speed low-power circuits fabricated using a
`submicron NMOS technology,” IEEE Electron Device Lett., vol.
`EDL-6, p. 662, 1985.
`W. Fichtner et al., “0.15 pm channel-length MOSFETs fabricated
`using E-beam lithography,” in IEDM Tech. Dig., 1982, p. 722.
`S. Y. Chou, H. I. Smith, and D. A. Antoniadis, “Sub-100 nm channel
`length transistors fabricated using X-ray lithography,” J. Vac. Sci.
`Tech. B, vol. 4, no. 1, p. 253, 1986.
`B. J. Sheu and P. K. KO, “A capacitance method to determine channel
`length for conventional and LDD MOSFET’s,” IEEE Electron Device
`Lett., vol. EDL-5, p. 491, 1984.
`P. K. KO, T. Y. Chan, A. T. Wu, and C. Hu, “The effects of weak
`gate-to-drain (source) overlap on MOSFET characteristics,” in IEDM
`Tech. Dig., 1986, p. 292.
`
`[4]
`
`[5]
`
`Page 3 of 3
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