200 mm Process Integration for a 0.15 pm Channel-Length
`CMOS Technology Using Mixed X-Ray / Optical Lithography
`S. Subbanna, E. Ganin, E. CrabbC, J. Comfort, S. Wu, P. Agnello, B. Martin, M. McCord,
`H. Ng, T. Newman, P. McFarland, J. Sun, J. Snare, A. Acovic, A. Ray, R. Gehres,
`R. Schulz, S. Greco, K. Bcyer, L. Liebmann, R. DellaGuardia tx, and A. Lambertit”.
`IB M, MicroElectronics Division,
`Semiconductor Research and Development Center,
`t Advanced Lithography Facility,
`Iiopewell Junction, NY 12533.
`
`AIWTRACT
`
`In this work, an integrated 0.35 pm CMOS tech-
`nology with 0.15 pm effective channel length (LE,r) is
`demonstrated in a 200 mm line. X-ray lithography is
`used for the critical gate level, along with conventional
`deep-UV and mid-UV lithography for other levels.
`Shallow Trench Isolation (STI) is used to achieve 0.35
`pm design rules. The NFET and PFET devices are
`designed for operation with a scaled power supply of
`1.8 V. This technology provides 50% performance
`improvement relative to a 2.5V, 0.5 pm design rule,
`0.25 pm L E F F high-performance CMOS technology.
`
`INTRODUCTION
`
`Achieving a technology with nominal electrical
`channel length (LEw) of 0.15 pm [l] requires gate
`lithography with a nominal dimension of 0.20-0.25 pm.
`In addition, for 0.35 pm high-performance, high-den-
`sity logic, the key technology issues to be considered
`are 0.35-0.40 pm isolation, 4.0-5.0 nm gate dielectric
`integrity, shallow implanted S/D junction formation for
`acceptable device rolloff, gate conductor resistance and
`borderless contact/ local interconnect formation for
`high density [2][3].
`
`PROCESS
`
`A shallow-trench process (STI) [4]
`is used to
`achieve an isolation thickness of 0.35 pm from infinite
`width down to 0.40 p m spaces. After the isolation
`trench is etched in the silicon and filled with LPCVD
`TEOS, a combination of resist planarkation, R E , and
`chemo- mechanical polish is used to form the oxide
`isolation. After growing the screen oxide, the wells are
`implanted. Non-uniform well profdes are used in order
`to obtain acceptable on-current and threshold voltage
`rolloff Cl].
`
`lithography, we have
`the critical gate-level
`For
`employed X-ray
`lithography using a synchrotron
`source and a 200mm wafer altgner with a stage capable
`of < 0.20 pm mix and match overlay. A 1.0 pm chem-
`ically-amplified positive resist (APEX) is used. This
`X-ray exposure facility allows routine integration of a
`single-level X-ray exposure for images down to 0.125
`pm with conventional 0.35 pm DUV process capability
`at a much higher level of throughput than electron-
`beam lithography systems can provide. The X-ray
`mask was fabricated using a 0.6 pm gold absorber with
`pattern sizes down to 0.125 pm on a 18 mm x 32 mm
`field size. Pig. 1 shows the resultant resist profile for a
`typical 0.20 pm line. Table I summarizes image CD
`data for 0.125 and 0.20 pm features. Fig. 2 shows an
`image placement error plot for demonstrating an
`average overlay error less than lOOnm with a worst case
`overlay of 124nm for a 123 site measurement sample.
`Fig. 3 shows an SEM view of the 0.2 p m gates (with
`sidewall spacer). Fig. 4 shows a TEM cross-section of
`a completed device (LMAsK = .20 pm) Figure 5 shows
`excellent across-wafer LEpF distribution for NFETs
`achieved for a nominal effective channel length of 0.15
`pm with X-ray lithography. A W-stud local intercon-
`nect ( < 1 O/sq.) with borderless contact to isolation
`provides wiring for embedded SRAM and high-density
`logic applications [2],[3].
`For an effective channel length of 0.15 pm, a gate oxide
`thickness of about 5 nm and shallow source-drain junc-
`tions with a depth of 60-80 nm are required. The corre-
`sponding power-supply voltage would be 1.8V [SI.
`The viability of a 5 nm gate oxide in a fully integrated
`process is demonstrated by the gate leakage histograms
`for NFET and PFET shown in Figure 6. One of the
`challenging integration issue for 0.15 pm CMOS is the
`controlled fabrication of sub-100 nm S/D junctions.
`
`28.8.1
`
`0-7803-2111-1 $4.00 C J 1994 IEEE
`
`IEDM 94-695
`
`Page 1 of 4
`
`IP Bridge Exhibit 2028
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`We have chosen to explore the extension of conven-
`tional ion-implantation techniques in order to fully
`utilize existing fabrication capabilities for this gener-
`ation. Figure 7 shows resultant SIMS profiles for
`shallow n-type and p-type junctions fabricated using
`Ge pre-amorphization to control channelling and ann-
`ealed with a 1000°C rapid thermal anneal. This figure
`also shows the halo implants that are used for short
`channel effect (SCE) control. Fig. 8 shows short
`channel threshold voltage (V7;saT, VDo = 1.8V) for
`NFETs and PFETs respectively. Both NFET and
`PFET devices exhibit VT,SAT rolloff of less than 225 mV
`down to channel lengths of about 0.12 pm. The halo
`implants also sharpen the dopant profde on the shallow
`S/D as a means to both improve short channel
`behavior and reduce the parasitic resistance.
`
`Key concerns for 0.15 pm devices using implanted S/D
`extensions is their leakage behaviour with limited
`annealing cycles and silicidation for series resistance
`reduction. Figure 9 shows the leakage current histo-
`grams for N-junctions with only a 1000°C anneal.
`Figure 10 shows the leakage current histogram for
`P-junctions, with a larger tail. The overall leakage con-
`tribution to off-current is still negligible, however.
`Figure 11 shows the ION - IOFF tradeoff for NFETs and
`PFETs and indicates acceptable off-current behavior
`for nominal 0.15 pm NFET and PFET devices, with
`on-currents of 0.45 mA/pm and 0.22 mA/pm respec-
`tively (VDD = 1.8V). We have used a thick sidewall to
`position deep junctions which can be salicided to
`reduce device series resistance and contact resistance.
`The resultant transconductance G M s S A T at 1.8V is 350
`mS/mm for NFET and 180 m S / m for PFET while
`the extemal resistances are 340 and 570 ohm-pm
`respectively. The gate conductor sheet resistance dis-
`tribution for both TiSi, salicide and polycide device
`structures at 0.25 pm linewidth is shown in Fig. 12.
`Here, the performance improvement for the polycide
`structure must be balanced against the additional
`process complexity of the gate stack.
`
`CMOS technology [2] These results highlight the
`application of mixed X-ray/DUV lithography for evalu-
`ation of 2 0 0 ” process integration for 0.15pm LE,
`CMOS devices.
`
`SUMMARY
`
`In summary, we have used X-ray lithography for
`the gate level to enable fabrication of CMOS devices
`with 0.15 pm nominal effective channel length, inte-
`grated with shallow trench isolation using 0.35 pm
`design rules in a 200”
`process targeted for operation
`with a scaled power supply of 1.8 V. This technology
`provides about SO% performance improvement relative
`to a 2.5V, 0.5 pm design rule, 0.25 pm LEFF CMOS
`technology [2].
`This technology is suitable for
`high-end microprocessors with embedded high-speed
`SRAM cache.
`
`ACKNOWLEDGEMENTS
`
`IUM
`the
`like to thank
`The authors would
`Advanced Silicon Technology Center (ASTC) and
`Advanced Lithography Facility (ALF) for the X-Ray
`lithography processing and for processing and fabri-
`cating these devices. We would also like to thank Bijan
`Davari for his help and support, Robin Assenza,
`Debbie Ryan, and Dave Robertson for technical assia-
`tance, and David Narame for helpful discussions, Ths
`work was partially funded by ARPA and administered
`by NAVAIR (contract number N00019-91-C-0207).
`
`REFERENCES
`
`+ On business leave of absence to LOKAL, FSC.
`[l.] G. Shahidi et al., “A High-Performance 0.15 pm
`CMOS”, 1993 Symp. VLSI Tech. Dig. Tech. Papers,
`pp. 93-94 (1993).
`C2.1 C. Koburger et al., ”Simple, Fast, 2.5 V CMOS
`Logic with 0.25 pm Channel Lengths and Damascene
`Interconnect”, 1994 Symp. VLSI Tech. Dig. Tech.
`Papers, pp. 85-86 (1994).
`[3.] F. White et al., ”Damascene Stud Local Intercon-
`nect in CMOS Technology“, Tech. Digest IEDM, pp.
`301-304 (1992).
`[4.] B. Davari et al., “A New Planarization Technique
`Using a Combination of RIE and Chemical-Mechan-
`ical Polish (CMP)”, Tech. Digest IEDM, pp. 61-64
`(1989).
`[S.] R. Dennard at al., ”Design of Ion-Implanted
`MOSFETs with Very Small Physical Dimensions”,
`IEEE J. Solid-state Ccts, SC-9, pp. 256-268 (1974).
`
`The delay vs. supply voltage behavior shown in Figure
`13 for both standard CMOS and pass-transistor logic
`gates demonstrate the low-voltage and low-power per-
`formance potential for this technology.
`Figure 14
`shows the delay for unloaded (FI= FO= 1, CL = 0)
`and loaded (FI=1;0=3, C, = 165fF) ring oscillators
`as a function of channel length. The minimum delays
`of 30 ps unloaded and 150 ps loaded at 1.8V represent
`about 50% performance improvement relative to a
`state-of-the-art 2.5 V, 0.25 pm LEFF high-performance
`28.8.2
`
`696-IEDM 94
`
`Page 2 of 4
`
`

`

`Table 1. S E M Da
`
`8 chips per wafer
`
`200nm
`200Nn
`
`2 0 0 m
`zoom
`2 0 0 m
`200nm
`
`10
`16
`18
`20
`
`-
`
`Scale:
`
`0 . l U I
`
`Fig. 1. SEM image of 0.20um features
`in l.0um APEX.
`
`Table I. Image CD data summary for
`0.125 pm and 0.20 pm features.
`
`Fig. 2. Overlay vectors XRAY/DUV
`mix-and-match.
`
`Fig. 3. SEM showing 0.2-
`gates
`crossing over STI to silicon (with 0.12
`pm spacer).
`
`Fig. 4. Cross-section TEM of com-
`pleted 0.20 pm L,+,As~ device.
`
`0.00
`
`0.15 0.20
`0.05
`0.10
`0.25
`Electrlcal channel length, pm
`Fig. 5. Eleckical channel-length dis-
`tribution (20 chips, across wafer).
`
`0.30
`
`.I1
`
`f F
`
`U
`
`-4
`
`-3.5 3 -2.5
`
`-2
`
`-1.5
`
`-1
`
`-0.5 0
`
`!lAllLJ
`
`tAIpmz
`Log(Current Denslty],
`-2
`-4
`Fig. 6. Gate oxide leakage histograms
`for N (top) and P (bottom) capacitors.
`
`l@' 7 - 7 --
`
`Eleetrlcll Chnnsl Lmglh (pm)
`
`10'6
`
`1wO
`
`Dapth $,%".)
`Fig. 7. S l M S profiles of N-extension
`(top) and P-extension (bottom).
`
`4o00
`
`111
`
`1 1 1
`
`I d >
`
`I S I "
`
`111
`1 1 1
`I 1 4
`111
`111
`l i t
`Electrical Channel Length (pm)
`Fig. 8(a). Threshold voltage as a func-
`tion of channel length for NFETs (top)
`and PFETs (bottom)
`
`28.8.3
`
`IEDM 94-697
`
`Page 3 of 4
`
`

`

`0
`
`5
`4
`3
`2
`1
`Log[Cumnl Density], Wpm,
`
`s
`
`
`
`-
`
`4
`3
`2
`1
`0
`1
`Log[Cumnt Density], fA/pm?
`
`5
`
`
`
`Fig. 9. Junction leakage histogram for
`N-junction
`
`Fig. 10.
`Junction leakage histogram
`for P-junction.
`
`0 1
`
`6 7 8 9 10
` 3 4
`5
`2
`sheet RIsIstance (n /sq.)
`Fig. 12(a). Gate conductor Sheet
`resistance for 0.25 pm Salicide lines.
`
`0 1
`
` 3 4 5 6 7 8 9 10
`2
`Sheet Reststance (n /sq.)
`Fig. 12(b). Gate conductor Sheet
`resistance for 0.25 pm Polycide lines.
`
`PET On-Current
`
`Fig. 1 I . Off currcnt as a function of
`for NFETs
`on-current
`(top) and
`PFETs (bottom).
`
`8007-
`
`0
`
`U
`
`251
`o
`
`b
`
`o
`
`o
`
`o
`
`g
`o
`
` 5 g 2 2 -
`
`o
`o
`NfET L d l (um)
`
`o
`
`o
`
`c
`
`
`
`Fig. 13.
`Ring-oscillator delay for
`standard and pass-transistor logic ring
`c
`oscillators.
`
`Fig. I4(a). Ring-oscillator delay for
`unloaded inverters (FI = FO = 1)
`
`28.8.4
`
`698-IEDM 94
`
`NFET L d i (um)
`
`Fig. 14(b). Ring-oscillator delay for
`loaded
`gates
`(2-way
`NAND,
`F l = F O = 3 , CL = 165 fF).
`
`Page 4 of 4
`
`