Structural Analysis
`Sample Report
`
`Overview and Layout Analysis – Excerpt from 45 nm Process Technology
`Process Analysis – Excerpt from 45 nm Process Technology
`SRAM Analysis – Excerpt from SOI 45 nm Process Technology
`Materials Analysis – Excerpt from SOI 45 nm Process Technology
`Critical Dimensions – Excerpt from 90 nm Process Technology
`
`For any additional technical needs concerning semiconductor and electronics technology,
`please call Sales at Chipworks.
`
`3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
`
`Page 1 of 161
`
` IP Bridge Exhibit 2026
` TSMC v. IP Bridge
` IPR2016-01246
`
`

`

`Structural Analysis
`Sample Report
`
`Overview and Layout Analysis – Excerpt from 45 nm Process Technology
`Process Analysis – Excerpt from 45 nm Process Technology
`SRAM Analysis – Excerpt from SOI 45 nm Process Technology
`Materials Analysis – Excerpt from SOI 45 nm Process Technology
`Critical Dimensions – Excerpt from 90 nm Process Technology
`
`For any additional technical needs concerning semiconductor and electronics technology,
`please call Sales at Chipworks.
`
`3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
`
`Page 2 of 161
`
`

`

`Structural Analysis – Sample Report
`Structural Analysis
`
`Table of Contents
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`Overview
`1.1 List of Figures
`1.2 List of Tables
`1.3 Introduction
`1.4 Device Summary
`1.5 Process Summary
`
`Device Overview
`2.1 Package and Die
`2.2 Die Features
`2.3 Die Utilization
`2.4 Selected Layout Features
`
`Process Analysis
`3.1 General Structure
`3.2 Dielectrics
`3.3 Metallization
`3.4 Vias and Contacts
`3.5 Logic MOS Transistors
`3.6 Isolation
`3.7 Wells and Substrate
`
`High Density (HD) 6T SRAM Analysis
`4.1 HD 6T SRAM Schematic and Layout Analysis
`4.2 HD 6T SRAM Cross-Section Analysis
`
`Materials Analysis
`5.1 TEM-EDS Analysis of BEOL Dielectrics
`5.2 TEM-EDS Analysis of MIM Capacitor
`5.3 TEM-EDS Analysis of BEOL Metallization and Contacts
`5.4 TEM-EDS Analysis of Transistors, SOI, and BOX
`
`Critical Dimensions
`6.1 Horizontal Dimensions
`6.2 Vertical Dimensions
`
`Statement of Measurement Uncertainty and Scope Variation
`
`About Chipworks
`
`Page 3 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-1
`
`1 Overview
`1.1 List of Figures
`2
`Device Overview
`2.1.1
`Package on PCB
`2.1.2
`Package Top
`2.1.3
`Package Bottom
`2.1.4
`Package X-Ray
`2.1.5
`Die Photograph
`2.1.6
`Die Markings
`2.1.7
`Analysis Sites
`2.2.1
`Die Corner A
`2.2.2
`Die Corner B
`2.2.3
`Die Corner C
`2.2.4
`Die Corner D
`2.2.5
`Detail of Die Corner A
`2.2.6
`Detail of Die Corner B
`2.2.7
`Detail of Die Corner C
`2.2.8
`Detail of Die Corner D
`2.2.9
`Bond Pads
`2.3.1
`Die Functional Blocks
`2.3.2
`Area 1
`2.3.3
`Area 2
`2.3.4
`Area 3
`2.3.5
`Area 4
`2.4.1
`Standard Logic at Metal 1
`2.4.2
`Detail of Standard Logic Cells at Metal 1
`2.4.3
`Overview of Standard Logic at Poly
`2.4.4
`Standard Logic at Poly – Wide Gates
`2.4.5
`Standard Logic – Standard Cell Size and Dummy Poly
`3
`Process Analysis
`3.1.1
`General Structure
`3.1.2
`Die Thickness
`3.1.3
`Die Edge Seal
`3.2.1
`Dielectric Stack Overview
`3.2.2
`Passivation and ILD 8
`3.2.3
`ILD 6 and ILD 7
`3.2.4
`ILD 7 – TEM
`3.2.5
`ILD 3, ILD 4, and ILD 5
`3.2.6
`TEM of ILD 5 – TEM
`3.2.7
`ILD 4 – TEM
`3.2.8
`ILD 3 – TEM
`3.2.9
`ILD 2 – TEM
`3.2.10
`ILD 1 – TEM
`
`Page 4 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-2
`
`3.2.11 PMD Overview
`3.2.12 PMD – TEM
`3.2.13 TEM-EDS Spectrum of Passivation
`3.2.14 TEM-EDS Spectra of ILD 7-4 and ILD 7-5
`3.2.15 TEM-EDS Spectra of ILD 7-1 through ILD 7-3
`3.2.16 TEM-EDS Spectra of ILD 5
`3.2.17 TEM-EDS Spectra of ILD 1
`3.2.18 TEM-EDS Spectra of PMD
`3.3.1
`Minimum Pitch Metal 9
`3.3.2
`Metal 9
`3.3.3
`Metal 9 Barrier – TEM
`3.3.4
`Minimum Pitch Metal 8
`3.3.5
`Metal 8 Liner – TEM
`3.3.6
`Minimum Pitch Metal 6
`3.3.7
`Metal 6 Liner – TEM
`3.3.8
`Minimum Pitch Metal 3 and 5
`3.3.9
`Metal 3 Liner – TEM
`3.3.10 Minimum Pitch Metal 2 and 4
`3.3.11 Metal 2 Liner – TEM
`3.3.12 Minimum Pitch Metal 1
`3.3.13 Metal 1 Liner
`3.3.14 TEM-EDS Spectrum of Metal 9 Body
`3.3.15 TEM-EDS Spectra of Metal 9 Barrier Layers
`3.3.16 TEM-EDS Spectrum of Metal 1 Barrier
`3.4.1
`Minimum Pitch Via 8s
`3.4.2
`Minimum Pitch Via 7s
`3.4.3
`Minimum Pitch Via 6s
`3.4.4
`Minimum Pitch Via 5s
`3.4.5
`Via 5 – TEM
`3.4.6
`Minimum Pitch Via 3s and 4s
`3.4.7
`Via 4 – TEM
`3.4.8
`Minimum Pitch Via 1s and 2s
`3.4.9
`Via 2s – TEM
`3.4.10 Minimum Pitch Contacts – TEM
`3.4.11 Contact to Poly – TEM
`3.4.12 Top of Contact – TEM
`3.4.13 Bottom of Contact – TEM
`3.4.14 TEM-EDS Spectrum of Contact Liner
`3.4.15 TEM-EDS Spectrum of Contact Silicide
`3.5.1
`Minimum Contacted Gate Pitch
`3.5.2
`NMOS Transistors – Si Etch
`3.5.3
`PMOS Transistors – Si Etch
`3.5.4
`Minimum Gate Length MOS Transistor
`3.5.5
`Minimum Gate Length MOS Transistor – TEM
`
`Page 5 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-3
`
`Gate Dielectric – TEM
`3.5.6
`3.5.7 Wide and Narrow Gate Length Transistors – TEM
`3.5.8
`Gate Dielectric Overview – TEM
`3.5.9
`Poly Thickness – TEM
`3.5.10 Poly Gate Wrap – TEM
`3.5.11
`TEM-EDS Spectrum of Gate Silicide
`3.6.1
`Minimum Width STI – TEM
`3.6.2
`STI Thickness – TEM
`3.6.3
`STI Beneath Poly – TEM
`3.7.1
`SCM of Wells and Substrate
`3.7.2
`SCM of N-Well
`3.7.3
`SCM of Embedded P-Well
`3.7.4
`TEM Diffraction Pattern – Si Channel Region
`3.7.5
`TEM-EDS Spectrum of Si Substrate
`4
`High Density (HD) 6T SRAM Analysis
`4.1.1
`HD 6T SRAM Schematic
`4.1.2
`HD 6T SRAM at Metal 3
`4.1.3
`HD 6T SRAM at Via 2s
`4.1.4
`HD 6T SRAM at Metal 2
`4.1.5
`HD 6T SRAM at Via 1s
`4.1.6
`HD 6T SRAM at Metal 1
`4.1.7
`HD 6T SRAM at Poly
`4.1.8
`HD 6T SRAM at Active Silicon
`4.2.1
`TEM Overview of NMOS Access and Pull-Down Transistors
`4.2.2
`TEM of NMOS Transistor (T2 or T6)
`4.2.3
`TEM Overview of PMOS Pull-Up Transistor
`4.2.4
`TEM of PMOS Pull-Up Transistor
`4.2.5
`TEM of SRAM Transistor Gate Dielectric
`5
`Materials Analysis
`5.1.1
`TEM-EDS Spectrum of ILD 10-3
`5.1.2
`TEM-EDS Spectrum of ILD 9-2 (ILD 10-2)
`5.1.3
`TEM-EDS Spectrum of ILD 9-3
`5.1.4
`TEM-EDS Spectrum of ILD 8-1 (ILD 9-1, ILD 10-1)
`5.1.5
`TEM-EDS Spectrum of ILD 8-5
`5.1.6
`TEM-EDS Spectrum of ILD 8-4
`5.1.7
`TEM-EDS Spectrum of ILD 8-2, ILD 8-3
`5.1.8
`TEM-EDS Spectrum of ILD 4-2 (ILD 5-2, ILD 6-2, ILD 7-2)
`5.1.9
`TEM-EDS Spectrum of ILD 4-1 (ILD 5-1, ILD 6-1, ILD 7-1)
`5.1.10 TEM-EDS Spectrum of ILD 1-2 (ILD 2-2, ILD 3-2)
`5.1.11
`TEM-EDS Spectrum of ILD 1-1 (ILD 1-2, ILD 1-3)
`5.1.12 TEM-EDS Spectrum of PMD 3
`5.1.13 TEM-EDS Spectrum of PMD 1/PMD 2
`
`Page 6 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-4
`
`5.2.1
`5.2.2
`5.2.3
`5.2.4
`5.3.1
`5.3.2
`5.3.3
`5.3.4
`5.3.5
`5.3.6
`5.3.7
`5.4.1
`5.4.2
`5.4.3
`5.4.4
`5.4.5
`5.4.6
`5.4.7
`
`TEM-EDS Spectrum of Capacitor Hard Mask
`TEM-EDS Spectrum of Capacitor Plates
`TEM-EDS Spectrum of MIM Capacitor Dielectric
`TEM-EDS Spectrum of Pre-capacitor Dielectric
`TEM-EDS Spectrum of UBM
`TEM-EDS Spectrum of Metal 11 Body
`TEM-EDS Spectrum of Metal 11 Ta-based Barrier
`TEM-EDS Spectrum of Metal 11 Ti-based Barrier
`TEM-EDS Spectrum of Metal 10 Body
`TEM-EDS Spectrum of Metal 1 Liner
`TEM-EDS Spectrum of Contact Liner
`TEM-EDS Spectrum of Gate Silicide
`TEM-EDS Spectrum of Diffusion Silicide
`TEM-EDS Spectrum of NMOS Stress Liner
`TEM-EDS Spectrum of PMOS Stress Liner
`TEM-EDS Spectrum of PMOS eSiGe
`TEM-EDS Spectrum of SOI (Channel Region)
`TEM-EDS Spectrum of BOX
`
`1.2 List of Tables
`1
`Overview
`1.3.1
`Device Identification
`1.4.1
`Device Summary
`1.5.1
`Process Summary
`2
`Device Overview
`2.1.1
`Package and Die Dimensions
`2.3.1
`Die Utilization
`3
`Process Analysis
`3.2.1
`Measured Dielectric Thicknesses
`3.3.1
`Metallization – Vertical Dimensions
`3.3.2
`Metallization – Horizontal Dimensions
`3.4.1
`Via and Contact Horizontal Dimensions
`3.5.1
`MOS Transistor Horizontal Dimensions
`3.5.2
`MOS Transistor Vertical Dimensions
`3.6.1
`Observed Isolation Dimensions
`3.7.1
`Die Thickness and Well Depths
`4
`High Density (HD) 6T SRAM Analysis
`4.2.1
`6T SRAM Transistor Sizes
`6
`Critical Dimensions
`6.1.1
`Minimum Pitch Metals
`6.1.2
`Contacts and Vias
`6.1.3
`Transistors, Poly, and Isolation
`6.2.1
`Vertical Dimensions
`
`Page 7 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-5
`
`1.3 Introduction
`This report is a structural analysis of the 45 nm XXXX extracted from the XXXX
`Blu Ray DVD recorder. The part uses multi decoding technology, which is capable
`of simultaneously processing two screens of full-HD, and MPEG-4 AVC/H.264
`encoding technology. This technology compresses a full-HD image into 1/2 to 1/3
`its original size, compared with conventional technology.
`
`XXXX developed their 45 nm process in their fab in conjunction with XXXX. The
`process is reported to use 193 nm immersion lithography, stress-induced,
`mobility-enhanced transistors, low-k dielectrics, and design-for-manufacturability
`(DFM) techniques.
`
`The XXXX is fabricated using a nine metal 45 nm CMOS process, featuring 32 nm
`minimum gate length MOS transistors. The part features “intermediate-k”
`dielectrics for the upper level dielectrics, and true low-k dielectrics for the lower
`level dielectrics. While XXXX has reported the use of strain engineering, we do
`not see (through reverse engineering techniques) any mechanism for applying
`strain. It is possible that the thin (~0.01 µm) oxynitride contact etch stop layer
`(CESL) is used to apply tensile strain for NMOS. This is, however, much thinner
`than the silicon nitride we have seen used for applying tensile strain on other
`devices (at the 65 nm node). It is possible that now, with such a small gate length,
`XXXX is able to apply strain with such a thin film.
`
`XXXX has migrated to using rotated wafers for the 45 nm node. The transistors on
`the XXXX are oriented with their channels in the <100> direction, as opposed to
`the more conventional <110> orientation. This technique increases the drive
`current of the PMOS transistors.
`
`Five different sizes of 6T SRAM are used, the smallest having a unit cell size of
`0.34 µm2. The 6T SRAM uses a uni-directional poly layout, with butted contacts
`used to reduce the cell size. 8T SRAM is used with a 0.63 µm2 unit cell size. The
`part also uses ROM memory.
`
`To date (January 2008), Chipworks has analyzed just one other die fabricated
`using a 45 nm process, the XXXX die.
`
`Page 8 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-6
`
`This report contains the following detailed information:
`• Package photographs, package x-ray, die markings, and die features
`• Die utilization analysis, including an annotated gate level die photograph and
`functional block measurements
`• SEM and transmission electron microscopy (TEM) analysis of the dielectrics,
`metals, vias and contacts, transistors, isolation and major structural features,
`and measurement of the horizontal and vertical critical dimensions of the die
`TEM-EDS analysis of the dielectrics, metals, and transistors
`•
`• Scanning capacitance microscopy (SCM) analysis of the wells and substrate
`• Embedded memory analysis, including bevel images of the 6T SRAM and
`block layout images of the various memory arrays
`All the information was derived by Chipworks from two samples with the
`following markings:
`
`Table 1.3.1
`
`Device Identification
`
`1.3.1 Device Identification
`
`Package markings
`Die markings
`Date code
`
`XXXX
`XXXX
`XXXX
`Table 1.3.1 Device Identification
`1.4 Device Summary
`
`Table 1.4.1
`
`Device Summary
`
`1.4.1 Device Summary
`
`Manufacturer
`Foundry
`Part number
`Type
`Date code
`Package markings
`Package type
`Die markings
`Die size (die edge seal)
`Process type
`Number of metal layers
`Number of poly layers
`Minimum transistor gate length
`Process generation
`Feature measured to determine
`process generation
`
`XXXX
`XXXX
`XXXX
`System LSI
`740 (week 40 of 2007)
`XXXX
`BGA
`XXXX
`8.42 mm x 8.14 mm (65.5 mm2)
`CMOS
`9
`1
`32 nm
`45 nm
`Transistor gate lengths, metal 1 pitch,
`SRAM cell size
`Table 1.4.1 Device Summary
`
`Page 9 of 161
`
`

`

`Structural Analysis – Sample Report
`Overview
`
`1-7
`
`1.5 Process Summary
`
`Table 1.5.1
`
`Process Summary
`
`1.5.1 Process Summary
`
`Passivation
`Dielectrics
`
`Single layer of silicon nitride
`ILD 8 uses oxide and oxynitride films
`ILD 6 and ILD 7 use oxide/FSG line dielectrics, SiON metal etch
`stop, oxide via dielectric, SiON Cu sealant
`ILD 5 uses FSG line dielectric, oxide via dielectric, SiCNO Cu
`sealant
`ILD 1 through ILD 4 use SiOC low-k line, via dielectrics, and
`SiCNO Cu sealant
`PMD uses SiOC line dielectric, oxide contact dielectric and
`SiON contact etch stop layer (CESL)
`Metallization Top level Al uses TiN/Ti barrier
`Metal 2 through metal 8 are dual damascene Cu with Ta-based
`liners
`Metal 1 is single damascene Cu with a Ta-based liner
`Via 8s are Al filled
`Via 1s through via 7s are Cu filled
`Contacts are W with TiN liner
`Single level of Ni silicide polysilicon
`36 nm minimum gate length
`Ni silicided transistor gates and diffusions (no Pt doping)
`Transistors oriented with their channels in the <100> direction
`Possible use of nitride strain for NMOS transistors
`0.10 µm minimum width shallow trench isolation (STI)
`Twin-wells in a P-epi
`P-type substrate
`Wafer rotated to provide <100> transistor channel orientation
`Five different sizes of 6T SRAM used
`Smallest 6T SRAM has a unit cell size of 0.37 µm x 0.93 µm
`(0.34 µm2)
`8T SRAM used with a 0.63 µm2 unit cell size.
`ROM used with a unit cell size of 0.20 µm x 0.26 µm (0.05 µm2)
`45 nm
`
`Vias and
`contacts
`
`Polysilicon
`Transistor
`
`Isolation
`Wells
`Substrate
`
`Embedded
`memory
`
`Process
`generation
`
`Table 1.5.1 Process Summary
`
`Page 10 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-1
`
`2 Device Overview
`2.1 Package and Die
`The XXXX used for this analysis was removed from a XXXX Blu Ray DVD Recorder.
`Figure 2.1.1 shows the part as mounted on the printed circuit board (PCB).
`
`Figure 2.1.1Package on PCB
`Figure 2.1.1 Package on PCB
`
`Figure 2.1.1 Package on PCB
`
`Page 11 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-2
`
`Top and bottom photographs of the XXXX package are shown in Figure 2.1.2 and
`Figure 2.1.3, respectively. The package markings include:
`
`XXXX
`
`The XXXX was sold under XXXX consumer electronics XXXX brand.
`
`Figure 2.1.2Package Top
`Figure 2.1.2 Package Top
`
`Figure 2.1.2 Package Top
`
`Page 12 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-3
`
`Figure 2.1.3Package Bottom
`Figure 2.1.3 Package Bottom
`
`Figure 2.1.3 Package Bottom
`
`Page 13 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-4
`
`A plan-view x-ray photograph of the XXXX is shown in Figure 2.1.4. Conventional
`wire bonding is used to connect the die to the package lands.
`
`Figure 2.1.4Package X-Ray
`Figure 2.1.4 Package X-Ray
`
`Figure 2.1.4 Package X-Ray
`
`Page 14 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-5
`
`Figure 2.1.5 shows a photograph of the decapsulated XXXX die extracted from
`the XXXX. The die measures 8.42 mm x 8.14 mm from the die seals, or
`8.45 mm x 8.17 mm for the whole die. The die area is 65.5 mm2 (die seals).
`A double row of bond pads is visible around the periphery of the die. The die is
`300 µm thick.
`
`Figure 2.1.5Die Photograph
`Figure 2.1.5 Die Photograph
`
`Figure 2.1.5 Die Photograph
`
`Page 15 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-6
`
`The 2WS0038 die markings are shown in Figure 2.1.6.
`
`Figure 2.1.6Die Markings
`Figure 2.1.6 Die Markings
`
`Figure 2.1.6 Die Markings
`
`Page 16 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-7
`
`Figure 2.1.7 is a die photograph annotated to show the regions of the die
`analyzed by SEM, SCM, TEM, and bevel analysis.
`
`Figure 2.1.7Analysis Sites
`Figure 2.1.7 Analysis Sites
`
`bevel
`
`P1AS1 (SEM)
`
`P1AS2 (SEM, SCM)
`
`TEM
`
`TEM
`
`Figure 2.1.7 Analysis Sites
`
`Page 17 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-8
`
`The dimensions of the XXXX package and die are summarized in Table 2.1.1.
`
`Table 2.1.1
`
`Package and Die Dimensions
`
`2.1.1 Package and Die Dimensions
`
`Feature
`Package size
`Die size (edge seal)
`Die area (edge seal)
`Die thickness
`Bond pad size
`Minimum bond pad pitch
`NAND cell
`
`Size
`35.0 mm x 35.0 mm x 1.75 mm
`8.42 mm x 8.14 mm
`65.5 mm2
`300 µm
`68 µm x 101 µm
`70 µm
`0.37 µm x 1.41 µm (0.52 µm2)
`Table 2.1.1 Package and Die Dimensions
`
`Page 18 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-9
`
`2.2 Die Features
`Figure 2.2.1 through Figure 2.2.8 show the four corners of the XXXX die, at low
`and high magnification. The metal die seal structure runs along the perimeter of
`the die, just inside the scribe lane.
`
`Figure 2.2.1Die Corner A
`Figure 2.2.1 Die Corner A
`
`Figure 2.2.1 Die Corner A
`
`Figure 2.2.2Die Corner B
`Figure 2.2.2 Die Corner B
`
`Figure 2.2.2 Die Corner B
`
`Page 19 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-10
`
`Figure 2.2.3Die Corner C
`Figure 2.2.3 Die Corner C
`
`Figure 2.2.3 Die Corner C
`
`Figure 2.2.4Die Corner D
`Figure 2.2.4 Die Corner D
`
`Figure 2.2.4 Die Corner D
`
`Page 20 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-11
`
`Figure 2.2.5Detail of Die Corner A
`Figure 2.2.5 Detail of Die Corner A
`
`Figure 2.2.5 Detail of Die Corner A
`
`Figure 2.2.6Detail of Die Corner B
`Figure 2.2.6 Detail of Die Corner B
`
`alignment mark
`
`Figure 2.2.6 Detail of Die Corner B
`
`Page 21 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-12
`
`Figure 2.2.7Detail of Die Corner C
`Figure 2.2.7 Detail of Die Corner C
`
`Figure 2.2.7 Detail of Die Corner C
`
`Figure 2.2.8Detail of Die Corner D
`Figure 2.2.8 Detail of Die Corner D
`
`Figure 2.2.8 Detail of Die Corner D
`
`Page 22 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-13
`
`Two rows of 70 µm pitch bond pads are present around the edge of the die, as
`shown in Figure 2.2.9. The bond pads are 68 µm x 101 µm large in size.
`
`Figure 2.2.9Bond Pads
`Figure 2.2.9 Bond Pads
`
`70 µm
`
`bond pad
`
`101 µm
`
`68 µm
`
`95 µm
`
`62 µm
`
`Figure 2.2.9 Bond Pads
`
`Page 23 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-14
`
`2.3 Die Utilization
`Figure 2.3.1 shows a poly die photo, annotated to show the functional blocks
`identified through microscopic observation. The functional block sizes are listed
`in Table 2.3.1. Analyses of the memory cell blocks are presented in Section X.
`
`Figure 2.3.1Die Functional Blocks
`Figure 2.3.1 Die Functional Blocks
`
`area 4
`
`area 5
`
`area 1
`
`area 2
`
`area 3
`
`Table 2.3.1
`
`Die Utilization
`
`area 6
`
`1.0 mm
`
`Figure 2.3.1 Die Functional Blocks
`
`Page 24 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`Functional Block
`
`Area 1
`(serial interface port)
`Area 2
`(serial interface port
`reference)
`Area 3 (communications
`interface port)
`Area 4
`(video/audio interface port)
`Area 5
`(DDR2 interface ports)
`Area 6
`(DDR2 interface ports)
`Die size
`
`Length
`(mm)
`1.19
`
`2.3.1 Die Utilization
`
`Width
`(mm)
`0.82
`
`Area
`(mm2)
`1.0
`
`1.31
`
`0.92
`
`0.57
`
`0.81
`
`0.83
`
`5.17
`
`8.14
`
`0.67
`
`0.64
`
`5.17
`
`0.83
`
`8.42
`
`1.2
`
`0.4
`
`0.5
`
`4.3
`
`4.3
`
`65.5
`
`Table 2.3.1 Die Utilization
`
`2-15
`
`Percentage
`
`2%
`
`2%
`
`1%
`
`1%
`
`7%
`
`7%
`
`–
`
`Page 25 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-16
`
`Detailed images of the area 1 through area 4 blocks are shown in Figure 2.3.1
`through Figure 2.3.5. The area 5 and area 6 are two identical DDR2 interface
`ports, each supporting eight external DDR2 memory chips.
`
`Figure 2.3.2 shows the area 1 block at poly. Area 1 is likely a serial interface port
`(Firewire) which has nine serial transceivers, including two transceivers with
`larger sizes.
`
`Figure 2.3.2Area 1
`Figure 2.3.2 Area 1
`
`0.2000 m m
`
`Figure 2.3.2 Area 1
`
`Page 26 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-17
`
`Figure 2.3.3 shows the area 2 block at poly. Area 2 has analog circuits, probably
`providing reference for the serial interface port of area 1.
`
`Figure 2.3.3Area 2
`Figure 2.3.3 Area 2
`
`0 .2000 m m
`
`Figure 2.3.3 Area 2
`
`Page 27 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-18
`
`Figure 2.3.4 shows the area 3 block at poly. Area 3 is likely a communication
`interface port such as USB.
`
`Figure 2.3.4Area 3
`Figure 2.3.4 Area 3
`
`0. 2000 m m
`
`Figure 2.3.4 Area 3
`
`Page 28 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-19
`
`Figure 2.3.5 shows the area 4 block at poly. Area 4 is likely a five-channel video/
`audio interface port, which includes five identical transmitters implemented with
`current-steering DAC’s.
`
`Figure 2.3.5Area 4
`Figure 2.3.5 Area 4
`
`0 .2000 m m
`
`Figure 2.3.5 Area 4
`
`Page 29 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-20
`
`2.4 Selected Layout Features
`A delayered sample, prepared for the memory cell analyses presented in Section
`X, was inspected to determine the use of dummy metal and poly structures.
`
`Figure 2.4.1 shows an overview of the standard logic at metal 1. The unused
`spaces between active interconnect lines are left unfilled (no dummy metal used).
`
`Figure 2.4.1Standard Logic at Metal 1
`Figure 2.4.1 Standard Logic at Metal 1
`
`M1 Cu
`
`residual ILD
`
`Figure 2.4.1 Standard Logic at Metal 1
`
`Page 30 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-21
`
`Figure 2.4.2 shows a detailed view of the metal 1 patterning over the standard
`logic cells.
`
`Figure 2.4.2Detail of Standard Logic Cells at Metal 1
`Figure 2.4.2 Detail of Standard Logic Cells at Metal 1
`
`residual ILD
`
`M1 Cu
`
`Figure 2.4.2 Detail of Standard Logic Cells at Metal 1
`
`Page 31 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-22
`
`Figure 2.4.3 is an overview of the corner of a block of standard logic. Several rows
`of dummy poly surround the logic block.
`
`Figure 2.4.3Overview of Standard Logic at Poly
`Figure 2.4.3 Overview of Standard Logic at Poly
`
`logic poly
`
`dummy poly
`
`Figure 2.4.3 Overview of Standard Logic at Poly
`
`Page 32 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-23
`
`Figure 2.4.4 shows several rows of standard logic. Both minimum gate length and
`wide gate transistors are used. Dummy poly lines fill the unused space between
`functional groupings of logic gates.
`
`Figure 2.4.4Standard Logic at Poly – Wide Gates
`Figure 2.4.4 Standard Logic at Poly – Wide Gates
`
`dummy poly
`
`wide gate
`
`logic poly
`
`Figure 2.4.4 Standard Logic at Poly – Wide Gates
`
`Page 33 of 161
`
`

`

`Structural Analysis – Sample Report
`Device Overview
`
`2-24
`
`Figure 2.4.5 shows a detailed view of the equivalent area occupied by a NAND
`cell. A typical NAND cell would be 0.38 µm wide by 1.41 µm high, yielding a
`0.54 µm2 cell. Dummy poly is used on each end of the logic cells.
`
`Figure 2.4.5Standard Logic – Standard Cell Size and Dummy Poly
`Figure 2.4.5 Standard Logic – Standard Cell Size and Dummy Poly
`
`dummy poly
`
`0.38 µm
`
`1.41 µm
`
`Figure 2.4.5 Standard Logic – Standard Cell Size and Dummy Poly
`
`Page 34 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-1
`
`3 Process Analysis
`3.1 General Structure
`Figure 3.1.1 shows the general structure of the XXXX, which features eight levels
`of Cu metallization plus a top layer of Al.
`
`passivation
`
`1.6 µm
`
`Figure 3.1.1General Structure
`Figure 3.1.1 General Structure
`
`metal 9
`
`metal 8
`
`1.6 µm
`
`4.5 µm
`
`metal 7
`
`1.6 µm
`
`M6
`
`M1
`
`STI
`
`M4
`
`Figure 3.1.1 General Structure
`
`Page 35 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-2
`
`Figure 3.1.2 and Figure 3.1.3 show cross-sectional views of the die. A single, full-
`depth saw cut was used for die singulation. No bevel has been applied to the die
`edge. The finished die is 300 µm thick.
`
`Figure 3.1.2Die Thickness
`Figure 3.1.2 Die Thickness
`
`bond pad
`
`200 µm
`
`die seal
`
`Si die
`
`300 µm
`
`Figure 3.1.2 Die Thickness
`
`Page 36 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-3
`
`Figure 3.1.3 shows the die seal structure. The die seal is comprised of all eight
`levels of Cu, plus the Al bond pad metal. The top portion of the die seal ring was
`etched during our sample depot process.
`
`Figure 3.1.3Die Edge Seal
`Figure 3.1.3 Die Edge Seal
`
`Al, M7, and M8
`etched during
`sample depot
`
`M8
`
`M7
`
`M6
`
`M5
`
`M1M2M3M4
`
`Figure 3.1.3 Die Edge Seal
`
`Page 37 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-4
`
`3.2 Dielectrics
`The XXXX uses conventional oxide, oxynitride and silicon nitride, fluorinated silicate
`glass (FSG) “intermediate-k”, and carbon doped low-k films for the passivation,
`interlevel dielectrics (ILD), and pre-metal dielectric (PMD). A full chemical mechanical
`planarization (CMP) process is used as part of the damascene Cu line formation.
`
`Table 3.2.1 lists the measured dielectric film thicknesses and material compositions,
`as determined by TEM-EDS. We have used the numbering convention such that the
`first film deposited is designated as ILD n-1, followed by ILD n-2, etc. The TEM-EDS
`spectra of the various dielectric films are presented in Figure 3.2.13 through
`Figure 3.2.18.
`
`Table 3.2.1
`
`Measured Dielectric Thicknesses
`
`Layer
`
`Passivation
`ILD 8
`ILD 7
`ILD 6
`ILD 5
`ILD 4
`ILD 3
`ILD 2
`ILD 1
`PMD
`
`3.2.1 Measured Dielectric Thicknesses
`
`Composition
`(Top to Bottom)
`Silicon nitride
`Oxide/oxynitride
`Oxide/FSG/SiON/oxide/SiON
`Oxide/FSG/SiON/oxide/SiON
`FSG/oxide/SiCNO
`SiOC/SiCNO
`SiOC/SiCNO
`SiOC/SiCNO
`SiOC/SiCNO
`SiOC/oxide/oxide/oxide/SiON
`
`Layer Thickness (µm)
`
`0.94
`0.46 (0.21/0.25)
`2.49 (0.44/0.94/0.07/0.92/0.12)
`2.56 (0.48/0.97/0.06/0.94/0.11)
`0.45 (0.19/0.21/~0.05)
`0.20 (0.15/~0.05)
`0.23 (0.18/~0.05)
`0.21 (0.16/~0.05)
`0.21 (0.16/~0.05)
`0.44 (0.08/0.02/0.21/0.12/0.01)
`
`Table 3.2.1 Measured Dielectric Thicknesses
`
`Page 38 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-5
`
`Figure 3.2.1 shows an overview of the dielectric stack. The passivation and ILD 8
`films are comprised of undoped oxide, oxynitride, and silicon nitride.
`
`The thick ILD 6 and ILD 7 layers are comprised of undoped oxide, FSG, and
`oxynitride.
`
`ILD 5 is comprised of undoped oxide, FSG, and SiCNO.
`
`The thin ILD 1 through ILD 4 films are comprised of SiOC and SiCNO low-k
`dielectrics.
`
`The PMD is comprised of undoped oxide, oxynitride, and SiOC.
`
`Figure 3.2.1Dielectric Stack Overview
`Figure 3.2.1 Dielectric Stack Overview
`
`passivation
`ILD 8
`
`ILD 6 and
`ILD 7
`
`0.92 µm
`
`M7
`
`ILD 5
`ILD 1 through ILD 4
`PMD
`
`M9 Al pad metal etched
`during sample depot
`
`M8
`
`M6
`M5M4
`M3M2M1
`
`Figure 3.2.1 Dielectric Stack Overview
`
`Page 39 of 161
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`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-6
`
`Figure 3.2.2 shows the 0.94 µm thick conformal layer of silicon nitride passivation.
`The TEM image of Figure 3.2.4 reveals no sub layers for this film.
`
`The figure also shows the 0.46 µm thick ILD 8. ILD 8-1 is a 0.25 µm thick
`oxynitride, while ILD 8-2 is a 0.21 µm thick undoped oxide.
`
`Figure 3.2.2Passivation and ILD 8
`Figure 3.2.2 Passivation and ILD 8
`
`passivation - silicon nitride
`
`M9 Al
`
`TiN
`
`Ti
`
`0.94 µm
`
`ILD 8-1 - oxide
`ILD 8-2 - oxynitride
`
`0.46 µm
`
`Figure 3.2.2 Passivation and ILD 8
`
`Page 40 of 161
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`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-7
`
`Figure 3.2.3 shows an overview of the 2.49 µm thick ILD 7. ILD 7-1 is a 0.12 µm
`thick oxynitride film used to seal the metal 7 Cu. ILD 7-2 is a 0.92 µm thick
`undoped oxide serving as the via 7 dielectric. A 0.07 µm thick oxynitride, ILD 7-3,
`serves as the metal 8 trench etch stop layer. The metal 8 line dielectric is
`comprised of a 0.94 µm thick FSG (ILD 7-4) and a 0.44 µm thick undoped oxide
`(ILD 7-5).
`
`The underlying ILD 6 has an overall thickness of 2.56 µm, and features the same
`composition as ILD 7.
`
`Figure 3.2.3ILD 6 and ILD 7
`Figure 3.2.3 ILD 6 and ILD 7
`
`passivation - silicon nitride
`
`0.46 µm
`
`M9 Al
`
`ILD 8
`
`M8 Cu
`
`M7 Cu
`
`2.49 µm
`
`ILD 7-5 - oxide
`
`ILD 7-4 - FSG
`ILD 7-3 - SiON
`ILD 7-2 - oxide
`ILD 7-1 - SiON
`ILD 6-5 - oxide
`
`ILD 6-4 - FSG
`ILD 6-3 - SiON
`ILD 6-2 - oxide
`ILD 6-1 - SiON
`
`M6 Cu
`
`2.56 µm
`
`Figure 3.2.3 ILD 6 and ILD 7
`
`Page 41 of 161
`
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`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-8
`
`Figure 3.2.4 shows a TEM image of the ILD 7, ILD 8, and passivation layers.
`
`Figure 3.2.4ILD 7 – TEM
`Figure 3.2.4 ILD 7 – TEM
`
`passivation - silicon nitride
`
`ILD 8-2 - oxide
`
`ILD 8-1 - SiON
`
`ILD 7-5 - oxide
`
`ILD 7-4 - FSG
`
`ILD 7-3 - SiON
`
`ILD 7-2 - oxide
`
`M7 Cu
`
`ILD 7-1 - SiON
`
`Figure 3.2.4 ILD 7 – TEM
`
`Page 42 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-9
`
`Figure 3.2.5 shows an overview of the ILD 3 through ILD 5 layers. ILD 5 uses an
`FSG line dielectric, while the underlying ILD 1 through ILD 4 layers use SiOC line
`and via dielectrics to lower the capacitance between the aggressively pitched
`metal lines used at these levels.
`
`Figure 3.2.5ILD 3, ILD 4, and ILD 5
`Figure 3.2.5 ILD 3, ILD 4, and ILD 5
`
`ILD 6-1 - SiON
`
`ILD 5-3 - FSG
`
`ILD 5-2 - oxide
`
`ILD 5-1 SiCNO
`
`ILD 4-2 - SiOC
`
`ILD 4-1 - SiCNO
`
`ILD 3-2 - SiOC
`
`ILD 3-1 - SiCNO
`
`M6 Cu
`
`M5 Cu
`
`M4 Cu
`
`Figure 3.2.5 ILD 3, ILD 4, and ILD 5
`
`Page 43 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-10
`
`Figure 3.2.6 shows the 0.45 µm thick ILD 5. ILD 5-1 is a 45 nm thick bi-layer of
`SiCNO serving to seal the metal 5 Cu. While these two layers are not resolved in
`Figure 3.2.6, they are delineated for the lower level ILDs as shown in Figure 3.2.7
`through Figure 3.2.9. The two layers likely have different densities, which yield the
`TEM contrast. Their elemental compositions appear to be the same as determined
`by TEM-EDS.
`
`ILD 5-2 is an undoped oxide serving as the via dielectric. ILD 5-3 is an FSG
`serving as the line dielectric.
`
`Figure 3.2.6TEM of ILD 5 – TEM
`Figure 3.2.6 TEM of ILD 5 – TEM
`
`ILD 7-1 - SiON
`
`M6 Cu
`
`ILD 5-3
`FSG
`
`0.45 µm
`
`ILD 5-2 - oxide
`
`ILD 5-1 - SiCNO
`
`45 nm
`
`M5 Cu
`
`Figure 3.2.6 TEM of ILD 5 – TEM
`
`Page 44 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-11
`
`Figure 3.2.7 shows the 0.20 µm thick ILD 4. The bi-layered SiCNO ILD 4-1 is
`about 0.05 µm thick, while the SiOC ILD 4-2 is about 0.15 µm thick. The ILD 1
`through ILD 4 layers are comparable in thickness and feature the same composition.
`
`Figure 3.2.7ILD 4 – TEM
`Figure 3.2.7 ILD 4 – TEM
`
`M5 Cu
`
`M4 Cu
`
`ILD 4-2 SiOC
`
`ILD 4-1 SiCNO
`
`0.20 µm
`
`Figure 3.2.7 ILD 4 – TEM
`
`Page 45 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-12
`
`Figure 3.2.8 shows the 0.23 µm thick ILD 3.
`
`Figure 3.2.8ILD 3 – TEM
`Figure 3.2.8 ILD 3 – TEM
`
`ILD 3-2 SiOC
`
`ILD 3-1 SiCNO
`
`M4 Cu
`
`via 3
`
`0.08 µm
`
`0.03 µm
`
`0.23 µm
`
`M3 Cu
`
`Figure 3.2.8 ILD 3 – TEM
`
`Page 46 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-13
`
`Figure 3.2.9 shows the 0.21 µm thick ILD 2. The two SiCNO layers making up the
`ILD 2-1 are clearly delineated in this image.
`
`Figure 3.2.9ILD 2 – TEM
`Figure 3.2.9 ILD 2 – TEM
`
`M3 Cu
`
`ILD 2-2 SiOC
`
`ILD 2-1 SiCNO
`
`0.21 µm
`
`Figure 3.2.9 ILD 2 – TEM
`
`Page 47 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-14
`
`Figure 3.2.10 shows the 0.21 µm thick ILD 1.
`
`Figure 3.2.10ILD 1 – TEM
`Figure 3.2.10 ILD 1 – TEM
`
`M2 Cu
`
`ILD 1-2 SiOC
`
`0.21 µm
`
`ILD 1-1 - SiCNO
`
`M1 Cu
`
`Figure 3.2.10 ILD 1 – TEM
`
`Page 48 of 161
`
`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-15
`
`Figure 3.2.11 and Figure 3.2.12 are SEM and TEM views of the PMD, respectively.
`PMD 1 is an approximately 0.01 µm thick oxynitride, serving as the contact etch
`stop layer (CESL). PMD 2 is an approximately 0.12 µm thick undoped oxide. PMD 3
`is an approximately 0.21 µm thick undoped oxide. The varied response of PMD 2
`and PMD 3 to our oxide etch suggests PMD 2 may be a CVD oxide while PMD 3
`may be an HDP oxide. PMD 2 and PMD 3 serve as the contact dielectric.
`
`PMD 4 is an undoped oxide, serving as the metal 1 trench etch stop layer. PMD 5
`is an 0.08 µm thick SiOC, serving as the metal 1 line dielectric.
`
`Figure 3.2.11PMD Overview
`Figure 3.2.11 PMD Overview
`
`PMD 5 - SiOC
`
`M1
`
`PMD 4 - oxide
`
`PMD 3 - oxide
`
`0.44 µm
`
`PMD 2 - oxide
`
`PMD 1 - SiON
`
`Figure 3.2.11 PMD Overview
`
`Page 49 of 161
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`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-16
`
`Figure 3.2.12PMD – TEM
`Figure 3.2.12 PMD – TEM
`
`PMD 5
`SiOC
`
`PMD 3
`oxide
`
`PMD 4
`oxide
`
`M1 Cu
`
`0.44 µm
`
`W
`contact
`
`PMD 2
`oxide
`
`poly
`gate
`
`PMD 1 - SiON
`
`NiSi
`
`NiSi
`
`Figure 3.2.12 PMD – TEM
`
`Page 50 of 161
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`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-17
`
`Figure 3.2.13 shows the TEM-EDS spectrum of the silicon nitride passivation.
`
`Figure 3.2.13TEM-EDS Spectrum of Passivation
`Figure 3.2.13 TEM-EDS Spectrum of Passivation
`
`Si
`
`Passivation - silicon nitride
`
`N
`
`800
`
`700
`
`600
`
`500
`
`400
`
`300
`
`200
`
`100
`
`Counts
`
`0
`
`0
`
`1
`
`3
`2
`Energy (keV)
`
`4
`
`5
`
`Figure 3.2.13 TEM-EDS Spectrum of Passivation
`
`Page 51 of 161
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`

`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-18
`
`Figure 3.2.14 shows the TEM-EDS spectra of the ILD 7-4 FSG and ILD 7-5
`undoped oxide. These spectra are representative of the ILD 6-4 and 6-5 layers.
`
`Figure 3.2.14TEM-EDS Spectra of ILD 7-4 and ILD 7-5
`Figure 3.2.14 TEM-EDS Spectra of ILD 7-4 and ILD 7-5
`
`Si
`
`ILD 7-5 - oxide
`ILD 7-4 - FSG
`
`3
`2
`Energy (keV)
`
`4
`
`5
`
`O
`
`F
`
`1
`
`700
`
`600
`
`500
`
`400
`
`300
`
`200
`
`100
`
`0
`
`0
`
`Counts
`
`Figure 3.2.14 TEM-EDS Spectra of ILD 7-4 and ILD 7-5
`
`Page 52 of 161
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`

`Structural Analysis – Sample Report
`Process Analysis
`
`3-19
`
`Figure 3.2.