412
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 8, AUGUST 1993
`
`The Current-Carrying Corner Inherent to
`Trench Isolation
`
`Andres Bryant, Member, ZEEE, W. Haensch, S. Geissler, Jack Mandelman, Member, ZEEE,
`D. Poindexter, and M. Steger
`
`this paper it is shown for the first time how the
`Abstract-In
`characteristics of the comer MOSFET inherent to trench isola-
`tion can be extracted from hardware measurements and how the
`comer device must be taken into account when extracting MOS-
`FET channel characteristics. For NFET's it is found that the
`comer's threshold voltage, substrate sensitivity, and sensitivity
`to well doping are all smaller than the channel's. The results
`imply that for low standby power logic applications requiring
`high performance, it may become necessary to locally control the
`well doping at the corner. However, the corner's reduced sub-
`strate sensitivity and width independence can provide a signifi-
`cant advantage in a DRAM cell.
`
`I. INTRODUCTION
`OCOS has been the traditional choice for isolation
`
`L between devices in past MOSFET technologies [ 13.
`
`However, as feature sizes are scaled down, trench isola-
`tion becomes a more desirable option because it elimi-
`nates the LOCOS bird's beak and is fully planar with the
`silicon surface (as indicated in the insert in Fig. 2) [2]-[41.
`Inherent to this geometry are fringing gate fields that
`enhance carrier inversion within the silicon corner at the
`isolation edge. As a consequence, there exists a low
`threshold voltage (V,) path at the silicon corner that
`conducts in parallel with the MOSFET channel region
`[41-[81. This parallel current-carrying corner device be-
`comes the dominant MOSFET contributor to standby
`current in low standby power logic applications and to
`leakage in DRAM cells. The corner device can even
`dominate on-currents in applications such as DRAM that
`require narrow channel widths to achieve high density.
`Furthermore, there exists concern that the enhanced elec-
`tric fields due to field crowding at the corner impact
`dielectric integrity. Hence, there is an immediate need to
`understand the corner device as we presently develop the
`ULSI technologies of the future.
`In this paper it is shown for the first time how corner
`MOSFET current characteristics can be extracted from
`measurements and how the corner device must be taken
`
`Manuscript received March 11, 1993; revised May 16, 1993.
`A. Bryant, S. Geissler, and J. Mandelman are with IBM Technology
`Products, Essex Junction, VT 05452.
`W. Haensch and M. Steger are with Siemens, Essex Junction, VT.
`D. Poindexter is with the IBM Technology Products, Hopewell Junc-
`tion, NY 12533.
`IEEE Log Number 9211204.
`
`into account when extracting MOSFET channel charac-
`teristics. These concepts are used to explore the control of
`the corner I: by varying the p-well boron concentration
`of an n-channel MOSFET. The implications of the corner
`device for logic and DRAM applications are discussed.
`11. RESULTS AND DISCUSSION
`The n-channel MOSFET's (NFET's) built for this ex-
`periment are based on the Siemens-IBM 64-Mb DRAM
`process [9]. The important technology feature for this
`work is the use of trench isolation. The NFET gate is
`formed from ni polysilicon and gate oxide is 10 nm thick.
`In Fig. 1, the saturated drain-to-source current (Zsat) for
`NFET's of equal designed length (Ldes = 0.5 pm) and
`age (5) at a drain voltage ( v d ) of 3.3 V and a substrate
`varying designed widths (W,,,) is plotted versus gate volt-
`voltage ( K x ) of - 1 V. A distinct discontinuity in the log
`(Zsat)-% curves occurs at a gate voltage near the thresh-
`old of the channel (Kcha,). A similar discontinuity is also
`observed on log plots of the linear mode current (Zlin).
`Below the Vg where this discontinuity occurs, the current
`is dominated by width-independent corner conduction
`while, above it, the channel contributes a significant
`width-dependent component to the total current. The
`presence of the corner device is not obvious in the linear
`plot of I,,, nor in the linear plot of Zlin. However, the
`width-independent corner on-current can be clearly iden-
`tified in the (Zsat)0.5-5 curves in Fig. 2, where it is evident
`that the saturated corner current obeys the usual square-
`law Y dependence observed at low gate overdrives
`(%-VI. Thus, the corner-V, (V,,,,)
`is the gate voltage at
`to be zero. The net
`(Zsat)0.5 is extrapolated
`which
`transconductance of the two corner devices bounding the
`NFET channel is proportional to the squared slope (ycor
`= 8 pA/V2) of the (Z,a,)0~5-Vg curve in the corner-
`dominated region. For these devices it was empirically
`found that the current at the extrapolated V,,,, was ~4
`X (0.5 pm/L,,,) nA and was independent of Kx.
`
`To first order, I/tchan is the voltage at which the width-
`dependent total current begins to deviate from the extrap-
`olation of the corner current. The total current at Kcha"
`includes a significant corner current [ yco, x ( K c h a " -
`l/c0,)2] component and a channel current
`[40 X
`(Wdes/Ldes) nA] component. For the NFET's in Fig. 1, the
`corner component dominates over the channel compo-
`nent. Therefore, the standard current definition for I/lchan
`
`0741-3106/93$03.00 0 1993 IEEE
`
`Page 1 of 3
`
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`

`BRYANT et ai.: CURRENT-CARRYING CORNER INHERENT TO TRENCH ISOLATION
`
`413
`
`0.7r
`
`2 0.4-
`
`h
`
`v
`c
`0.3-
`
`0.1 -
`
`;, . . ,:
`
`0.0
`
`~
`
`0.0
`
`1
`0.5
`
`~ V T C H A N
`
`WDES = 9.5 prn,:’
`
`--3
`
`- -6
`--7 3
`--8 d
`--9 3
`m
`
`” --11
`
`I
`I
`1
`1.0
`2.0
`1.5
`Gate Voltage (V)
`
`2.5
`
`3.0
`
`Fig. 1. The corner device current contribution is not obvious in the
`linear plot of Isal. However, a distinct discontinuity in the log (Isat)-&
`curves occurs at a gate voltage near Vchan. (V,, = - 1 V, V, = 3.3 V).
`
`WDES = 9.5 vm
`
`”I
`
`1.61
`
`1.2
`
`+ YCOR (VTCHAN-VTCOR)‘
`
`.....................
`
`1~>40(w) nA
`L
`
`VTCHAN
`
`0.4 t
`
`0.0 o
`
`1
`
`2
`
` 3
`
`4
`
`.
`5
`
`6
`
`7
`
`8
`
`9
`
`2
`10
`
`~
`
`WDES (pm)
`Fig. 3. The extrapolated corner V,, the traditional channel
`defined
`by the current level It,, = 40 X (Wdes/Ldes)
`nA that only accounts for
`channel current, and the channel V, defined by the current I,, = [40 X
`+ -ycocor X (yrchan V,:,,]
`(Wdes/Ldes)
`that also accounts for the corner
`current are plotted versus designed channel width (Wdeh). (5, = - 1 V,
`v, = 3.3 V).
`
`0.8-
`-
`0.7
`-
`0.6
`-
`-
`0.5
`e- > 0.4-
`
`E
`
`-&
`
`0.3-
`-
`0.2
`-
`0.1
`-
`0.0
`-
`1
`0
`
`0.5’
`
`I
`2.0
`1.5
`1.0
`Gate Voltage (V)
`
`I
`
`I
`2.5
`
`I
`3.0
`
`Fig. 2. The width-independent corner on-current can be identified in
`curves. The comer V, (V,,,,)
`the (I::)-&
`is the gate voltage at which
`(Isa1)0.5
`is extrapolated to be zero.
`
`[Iv, = 40 X (Wdes/Ldes) nA] would lead to misleading
`results, such as predicting that VJchan decreases with width,
`as illustrated in Fig. 3. The corner must also be taken into
`account to accurately determine channel widths of the
`devices in Fig. 1, since its transconductance is comparable
`to that of a 0.1-pm-wide channel.
`The Ychan and V,,,, sensitivities to surface-channel V,-
`adjust implant dose were determined by using these sim-
`ple corner characterization concepts and are shown in Fig.
`4. Three observations are made: 1) V,,,, < Kcha,,; 2) the
`corner’s V,, sensitivity is approximately half the channel’s;
`and 3) the corner’s dose sensitivity is much less than the
`channel’s . These results are a consequence of the fring-
`ing fields at the silicon corner, which enhance gate control
`and increase the ratio of the gate capacitance to the
`depletion capacitance at the corner. Although V,,,, was
`increased from 0.5 to 1 V, ychan was simultaneously
`increased from 0.9 to 1.7 V. Thus, it may become neces-
`sary to locally increase the doping concentration at the
`corner above the channel concentration in order to de-
`crease corner off-current without degrading the channel
`current drive [4].
`
`0.01
`4
`
`I
`6
`
`I
`I
`8
`10
`Dose (1 x 10’’ ern-')
`Fig. 4. The measured corner V, (V,c,,r) and channel V, (Kcha”) are
`plotted versus the dose of the surface-channel V,-adjust 12-keV boron
`implant. (I& = - 1 and -3 V, V, = 3.3 V).
`
`1
`12
`
`J
`14
`
`In contrast, the corner device offers advantages in ap-
`plications such as DRAM’S that use narrow devices. First,
`even at equal I/%, the corner’s contribution to on-current
`becomes comparable to the channel’s and is independent
`of width variations. For the devices built in this work, the
`corner would contribute 30% to the total current of a
`0.30-pm-wide device. Furthermore, since DRAM cell de-
`vice currents are limited by the source-follower mode, the
`corner’s weak substrate sensitivity offers an even more
`significant advantage
`
`111. SUMMARY
`To provide a better understanding of the corner MOS-
`FET inherent to trench isolation, it has been shown how
`corner MOSFET characteristics can be extracted from
`hardware measurements and how the corner device must
`
`Page 2 of 3
`
`

`

`414
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 8, AUGUST 1993
`
`be taken into account when extracting MOSFET channel
`characteristics. For NFET’s it was found that the corner’s
`threshold voltage, substrate sensitivity, and dose sensitiv-
`ity were all smaller than the channel’s. The results implied
`that, for low standby power logic applications requiring
`high performance, it may become necessary to locally
`control the well doping at the corner. However, the cor-
`ner’s reduced substrate sensitivity and width indepen-
`dence can provide a significant advantage in a DRAM
`cell.
`
`ACKNOWLEDGMENT
`The authors are grateful for R. Mohler’s continual
`support and the many helpful discussions with M. Worde-
`man, W. Noble, and A. Leblanc.
`
`REFERENCES
`[l] J. A. Appels, E. Kooi, M. M. Paffen, J. J. H. Schatorje, and
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`25, p. 118, 1970.
`
`G. Fuse et al., “A practical trench isolation technology with a
`novel planarization process,” in IEDM Tech. Dig., 1987, pp.
`732-735.
`B. Davari et al., “A new planarization technique using a combina-
`tion of RIE and chemical-mechanical polish (CMP),” in IEDM
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`K. Shibahara et al., Trench isolation with nabla-shaped buried
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`N. Shigyo et al., “Steep subthreshold characteristic and enhanced
`transconductance fully-recessed oxide (trench) isolated 1/4 pm
`width MOSFETs,” in IEDM Tech. Dig., 1987, pp. 636-639.
`T. Furukawa and J. A. Mandelman, “Process and device simula-
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`Oct. 9-14, 1988.
`K. Ohe, S. Odenaka, K. Moriyama, T. Hori, and G. Fuse,
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`D. Foty, J. Mandelman, and T. Furukawa, “Behavior of an NMOS
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`sented at the 1989 Meeting Electrochem. Soc., Hollywood, FL,
`Oct. 1989, pp. 15-20.
`D. Kenney et al., “A buried-plate trench cell for 64 Mb DRAM,”
`in 1992 Symp. W S I Technology, Dig. Tech. Papers, pp. 14-15.
`
`Page 3 of 3
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