.
`
`Unlted States Patent [19]
`Corbin, II et al.
`
`US005097422A
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5 097 422
`9
`,
`Mar. 17, 1992
`
`[54] METHOD AND APPARATUS FOR
`
`4,500,963 2/1985 Smith et a1. ....................... .. 364/488
`
`DESIGNING INTEGRATED CIRCUITS
`
`[75] Inventors: Ludlow V. Corbin, II; Steven G.
`Danielson, both of Seattle; Richard E.
`Oettel, Bellevue; Mark E, Rossman,
`Redmond; James E_ Thiele’ Seattle’
`
`an of wash
`
`[73] Assignee; Cascade Dgsign Automation
`Corporauon’ Benevue’ Wash‘
`[21] App], No,; 374,435
`[22] Flled:
`Jun. 29’ 1989
`.
`
`[63]
`
`Related US. Application Data
`Continuation of Ser. No. 917,917, Oct. 10, 1986, aban-
`dual
`
`[51] Int. Cl.5 ............................................ .. G06F 15/60
`[52] US. Cl. .................................. .. 364/491; 364/490;
`_
`364/489; 364/488
`[58] Field of Search ............. .. 364/488, 489, 490, 491,
`364/200
`
`[56]
`
`References Cited
`Us. PATENT DOCUMENTS
`
`4,234,332 111/1985 Otten . . . . . . . . . . . . . . .
`4,
`,
`/1986 Dunlo et al. ..
`4,580,228 4/1986 Note . . . . . . . . . . . . .
`4,584,653 4/ 1986 Chih et a1. ........ ..
`4,630,219 12/1986 DiGiacomo et al.
`4,635,208 1/ 1987 Coleby et a1. . . . . . . .
`
`. . . .. 364/491
`364/491
`. . . .. 364/300
`364/491
`364/488
`. . . _. 364/491
`
`. . . .. 364/488
`4,656,603 4/1987 Dunn . . . . . . . . . . . . . . .
`364/300
`4,667,290 5/1987 Goss et al. .... ..
`4,700,317 10/1987 Watanabe et al. ................ .. 364/488
`Primary Examiner—Parshotam S. Lall
`Assistant Examiner-V. N. Trans
`orney Agen or zrm Seed and Berry
`Att
`,
`t,
`F‘ —
`[57]
`ABSTRACT
`A method and apparatus for determining integrated
`cum!“ layouts fr°m a virtual circlm de§criPFi°n and
`speci?cation of a technology. Starting wlth high-level
`descriptions of a circuit, a virtual geometric description
`of the circuit is developed using a virtual grid described
`in terms of reference points relative to a Substrate Sur,
`face. The relationships among the reference points are
`expressed as fractions of variables that can also be used
`to de?ne the design rules. When the technology is speci
`?ed, the relationships among the reference points is
`determ' d, 'thl t fth '
`'
`'.
`me as in e ayou o
`e mtegrated circuit
`
`H 354 10/1987 Rubin .................................... .. 364/491
`
`16 Claims, 9 Drawing Sheets
`
`> usER
`INTERFACE
`
`GEONETRY
`GEN ERATOR
`
`BY DESIGN Ru1.E SETS
`‘ TO GENERATORS
`
`CREATE LAYER-BY-LAYER
`I SCRIPTION OF PHYSICAL
`
`WRiTE LAYER-BY-LAYER
`DESCRIPTION TO SSTIF
`
`Page 1 of 23
`
`IP Bridge Exhibit 2019
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`U.S. Patent
`US. Patent
`
`Mar. 17, 1992
`Mar. 17, 1992
`
`Sheet 1 of 9
`Sheet 1 of 9
`
`5,097,422
`5,097,422
`
`IE‘KGO l
`]E‘]IG. II
`
`Page 2 of 23
`
`Page 2 of 23
`
`

`

`US. Patent
`
`Mar. 17, 1992
`
`Sheet 2 of 9
`
`5,097,422
`
`mOULE
`SPECIFICATION
`
`2O
`
`l
`
`GATE-LEVEL
`ORAHING
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`COHP ILER
`
`IFKGO 2
`
`Page 3 of 23
`
`

`

`U.S. Patent
`
`Mar. 17, 1992
`
`Sheet 3 of 9
`
`5,097,422
`
`”'
`
`28
`
`52
`
`30
`
`]F’1[G° 3
`
`INPUT
`
`OUTPUT
`
`INPUT
`
`CLKINOT
`
`CLKZNOT
`
`Page 4 of 23
`
`Page 4 of 23
`
`

`

`U.S. Patent
`US. Patent
`
`Mar. 17, 1992
`Mar. 17, 1992
`
`Sheet 4 of 9
`Sheet 4 of 9
`
`5,097,422
`5,097,422
`
`FIG, 5
`
`Page 5 of 23
`
`Page 5 of 23
`
`

`

`US. Patent
`
`Mar. 17, 1992
`
`Sheet 5 of 9
`
`5,097,422
`
`SPECIFY MODULE NAME
`
`SPECIFY DESIGN RULE SET
`
`SPECIFY NUMBER OF BITS
`
`72
`A
`
`[73
`
`74
`
`USER
`* INTERFACE
`
`PASS SPECIFICATIONS
`35%“???‘6? Ns‘I‘1MsETAoND
`GENERATORS
`
`76
`'I5Ass RULE SETS AND PROCESS
`PARAMETER TABLES REFERENCED
`BY DEsIeN RULE sETs
`TO GENERATORS
`
`I
`INITIATE SETUP OF
`Ic MODULE DATABASE
`
`J
`/77 \
`
`[78
`‘
`CALL GEOMETRY GENERATOR
`
`$ INITIALIzATION
`
`_____ _ _ _ _ _ _ _ _ _ _ __J_ _ _§I—I_I_E_LL
`
`GEOMETRY
`GENERATOR
`
`ACCEPT PARAMETERS
`FROM UsER INTERFACE
`
`CREATE LAYER-BY-LAYER
`DESCRIPTION OF PHYSICAL
`MODULE
`I
`CREATE ssTIF
`
`wRITE LAYER-BY-LAYER
`DESCRIPTION TO ssTIF
`
`EXTRACT FOOTPRINTs
`FROM ssTIF FILER
`
`fvs
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`
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`
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`
`FIG‘, 7
`
`Page 6 of 23
`
`

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`US. Patent
`
`Mar. 17, 1992
`
`Sheet 6 of 9
`
`5,097,422
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`Page 7 of 23
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`

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`US. Patent
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`Mar. 17, 1992
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`Sheet 7 of 9
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`5,097,422 ‘
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`Mar. 17, 1992
`Mar. 17, 1992
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`Sheet 8 of 9
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`5,097,422
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`

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`US. Patent
`
`Mar. 17, 1992
`
`Sheet 9 of 9
`
`5,097,422
`
`8
`
`102‘
`
`FIG, 11GB
`
`Page 10 of 23
`
`

`

`METHOD AND APPARATUS FOR DESIGNING
`INTEGRATED CIRCUITS
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`This application is a continuation of U.S. application
`Ser. No. 06/917,917 ?led Oct. 10, 1986, now aban
`donned.
`
`5
`
`TECHNICAL FIELD
`This invention relates to integrated circuit design
`tools. More particularly, this invention relates to a sym
`bolic and dynamic method for designing integrated
`circuits and an apparatus for implementing such
`method.
`
`25
`
`40
`
`BACKGROUND ART
`A monolithic integrated circuit is a combination of
`20
`interconnected circuit elements inseparably associated
`on or within a continuous substrate. Typically, the cir
`cuit elements are conventional components-transis
`tors, diodes, capacitors, and resistors—fabricated in situ
`within or on a single crystal of semiconductor material
`with the capability of performing a complete electronic
`circuit function.
`In practice, an integrated circuit is designed in a top
`down method by ?rst designing a logic level drawing
`and a transistor level drawing. These drawings then are
`used to design the more detailed integrated circuit lay
`out, which shows the IC layers (i.e., metal, polysilicon,
`active, and the ways they interrelate to form transistor
`gates, wires, contact points, etc.). The integrated circuit
`layout, often referred to as “geometry,” is used to gen
`erate the integrated circuit tooling, which is a series of
`35
`masks, each representing a layer for the integrated cir
`cuit. The tooling is then used by manufacturers to fabri
`cate an integrated circuit.
`Typically, monolithic integrated circuits are fabri
`cated by a process of photolithography, doping, and
`material deposition. Photolithography is any technique
`whereby light or other electromagnetic rays are shown
`through a mask to create a pattern on a silicon wafer
`coated with a photosensitive ?lm. Doping includes
`those techniques for treating the exposed areas in the
`pattern to take on n- or p-type characteristics to form
`components of transistors and diodes. “Material deposi
`tion” refers to the growth or deposit of photoresist,
`insulating oxide, metal, polysilicon, and other materials
`that form the topology of the circuit.
`In one method for fabricating an integrated circuit, a
`layer of photoresistive material is deposited on a semi
`conductor wafer. A mask for the integrated circuit is
`then placed over the layer of photoresistive material
`and light is shown through the mask to activate parts of
`55
`the photoresistive material, thereby leaving a predeter
`mined pattern of conductors on the wafer and exposed
`areas of the wafer between the conductors. Transistors
`and diodes are then formed by doping portions the
`exposed areas of the wafer with a chemical doping
`agent. A second mask can then be used. to generate
`another pattern of conductors and exposed areas which
`are, once again, doped. Additional doping layers may
`also be used. After each doping step, the photoresistive
`material is chemically removed from the wafer. When
`65
`the ?nal doping layer has been completed, a pattern of
`exposed areas of the wafer is once again formed by
`exposing a layer of photoresist on the wafer through a
`
`45
`
`50
`
`1
`
`5,097,422
`
`2
`mask. A layer of metal or other suitable conductor is
`then deposited onto portions of the exposed areas of the
`semiconductor wafer to form the desired interconnec
`tions between components on the wafer. Though there
`are many fabrication technologies, fabrication tech
`niques, and integrated circuit materials, fabricating the
`design for the integrated circuit through one or more
`masks is used consistently.
`'
`Depending on the fabrication technologies and tech
`niques, and the materials used, different con?guration
`constraints apply. These constraints are commonly re
`ferred to as “geometric design rules” or “design rules.”
`Design rules include, for example, specifications for
`minimum spacing between transistors and minimum
`separation between conductors to prevent shorting,
`speci?cations for minimum metal width, and speci?ca
`tions for maximum metal heights and slopes of walls
`which form metal junctions.
`With the continued improvement of fabrication tech
`nologies and techniques and the development of new
`materials used in de?ning electronic circuits, design
`rules are changing to allow for smaller and smaller
`spacings between materials on an integrated circuit and
`to allow smaller and smaller substrate areas. Thus de
`sign rules may change during the development process
`of any particular circuits. Because increases in the die
`size of a mask by 15% typically result in a doubling of
`the cost of an integrated circuit, minimal substrate areas
`are desired
`One of the most commonly used methods for chang
`ing integrated circuit layouts to account for these de
`sign rules or changes in these design rules is called the
`“manual compaction method.” If the substrate area
`specification is reduced during the middle of the design
`process, the designer, using the manual compaction
`method, manually varies each of the spacings shown in
`the integrated circuit layout. Because the relative move
`ment of any component impacts the spacing of all adja
`cent components, the adjacent components may also
`have to be moved. As a result, this manual process is
`very tedious and time-consuming. It consequently limits
`the circuit complexity that integrated circuits designed
`in this manner can achieve, and precludes the develop
`ment of a market for most custom-integrated circuits.
`Another method used to make changes in integrated
`circuit layouts is the virtual grid compaction method,
`developed at Bell Laboratories. In this method, a virtual
`grid of typical worst-case component spacing is de?ned
`and the circuit components are relatively positioned on
`the grid using an automatic post-processing algorithm.
`Each grid line is then sequentially moved closer to
`another grid line until a design rule is violated. A prob
`lem with this approach is that the design rule constraint
`must apply to the entire grid line, thereby impacting
`neighboring devices which may have allowed for less
`spacing and thus more compaction.
`Typically, the manual compaction processes have
`been the expensive and time-consuming processes used
`for minimizing the area and cost of an integrated circuit.
`A turnaround time of six months or more has been
`common. There has long been a need for a versatile and
`simple compaction method that can accommodate the
`various design rules and constraints from different fabri
`cation techniques and materials and achieve compac~
`tion results comparable to manual methods.
`
`Page 11 of 23
`
`

`

`5,097,422
`
`4
`and the methodology for using such subset combine to
`be the preferred embodiment of the method of this
`invention. The computer system is used to automate the
`design process and might include additional software
`tools for integrating modules, simulating integrated
`circuit performance, printing geometries, and creating
`tooling (such as masks).
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an isometric view of an embodiment of the
`apparatus for designing integrated circuits.
`FIG. 2 is a ?ow chart for designing an integrated
`circuit module compiler using the apparatus of FIG. 1.
`FIG. 3 is a sample gate level schematic of one cell of
`a clocked dynamic shift register.
`FIG. 4 is a sample discrete device level schematic of
`one cell of a clocked dynamic shift register.
`FIG. 5 is a sample hand-drawn geometry layout of a
`clocked dynamic shift register.
`FIG. 6 is a sample schematic symbol for an eight-bit
`clocked dynamic shift register.
`FIG. 7 is a ?ow chart showing the steps performed
`by the compiler-link editor when generating an execut
`able module compiler for producing the integrated cir
`cuit layout geometry.
`FIG. 8 is a schematic diagram showing the directory
`?le organization for a clocked dynamic shift register of
`unspeci?ed length.
`FIG. 9 is a layout of the geometry generated from the
`source code of Table 2.
`FIGS. 10A and 10B are layouts of a shift register cell,
`expressing the cell in two distinct technologies.
`
`15
`
`20
`
`25
`
`3
`DISCLOSURE OF THE INVENTION
`An object of this invention is to provide a method and
`an apparatus for designing integrated circuits which are
`independent of the design rule constraints of conven
`tional materials and fabrication technologies and tech
`niques.
`Another object of this invention is to provide a
`method and an apparatus for designing integrated cir
`cuits which minimize the area of a circuit layout for any
`given electronic circuit design, including highly com
`plex, custom~designed integrated circuits.
`A further object of this invention is to provide a
`method and an apparatus for designing integrated cir
`cuits that automate the design process so that highly
`complex, custom-integrated circuits can be economi
`cally produced in a relatively short time.
`A still further object of this invention is to provide a
`method and an apparatus for designing integrated cir
`cuits which can be used to create electronic circuit
`design “building blocks,” which in turn can be used for
`designing highly complex integrated circuits.
`Yet another object of this invention is to provide a
`method and an apparatus for designing integrated cir
`cuits which require minimal integrated circuit design
`expertise in operation.
`These and other objects of the invention are accom
`plished by a method for designing layouts using a dy
`namic virtual grid and a set of design rule variables. The
`grid is de?ned in relative terms, such that an origin
`,30
`along an x axis and an origin along a y axis are used to
`de?ne reference points from which all positions on the
`grid are de?ned. These reference points are relative
`positions de?ned in terms of the origin or other refer
`ence points along the same axis, and/or one or more
`35
`design rule variables. Integrated circuit components
`(contacts, gates, wires, etc.), then, are de?ned as one or
`more polygons, in a speci?c layer, using the reference
`points and design rule variables. A speci?c layout is
`de?ned by specifying values for the design rule vari
`ables, thereby ?xing the positions of the integrated cir
`cuit components. If the fabrication process for manufac
`turing the chip changes or the technology changes to
`allow for smaller dimensions, thereby changing the
`layout position constraints (a part of the design rules),
`the design rule variables are changed accordingly and a
`new geometry is de?ned. Designing integrated circuits
`in this manner thus achieves design rule independence.
`Though the method described refers to relatively
`positioning integrated circuit components and to design
`rule variables corresponding to positioning constraints
`for various fabrication technologies and techniques, the
`method could also be used for relatively positioning
`other objects and for design rule variables correspond~
`ing to other positioning constraints.
`Typically, the method is used for designing subpor
`tions of an integrated circuit which are then integrated
`to form an entire integrated circuit layout database. The
`database is used to form tooling and/or masks for con-=
`ventional fabrication processes. The subportions may be
`strategically designed by function, so the geometry may
`be used as an interchangeable module for various inte
`grated circuit layouts or as a building block in highly
`complex integrated circuits. Thus, the method is com
`monly referred to as “module compilation.”
`One apparatus for implementing this invention is a
`computer system used to host software tools for design
`ing integrated circuits. A subset of the software tools
`
`50
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`Hardware
`Referring to FIG. 1, the preferred embodiment of the
`apparatus for designing integrated circuits 10 is a con
`ventional computer system including a computer 12,
`terminal 14, printer 16, and plotter 18. In one embodi
`ment, the computer is a VAX l l/ 785, model no. 1l-785
`AA, manufactured by Digital Equipment Corporation
`(DEC); the terminal is an AED 767 monitor terminal
`manufactured by Advanced Electronic Design, Inc.;
`the printer may be any one of a large number of avail
`able models; and the plotter is an HP 7475A manufac
`tured by Hewlett-Packard, Inc. The VAX 11/785 uses
`a UNIX version 4.2 operating system and includes an
`interface program for the AED 767 monitor called
`“Caesar version 7,” developed at the University of Cali
`fornia at Berkeley, and a “C” program language com
`piler, developed by Bell Laboratories. In the preferred
`embodiment, the method for designing integrated cir
`cuits is embodied within a Compiler Development Sys
`tem (CDS).
`
`Software
`The computer system 10 includes a set of software
`tools for designing integrated circuit module compilers,
`each consisting of source code and executable code.
`The integrated circuit module is an array of cells. Each
`cell, in turn, is the geometric de?nition of the required
`integrated circuit components. Every module can be
`combined, like a building block, with other modules in
`order to create a complete geometric description of an
`integrated circuit and a corresponding mask work.
`
`45
`
`55
`
`65
`
`Page 12 of 23
`
`

`

`10
`
`25
`
`5,097,422
`5
`The preferred embodiment of the method is, in effect,
`the implementation of a high level software language
`referred to as the “Silicon Compiler Software Lan
`guage for Integrated Circuits” (SLIC). Each SLIC
`command comprises, in one embodiment, a set of “C”
`language function calls. Thus, the preferred embodi
`ment is a language for writing source code which is to
`be compiled to generate executable code. Execution of
`the executable code results in a speci?c geometry lay
`out.
`The module compiler, developed using CDS, may be
`used with other module compilers or alone to develop
`an integrated circuit layout. Typically, the software
`tools for developing module compilers are used with
`other software in packages such as the ConcordeTM
`VLSI Compiler produced by Seattle Silicon Technol
`ogy, Inc. These other software tools include programs
`for interconnecting modules, such as the Pride/Auto
`Route TM software tool within the Concorde TM pack
`age.
`Typically, a modular approach is used for designing a
`complex integrate circuit. In this approach, the circuit
`for each module is designed, tested, and debugged be
`fore it is integrated with other modules to form the
`complete integrated circuit layout and mask work.
`Although the preferred embodiment of the method is
`a software embodiment designed to run on the VAX
`11/785 having a Unix Version 4.2 operating system and
`a "C” compiler, other embodiments of the method
`could be software programs designed to run on com
`puter systems using other computers, terminals, print
`ers, and plotters with another operating system and
`programming language. Still other embodiments of the
`method need not take the form of a computer program
`or be implemented through a computer system.
`SLIC is an extension language of the “C" program
`ming language. SLIC is used to write geometry genera
`tor source code for generating a layout. A second exten
`sion language, GSSLIC, may be used to write simula
`tion model source code for simulating the performance
`of the layout design. A third extension language,
`SSSLIC, may be used to write schematic symbol gener
`ator source code for deriving a schematic symbol for
`the module under development (e.g., the logic symbol
`for an ‘OR’ gate with inputs and outputs).
`
`40
`
`6
`The design will be implemented in CMOS PWELL
`technology, with Vdd above, +5 volts, GND below,
`0.5 volts. The input will be placed on the left, the output
`on the right. Each cell (or bit) of the shift register will
`delay an input signal one clock cycle. The number of
`bits, and thus the number of delays, is determined by the
`designer. There is to be no limit to the number of bits
`allowed.
`Referring to FIG. 3, the gate level schematic (draw
`ing 22 in FIG. 2) for one cell of the serial-in, serial-out
`clocked dynamic shift register speci?ed above consists
`of two clocked inverters 28, 30, which together have
`the effect of delaying an input signal one clock cycle.
`Referring to FIG. 4, a single cell at the discrete device
`level (drawing 24 in FIG. 2) for the serial-in, serial-out
`clocked dynamic shift register speci?ed above com
`prises two identical buffers, each consisting of a basic
`inverter circuit of transistors 32, 34, 36, 38 and 32', 34’,
`36’, 38’.
`Referring to FIG. 5, the preliminary, manually drawn
`layout (drawing 26 in FIG. 2) for one cell of the serial
`in, serial-out clocked dynamic shift register is shown,
`comprising its component metal 40, polysilicon 42, and
`active (diffusion) region 44, PWELL 46, P+ region 48, '
`and N+ regions 50. The input, output, clock signals
`(CLKI, CLKZ), inverted clock signals (CLKlNOT,
`CLKZNOT), power voltage (V dd), and ground con
`nections (GND) are all labeled.
`The designer strategically identi?es reference points
`(Xl-XS, Y1-Y9) for forming a dynamic virtual grid.
`Each reference point is de?ned along an X axis or a Y
`axis. In this case, the reference points are de?ned as all
`horizontal rows and vertical columns that contain at
`least one contact (speci?ed by an “X” in FIG. 5). These
`reference points can be de?ned with respect to other
`landmarks, such as transistor gates, the center of a wire,
`or other geometric features.
`The positions of these reference points will be de?ned
`using SLIC source code as mathematical functions of an
`origin, another reference point, and/or one or more
`design rule variables, electrical rule variables, or other
`constraints. The relationships among the reference
`points can be referred to as virtual geometric relation
`ships. Design rule variables are variables specifying
`con?guration constraints, such as metal width, polysili
`con width, metal spacing, etc. A sample of design rule
`variables, by no means a complete list, is included below
`in Table 1.
`By de?ning the reference points in this manner, the
`virtual grid may be abstracted from the reference points
`to consist of lines crossing each other, wherein the spac
`ing between lines is not determined. The grid is not part
`of the layout, but instead is a virtual grid for dynami
`cally de?ning relative integrated circuit feature posi
`tions. The virtual grid is superimposed on a ?xed grid of
`centi- micron units, using the X origin and Y origin as
`the link between the two grids. The ?xed grid de?nes
`the precision designed into the geometry generator for
`relatively positioning components on the virtual grid.
`After designing the preliminary layout and labeling
`the reference points, the designer may wish to design a
`modi?ed gate level drawing 52 (see FIG. 2) as a result
`of the discovery of advantageous gate level changes
`that can be made. For example, an alternative way of
`realizing a given logic function could be discovered at
`this point. As a preliminary step, the designer also de
`fines a schematic symbol drawing 54 to be used to rep
`resent the module in an overall schematic diagram of an
`
`45
`
`METHODOLGY: MANUAL DRAWINGS
`Referring to FIG. 2, the following is a description of
`the methodology used to design integrated circuit mod
`ule compilers. As a preliminary step, the designer iden
`ti?es the module speci?cation 20, including the technol
`ogy to be used (e.g., CMOS or BIPOLAR), the func
`tional characteristics of the circuit, a connection dia
`gram, the approximate dimensions, and the end user
`55
`input options for the integrated circuit module. The
`designer then develops preliminary high-level drawings
`of the integrated circuit. One drawing, typically, is a
`gate level drawing 22 specifying the circuits with stan
`dard gates and interconnections. At the next level, the
`gates are reduced to their discrete devices (i.e., transis
`tors) in a device level drawing 24. From the device
`level drawing, a preliminary layout drawing 26 is then
`derived, translating the discrete devices into a physical
`geometry of layers and components, such as wires,
`contacts, etc.
`As an example, a clocked dynamic shift register
`might be speci?ed as follows:
`
`65
`
`60
`
`Page 13 of 23
`
`

`

`7
`. integrated circuit using the shift register. Referring to
`FIG. 6, a schematic symbol 56 for an eight-bit clocked
`dynamic shift register is shown.
`TABLE 1
`Daign Rule variables
`_ Below is a sample list of design rule variables
`de?ning minimum valuevconstraints between material edges
`for a typ‘ca] CMOS process‘
`Description
`Active area width
`Active area spacing (N + Active to N+
`Active or P+ Active to P + Active)
`N+ active area to P+ active area
`(in PWELL' different pommials)
`Minimum PWELL width
`PWELL overlap of N+ active inside PWELL
`P 01y width
`P 01y spacing
`Cut width
`Cut spacing
`Active overla of contact
`Mew ovle?appof Contact
`g
`P+ mlsk width
`N+ mask width
`Pad-to-Pad spacing (giass-to-glass)
`zg‘t‘tfimdth
`PWELL Spacing, Same potential
`Center of p+ active Contact to center
`of substrate contact
`5:31:12;
`fo;°0°f°:;;l"f Poly
`Center of active contact to center of
`poly-metal comm in the dim?on of
`metal _
`_
`gflfaaigl‘iii’yntitic‘z'fgg center Ora
`minimum wid‘h zen-v: wire must diverge
`from the ccnm of ,, comcnwidth activc
`Wirc '0 achicvc ‘:1 common cdgc
`P°iylwire "Ft" ‘° P°]Y wi'" "m"
`width assumcd)
`to center of poly wmnct, poly Contact
`not in direction of metal
`
`5,097,422
`
`mcZmc
`bmzb
`dpyc
`
`I'D
`
`acZgt
`
`nacZpac
`
`bm
`mw
`gtx2
`
`pyoc
`
`Pyw
`pwopac
`pwonac
`noac
`
`5
`
`10
`
`15
`
`In
`
`ween CCU Cl'S O 1 me Wll'CS
`
`8
`Metal wire center to metal wire center,
`pgss?ible contains asiugiied ml _
`D2; game by which the “Mir ofa
`minimum width poly wire must diverge from
`th;i center of a contzgtewidth poly wire to
`antee‘i'eoii'ggiilxzxhntaiet to center of gate
`region
`Center of n+ active contact to center of
`p+ active contact
`Bi? ,meml width ,
`.
`Mmunum metal width
`Center of gate region to poly extension
`beyond gate mums i poly width.
`.
`Poly overlap of contact not in direction
`“PM
`.
`.
`M‘mmm 1”” w‘d‘h
`Pwell overlap of p+ active cut
`Pwell overlap of n+ active cut
`N+ mask overlap of active cut
`
`20
`
`METHODOLOGY: MODULE COMPILER
`_ Using the design rule variables in Table l, the de
`signer can write a computer program using the well
`known “C” programming language and SLIC com
`mands to generate a design rule-independent layout rule
`25 module compiler. Using the module speci?cation 20 (‘in ,
`FIG. 2), the designer may write shell source code 58 in
`the “C” programming language to de?ne the module»
`may include a ?le of design rules, and may also develop
`an interactive menu to make the completed module
`30 comPller “uscr'fnendly""
`_
`Using the layout drawing 26 (in FIGS. 2 and 5) for
`reference, the designer includes SLIC commands as
`geometry generator source code
`This source code
`de?nes the dynamic virtual grid in terms of the refer
`35 ence points shown in FIG. 5. Referring to Table 2,
`below, an example of SLIC source code used to de?ne
`the reference points for one cell of the clocked dynamic
`shift register speci?ed above is shown in program lines
`81-85 and 88-96. This example also includes shell
`40 source code 58.
`
`‘
`
`'
`
`‘
`
`'
`
`‘
`
`Name
`aw
`as
`
`napasi
`
`pww
`pwona
`pyw
`pys
`cw
`cs
`aoc
`me
`:3
`ppw
`nnw
`pds
`:a
`pwss
`pacZsbc
`
`azpycm
`acZpycm
`
`2::
`
`PYZPY
`pyzpyc
`
`TABLE 2
`
`l /****i*iri*************?t*****k*?*********k************
`2
`vi
`3
`* Module : Dynamic Shift Reg .. Shell & Geometry Generator
`*
`g ******************?****************?****************‘k/
`6
`7
`8
`
`.
`
`9 /*****************************************************7
`l0
`COMP ILER SHELL
`ll Mimum*********************************************ik/
`l 2
`l 3
`l 4
`l5 # include (stdio . h>
`l6 # include "/u9/exp/include/slic . h"
`17
`18
`19 ma in ( argc , argv)
`20 INT32 argc;
`21 char *argvl ]:
`
`Page 14 of 23
`
`

`

`9
`
`I
`INT32 nbits;
`char modname[80l ;
`
`5,097,422
`
`10
`
`printf ("\nDYNAMIC SHIFT REGISTER MODULE COMPILER\r§l‘) 7
`printf ("\nModule Name? ") :
`scanf (“%s" , modname) ;
`printf ("\nNumber of Bits? “) ;
`scanf ("%d", &nbits) ;
`printf ("\nCreating Module %s. . .\n\n" ,modname) ;
`
`cfInit();
`initialize(argc, argv) ;
`
`dsrlyout(nbits,modname) ;
`1
`
`GEOMETRY GENERATOR
`****k'k***********************************k*k*?~k**k*k*/
`
`dsrlyout(nbits,modname)
`INT32 hbits;
`char *modname;
`
`rtend;
`
`(
`INT32
`INT32
`INT32
`INT32
`INT32
`UPORTRECORD pp;
`char lastl80], nowl80];
`char templ80] ,instl80];
`char commandIBO];
`xorigin=0; yorigin=07
`
`.
`
`/**********************ki**************i************tk
`Define the Subcell
`t***?*******************i************************ii*?/
`
`.define("SRsubcell");
`
`rtend=MAX(nac2pwc,pac2sbc)7
`
`landmark("xl",xl,xorigin):
`landmark("x3",x3,xl+rtend);
`
`Page 15 of 23
`
`

`

`/**********iz******i*
`
`*******?*k***k****/
`
`104 layer("metal");
`
`/***********k****
`
`108
`109
`110 wire(bm,x1,yl) zx(x5+rtend) ;v
`111 wire('bm,xl,y9) ;x(x5+rtend) ;
`112
`113
`
`/*************k******
`
`115
`116
`
`122
`
`.
`
`/*************
`
`124
`125
`126 wire(bm,x3,y4) ;y(y6) :
`127 wire(bm,x3,y4) ;y(y6) ;
`128
`129
`
`/******************
`
`131
`132 ,
`133-~ 1ayer("act.ive") ;
`134
`
`137 wire(2*hac,x5,yl) ;y(y4) 7
`138 wire(2*hac,x5,y6) ;y(y9) ;
`139
`140
`
`/*******************
`
`142
`
`****************/
`
`*****'k************/
`
`************k/
`
`§**************tk*/
`
`'A'******************/
`
`Page 16 of 23
`
`

`

`13
`
`5,097,422
`
`14
`
`C-shaped Gates
`
`/**'k*'k************** Clock Gates
`
`*****kk******tk***/ _
`
`/********** Stage to Stage Interconnects **f*******/
`
`ADD SUBSTRATE AND PWELL CONTACTS
`
`PwCON(x1,yl) 7
`SUBCON(x1,y9);
`
`/*************
`
`ADD ALL OTHER CONTACTS
`
`*************/
`
`143
`144
`145
`146
`147
`148
`149
`150
`151
`
`152
`
`153
`154
`155
`156
`157
`158
`159
`160
`161
`162
`163
`164
`165
`166
`167
`168
`169
`
`170
`171
`172
`173
`174
`175
`176
`1:77
`178
`179
`180
`181
`182
`183
`
`185
`186
`187
`188
`189
`190
`191
`192
`193
`194
`195
`196
`197
`198
`199
`
`Page 17 of 23
`
`

`

`15
`PYM(x3,y5,"NS");
`PYM(x5,y5,"NS")7
`
`5,097,422
`
`16
`
`/'k***k************
`
`N+ ACTIVE LAYER
`
`****k**k********/
`
`layer("nplus"):
`
`/*********?*****~k*
`
`P+ ACTIVE LAYER
`
`*******k*kkk***k/
`
`layer("pplus“);
`
`/***************1’
`
`PWELL LAYER
`
`***************k*****/
`
`layer(“pwel1");
`box(x1-pwopac,yl-MAX(pwopac,pwonac),x5+mc2mc+bm/2,
`y4+pwonac);
`
`/**************k***
`
`ADD THE PORTS
`
`***************ir*/
`
`port("GND_LR",x5+rtend,yl,"metal",NONE);
`port("CLK_R",xS+rtend,y2,"metal",NONE);
`port(”CLKl_R",x5+rtend,y3,"metal",NONE);
`port(“OUTPUT",x5+rtend,y5,"poly",NONE);
`port("CLKlNOT_R",x5+rtend,y7,"metal",NONE):
`port("CLK2NOT_R“,xS+rtend,y8,"metal",NONE);
`port("Vdd_UR",x5+rtend,y9,"metal“,NONE);
`port("GND_ll“,xl,yl,"metal",NONB);
`port("CLK2_L",xl,y2,"metal",NONE);
`port("CLKl_L",xl,y3,"metal",NONE);
`port("INPUT",xl,y5,"poly",NONE);
`port("CLK1NOT_L",xl,y7,"metal",NONE);
`port("CLK2NOT_L",xl, 8,"metal",NONE);
`port("Vdd_UR",xl,y9,"metal",NONE);
`port(“STlOUT“,x5—py2pyc,y5,“poly",NONE);
`
`enddef();
`
`/***************************i*************************
`Define the Module
`*************i*k*k***********************************/
`
`define(modname);
`
`200
`201
`>202
`203
`204
`205
`206
`207
`208
`209
`210
`211
`212
`213
`214
`215
`216
`217
`218
`219
`220
`221
`222
`223
`224
`225
`226
`227
`
`228
`229
`230
`231
`231
`233
`234
`235
`236'
`237
`238
`239
`240
`241
`242
`243
`244
`245
`246
`247
`248
`249
`250
`2