Trials@uspto.gov
`571-272-7822
`
`Paper 8
`Entered: January 4, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
` TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Cases IPR2016-01246 and IPR2016-01247
`Patent 7,126,174 B2
`____________
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`

`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`Petitioner Taiwan Semiconductor Manufacturing Company, Ltd. filed
`
`two Petitions requesting inter partes review of claims 1–12 and 14–18 of
`
`U.S. Patent No. 7,126,174 B2 (Ex. 1001, “the ’174 patent”)1 pursuant to
`
`35 U.S.C. § 311(a). Patent Owner Godo Kaisha IP Bridge 1 filed a
`
`Preliminary Response and Motion for District Court-Type Claim
`
`Construction in each proceeding, as listed in the following chart.
`
`Case Number
`
`Challenged
`Claims
`
`Petition
`
`Preliminary
`Response
`
`Motion
`
`IPR2016-01246 1–3, 5–7,
`9–12, and
`14–18
`
`Paper 2
`(“Pet.”)
`
`IPR2016-01247 1, 4, 5,
`8–12, 14,
`and 16
`
`Paper 2
`(“-1247 Pet.”)
`
`Paper 7
`(“Prelim.
`Resp.”)
`
`Paper 7
`(“-1247
`Prelim.
`Resp.”)
`
`Paper 6
`(“Mot.”)
`
`Paper 6
`(“-1247
`Mot.”)
`
`Pursuant to 35 U.S.C. § 314(a), the Director may not authorize an
`
`inter partes review unless the information in the petition and preliminary
`
`response “shows that there is a reasonable likelihood that the petitioner
`
`would prevail with respect to at least 1 of the claims challenged in the
`
`petition.” For the reasons that follow, we institute an inter partes review as
`
`to claims 1–12 and 14–18 of the ’174 patent on certain grounds of
`
`unpatentability. We also exercise our authority under 35 U.S.C. § 315(d) to
`
`consolidate the two proceedings and conduct the proceedings as one trial.
`
`
`
`
`1 Unless otherwise specified with the “-1247” prefix, references to exhibits
`herein are to those filed in Case IPR2016-01246.
`
`
`
`
`2
`
`

`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`I. BACKGROUND
`
`A. The ’174 Patent2
`
`The ’174 patent discloses a “semiconductor device including
`
`transistors and connection[s] between the transistors for constituting
`
`[a large-scale integration (LSI) integrated circuit (IC)] with high integration
`
`and a decreased area.” Ex. 1001, col. 1, ll. 13–16. At the time of the
`
`’174 patent, various improvements had been made in semiconductor
`
`manufacturing due to “increasing demands for more refinement of the
`
`semiconductor device.” Id. at col. 1, ll. 17–22. The ’174 patent describes
`
`one known method of forming an isolation structure (for shielding devices
`
`from each other on a substrate) known as Local Oxidation of Silicon
`
`(LOCOS), which was “conventionally adopted in view of its simpleness and
`
`low cost.” Id. at col. 1, ll. 22–25. The LOCOS isolation method involves
`
`selective oxidation of a silicon substrate, but has a disadvantage in that it
`
`results in a “bird’s beak” overhanging area of silicon dioxide. Id. at col. 1,
`
`ll. 29–31. “As a result, the dimension of a transistor is changed because an
`
`insulating film of the isolation invades [the] transistor region against the
`
`actually designed mask dimension.” Id. at col. 1, ll. 31–34. According to
`
`the ’174 patent, compared to LOCOS, “trench buried type isolation” (or
`
`“trench isolation”) was determined to be “more advantageous for
`
`manufacturing a refined semiconductor device.” Id. at col. 1, ll. 25–28.
`
`The ’174 patent describes a “conventional semiconductor device”
`
`with a trench isolation structure “whose top surface is flattened so as to be at
`
`the same level as the top surface of the silicon substrate” (as shown in
`
`2 The ’174 patent is a division of a series of U.S. applications ultimately
`descending from a U.S. application filed on July 24, 1996, and claims the
`benefit of foreign applications filed on July 27 and December 19, 1995.
`
`
`
`3
`
`

`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`Figure 17) or whose top surface is higher than the surface of the silicon
`
`substrate (as shown in Figure 20(e)). Id. at col. 1, l. 52–col. 2, l. 6 (structure
`
`2b), col. 4, l. 16–col. 5, l. 11 (trench isolation 105a). By using the
`
`“conventional trench isolation” structure, “the dimensional change of the
`
`source/drain region can be suppressed because the bird’s beak” created using
`
`LOCOS is avoided. Id. at col. 4, ll. 16–19, col. 5, ll. 12–17. According to
`
`the ’174 patent, using the trench isolation method caused various problems
`
`of its own due to the etching required. Id. at col. 5, ll. 21–58.
`
`The ’174 patent describes various embodiments of semiconductor
`
`devices and methods of manufacturing the same. The manufacturing
`
`process for Embodiment 10 is depicted in the sequence of Figures 12,
`
`13(a)–(e), and 15(a)–(f). Id. at col. 21, ll. 33–34, col. 26, ll. 36–45 (referring
`
`to the previously described process of Embodiment 8). Petitioner provides
`
`on page 13 of the Petition a colored and annotated version of Figure 15(f) of
`
`the ’174 patent, reproduced below, which is consistent with the ’174 patent’s
`
`disclosure.
`
`The figure above depicts a device including isolation 2b, which is the result
`
`of forming a trench in silicon substrate 1 and filling it with insulating
`
`
`
`
`
`4
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`material. Id. at col. 21, ll. 39–50, col. 22, ll. 34–44. “[E]lectrode sidewalls
`
`32a, interconnection sidewalls 32b and a step sidewall 32c each having an
`
`L-shape remain on the sides of the gate electrode 4a, the gate
`
`interconnection 4b and the step portion, respectively.” Id. at col. 27, ll. 4–8.
`
`The ’174 patent describes various advantages of forming “L-shaped
`
`sidewalls” in the manner disclosed. Id. at col. 27, ll. 34–47.
`
`
`
`
`
`B. Illustrative Claim
`
`Claim 1 of the ’174 patent recites:
`
`1. A semiconductor device, comprising:
`
`a trench isolation surrounding an active area of a
`semiconductor substrate;
`
`a gate insulating film formed over the active area;
`
`a gate electrode formed over the gate insulating film;
`
`first L-shaped sidewalls formed over the side surfaces of
`the gate electrode;
`
`first silicide layers formed on regions located on the sides
`of the first L-shaped sidewalls within the active area
`
`an interconnection formed on the trench isolation; and
`
`second L-shaped sidewalls formed over the side surfaces
`of the interconnection.
`
`
`
`C. The Prior Art
`
`Petitioner relies on the following prior art:
`
`U.S. Patent No. 4,506,434, issued Mar. 26, 1985
`(Ex. 1010, “Ogawa”);
`
`U.S. Patent No. 5,021,353,
`(Ex. 1017, “Lowrey”);
`
`issued June 4, 1991
`
`5
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`U.S. Patent No. 5,153,145, issued Oct. 6, 1992 (Ex. 1002,
`“Lee”); and
`
`U.S. Patent No. 5,539,229, filed Dec. 28, 1994, issued
`July 23, 1996 (Ex. 1015, “Noble”).
`
`
`
`D. The Asserted Grounds
`
`Petitioner challenges claims 1–12 and 14–18 of the ’174 patent as
`
`unpatentable under 35 U.S.C. § 103(a)3 on the following grounds:
`
`Case Number
`
`References
`
`Claims Challenged
`
`IPR2016-01246
`
`Lee and Noble
`
`1–3, 5–7, 9–12, and 14–18
`
`IPR2016-01246
`
`Lee and Ogawa
`
`1–3, 5–7, 9–12, and 14–18
`
`IPR2016-01247
`
`Lowrey and Noble
`
`1, 4, 5, 8–12, 14, and 16
`
`IPR2016-01247
`
`Lowrey and Ogawa
`
`1, 4, 5, 8–12, 14, and 16
`
`
`
`E. Claim Interpretation
`
`Patent Owner requests, under 37 C.F.R. § 42.100(b), a district
`
`court-type claim interpretation approach, as the ’174 patent expired on July
`
`24, 2016 (after the filing of the Petitions). Mot. 1; -1247 Mot. 1. Petitioner
`
`agrees that the ’174 patent is expired and that the Board should apply the
`
`district court standard. Pet. 16. Patent Owner’s motions are granted.
`
`In district court, claim terms are given their plain and ordinary
`
`meaning as would be understood by a person of ordinary skill in the art at
`
`
`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Because the ’174 patent has an
`effective filing date before the effective date of the applicable AIA
`amendment, we refer to the pre-AIA version of 35 U.S.C. § 103.
`
`
`
`6
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`the time of the invention and in the context of the entire patent disclosure.
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc).
`
`“There are only two exceptions to this general rule: 1) when a patentee sets
`
`out a definition and acts as his own lexicographer, or 2) when the patentee
`
`disavows the full scope of a claim term either in the specification or during
`
`prosecution.” Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362,
`
`1365 (Fed. Cir. 2012).
`
`Petitioner argues that the terms of the challenged claims should be
`
`given their plain and ordinary meaning, but does not propose any specific
`
`interpretations. Pet. 16. Patent Owner proposes various interpretations that
`
`mirror what Patent Owner and a third party agreed to in a related district
`
`court case involving the ’174 patent. Prelim. Resp. 18–20. We also have
`
`considered the district court’s Order interpreting various claim terms of the
`
`’174 patent, dated November 9, 2016. See Ex. 3001, 7–11, App’x A.
`
`However, for purposes of this Decision, we conclude that no claim terms
`
`require interpretation at this time.
`
`
`
`II. DISCUSSION
`
`A. Obviousness Ground Based on Lee and Noble
`(Claims 1–3, 5–7, 9–12, and 14–18)
`
`Petitioner contends that claims 1–3, 5–7, 9–12, and 14–18 are
`
`unpatentable over Lee and Noble under 35 U.S.C. § 103(a), citing the
`
`testimony of Sanjay Kumar Banerjee, Ph.D. as support. Pet. 21–69 (citing
`
`Ex. 1004).4 We are persuaded that Petitioner has established a reasonable
`
`
`4 In each of the instant proceedings, Petitioner filed a copy of Dr. Banerjee’s
`declaration with the Petition as Exhibit 1004. On July 26, 2016, Petitioner
`contacted the Board by email and requested authorization to file corrected
`
`
`
`7
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`likelihood of prevailing on its asserted ground for the reasons explained
`
`below.
`
`
`
`
`
`1. Lee
`
`Lee describes a “field effect transistor with a gate stack formed upon a
`
`semiconductor substrate.” Ex. 1002, col. 1, ll. 57–59. “During fabrication,
`
`three material layers are formed over the gate stack and upon the substrate.
`
`At least the outer two material layers are sequentially anisotropically etched,
`
`creating two spacers adjacent the gate stack (and gate runners).” Id. at
`
`col. 1, ll. 59–63. Lee describes a fabrication process depicted in Figures
`
`11–15. Figure 15 of Lee is reproduced below.
`
`
`
`The device shown above includes, inter alia, field oxide 113 formed on
`
`substrate 111, and spacer layer 121 of silicon nitride or silicon oxynitride.
`
`Id. at col. 6, ll. 47–51, col. 7, ll. 6–16.
`
`
`versions of the declarations, which omitted Dr. Banerjee’s curriculum vitae
`as “Appendix A” due to an alleged clerical error. We authorized the filing
`of the corrected declarations by email on August 29, 2016, and Petitioner
`subsequently filed them as Exhibit 1004 in each proceeding on September
`13, 2016. To avoid any confusion, the original versions of the declarations
`will be expunged. Also, for future reference, the parties are reminded that
`all exhibits must be filed and numbered separately, rather than as an
`“appendix” to another exhibit. See 37 C.F.R. § 42.63.
`
`
`
`8
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`2. Noble
`
`Noble describes “shallow trench isolation (STI) in which the
`
`insulating material is raised above the surface of the semiconductor.”
`
`Ex. 1015, col. 1, ll. 8–10. Noble describes a fabrication process depicted in
`
`Figures 9–13. Figure 13 of Noble is reproduced below.
`
`The device shown above includes, inter alia, raised STI 30, created by
`
`etching to form a trench that is filled with insulating material. Id. at col. 4,
`
`
`
`ll. 40–46, Figs. 3–4.
`
`
`
`3. Level of Ordinary Skill in the Art
`
`Section 103(a) forbids issuance of a patent when “the
`differences between the subject matter sought to be patented
`and the prior art are such that the subject matter as a whole
`would have been obvious at the time the invention was made to
`a person having ordinary skill in the art to which said subject
`matter pertains.”
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007) (quoting 35 U.S.C.
`
`§ 103(a)). Petitioner argues that a person of ordinary skill in the art at the
`
`time of the ’174 patent would have had “(1) the equivalent of a Master of
`
`Science degree from an accredited institution in electrical engineering,
`
`materials science, physics, or the equivalent; (2) a working knowledge of
`
`
`
`9
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`semiconductor processing technologies for integrated circuits; and (3) at
`
`least two years of experience in related semiconductor processing analysis,
`
`design, and development.” Pet. 16 (citing Ex. 1004 ¶ 72). Patent Owner
`
`argues that a person of ordinary skill in the art would have had “at least a
`
`Bachelor’s degree in Electrical, Materials, Mechanical, or Chemical
`
`Engineering, or a related degree, and at least two years of experience
`
`working in semiconductor processing and fabrication, semiconductor
`
`equipment manufacturing, or semiconductor materials.” Prelim. Resp. 18.
`
`The parties’ proposed definitions are similar, but differ, for example,
`
`in that Petitioner would require experience in “semiconductor processing
`
`analysis, design, and development,” whereas Patent Owner would require
`
`experience in “semiconductor processing and fabrication, semiconductor
`
`equipment manufacturing, or semiconductor materials.” Based on the
`
`current record, including our review of the ’174 patent and the types of
`
`problems and solutions described in the ’174 patent and cited prior art, we
`
`agree with Petitioner’s assessment of the level of ordinary skill in the art and
`
`apply it for purposes of this Decision. See, e.g., Ex. 1001, col. 1, l. 13–col.
`
`11, l. 9 (describing previous designs of semiconductor devices with high
`
`integration and high performance, issues with previous designs, and
`
`potential solutions).
`
`
`
`4. Analysis
`
`Petitioner relies on Lee as allegedly teaching all limitations of claim 1
`
`other than a “trench isolation.” Pet. 21, 30–44. Petitioner argues that Lee’s
`
`disclosed device has an isolation (i.e., field oxide 113) surrounding an active
`
`area of a semiconductor substrate (i.e., substrate 111), a “gate insulating
`
`
`
`10
`
`

`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`film” (i.e., gate oxide 115) formed over the active area, a “gate electrode”
`
`(i.e., layer 117 above the source and drain) formed over gate oxide 115,
`
`“first L-shaped sidewalls” (i.e., layer 121) formed over the side surfaces of
`
`layer 117, “first silicide layers” (described in Lee but not shown explicitly in
`
`Figure 15) formed on the sides of the first L-shaped sidewalls within the
`
`active area, an “interconnection” (i.e., layer 117 above field oxide 113), and
`
`“second L-shaped sidewalls” (i.e., layer 121) formed over the side surfaces
`
`of the interconnection. Id. (citing Ex. 1002, col. 3, ll. 9–11, col. 7, ll. 5–16
`
`(disclosing that “spacers 19 and 21 (which are nested beneath spacer 23)
`
`have a generally ‘L-shaped’ appearance (in cross-section),” and layer 121 is
`
`formed “in a manner analogous to that depicted” in the figures depicting
`
`spacers 19 and 21)). Petitioner provides on page 18 of the Petition the
`
`following colored and annotated version of Figure 15 of Lee, which we find,
`
`based on the current record, is consistent with Lee’s disclosure.
`
`The figure above depicts Lee’s device including field oxide 113, which is
`
`formed using LOCOS rather than trench isolation. Id. at 32–33.
`
`
`
`
`
`11
`
`

`
`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`Petitioner relies on Noble as allegedly teaching a “trench isolation,”
`
`citing Noble’s description of STI 30. Id. at 32. Petitioner provides on page
`
`19 of the Petition the following colored and annotated version of Figure 13
`
`of Noble, which we find, based on the current record, is consistent with
`
`Noble’s disclosure.
`
`
`
`The figure above depicts Noble’s STI 30, as well as various components that
`
`are very similar to those of Lee, such as the gate electrode, interconnection,
`
`gate dielectric, source, drain, and silicide regions. Id. at 26–28 (describing
`
`the similar structures of Lee and Noble), 32–33.
`
`Petitioner provides a detailed explanation for why a person of
`
`ordinary skill in the art would have been motivated to replace Lee’s LOCOS
`
`with trench isolation, as taught by Noble, with supporting testimony from
`
`Dr. Banerjee. Id. at 21–30 (citing Ex. 1004 ¶¶ 82–97). For example,
`
`Petitioner argues that due to the bird’s beak problem, which limited the
`
`device density that could be achieved, the industry began moving away from
`
`LOCOS and toward trench isolation. Id. at 22. The ’174 patent states that
`
`“even in . . . mass-production techniques, the isolation forming method ha[d]
`
`
`
`12
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`

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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`started to be changed to the trench isolation method in which the
`
`dimensional change is very small.” Ex. 1001, col. 1, ll. 36–39. Petitioner
`
`also cites a number of other prior art references as evidence that LOCOS and
`
`trench isolation were viewed as alternative methods of isolation, and that a
`
`person of ordinary skill in the art would have considered using trench
`
`isolation rather than LOCOS “a simple substitution of one element for an
`
`equivalent element, according to known methods, to achieve predictable
`
`results.”5 Pet. 24–26; see, e.g., Ex. 1009, col. 2, ll. 20–24 (“Shallow Trench
`
`Isolation (STI) is used primarily for isolating devices of the same type and is
`
`often considered an alternative to LOCOS isolation. Shallow trench
`
`isolation has the advantages of eliminating the birds beak of LOCOS and
`
`providing a high degree of surface planarity.”); Ex. 1014, col. 22, ll. 49–52
`
`(“Although the isolation is composed of the LOCOS film, . . . the present
`
`invention is not limited thereto [and] is also applicable to an isolation of
`
`
`5 Patent Owner notes the additional cited references, but states that its
`arguments only address the prior art references that make up each asserted
`ground. Prelim. Resp. 20. We have reviewed Petitioner’s citations to the
`other references and are persuaded, based on the current record, that they
`appropriately show the background knowledge that a person of ordinary skill
`in the art would have had in reading Lee and Noble, and why a person of
`ordinary skill in the art would have been motivated to make the asserted
`combination. See Ariosa Diagnostics v. Verinata Health, Inc., 805 F.3d
`1359, 1365 (Fed. Cir. 2015); Randall Mfg. v. Rea, 733 F.3d 1355, 1362–63
`(Fed. Cir. 2013). We also agree with Petitioner, based on the current record,
`that the references are prior art because the challenged claims are not
`entitled to the July 27, 1995 filing date of Japanese Patent Application
`No. 7-192181, such that the earliest potential effective filing date would be
`December 19, 1995. See Pet. 14–15 (citing Exs. 1019, 1020); Prelim. Resp.
`20 (not disputing Petitioner’s assertion for purposes of the Preliminary
`Response, but reserving the right to contest the effective filing date during
`trial).
`
`
`
`13
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`Patent 7,126,174 B2
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`trench structure or the like.”). Petitioner further argues that using trench
`
`isolation rather than LOCOS had known advantages, such as increased
`
`device density due to elimination of the bird’s beak. Pet. 29–30 (citing
`
`Ex. 1004 ¶¶ 95–96).
`
`According to Petitioner, a person of ordinary skill in the art would
`
`have understood that “replacing Lee’s LOCOS with trench isolation would
`
`have been entirely compatible and not affected gate formation, source/drain
`
`formation, L-shaped sidewall formation, silicide formation, or any other
`
`aspect relevant to the challenged claims.” Id. at 25. Dr. Banerjee elaborates
`
`as to why an ordinarily skilled artisan would have been able to make the
`
`combination, opining that “LOCOS and STI are both methods for forming
`
`insulating materials in the same locations of the substrate to perform the
`
`same function,” and “[t]hey are both performed near the very beginning in
`
`device processing, and how the isolation regions are formed would not affect
`
`Lee’s processes or the resultant device structures.” Ex. 1004 ¶ 82. Upon
`
`review of the parties’ papers, we are persuaded that Petitioner has shown a
`
`reasonable likelihood of prevailing on its challenge to claim 1.
`
`Patent Owner makes three arguments regarding claim 1, citing the
`
`testimony of E. Fred Schubert, Ph.D., as support. Prelim. Resp. 2–41 (citing
`
`Ex. 2001). First, Patent Owner’s primary argument is that Petitioner
`
`proposes simply replacing Lee’s LOCOS with Noble’s trench isolation,
`
`without describing exactly how and when the substitution would be
`
`accomplished during the fabrication process. Id. at 10–12. Patent Owner
`
`argues that
`
`[t]he Petition fails to address the fact that when
`combining references relating to semiconductor devices, the
`process (“process sequence”) by which the integrated circuit
`
`
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`14
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`Patent 7,126,174 B2
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`
`(IC) devices are formed is inseparable from their final structure
`as claimed. As such, simply substituting a component from one
`device, e.g., STI, for a different component in another device,
`e.g., LOCOS isolation, can provide unworkable results, both in
`terms of how the substituted component cooperates with other
`components, and how the changed manufacturing sequence,
`which is required to effectuate such substitution, can be
`implemented. This is particularly true for Si ICs where a single
`film can serve multiple purposes, and where a multitude of
`different functional features are condensed into a minimum
`number of layers and processing steps.
`
`Id. at 10–11 (citations omitted).
`
`Patent Owner contends that, when the fabrication processes of each
`
`reference are considered, a person of ordinary skill in the art would not have
`
`been led to replace Lee’s LOCOS with Noble’s trench isolation because the
`
`initial processing sequence of Noble is opposite that of Lee. Id. at 27–33.
`
`Specifically, Lee forms its field oxide before depositing the gate dielectric
`
`and gate conductor film, whereas Noble forms its STI after deposition of the
`
`gate dielectric film and gate conductor film (and then planarizes the
`
`substrate surface). Id. at 27–28 (citing Ex. 1015, Fig. 9). As a result,
`
`Noble’s trench etching provides the boundaries for the gate conductor,
`
`whereas in Lee the gate conductor would partially wrap around the LOCOS
`
`isolation area. Id. at 28–33. Patent Owner provides an illustration on page
`
`30 of its Preliminary Response, a portion of which is reproduced below.
`
`
`
`15
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`Patent 7,126,174 B2
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`Patent Owner’s diagram depicts a cross-sectional view of Noble’s layering
`
`on the left and Lee’s layering on the right. According to Patent Owner,
`
`Noble specifically chose its sequence to avoid adverse effects of the gate
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`conductor wrapping around the trench corner. Id. at 31–33 (citing Ex. 1015,
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`col. 1, l. 20–col. 2, l. 22, col. 2, ll. 30–35; Ex. 2001 ¶¶ 117–20).
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`Patent Owner similarly argues that, when the fabrication processes of
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`each reference are considered, a person of ordinary skill in the art would
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`have found the processes incompatible because (1) due to the ordering of
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`steps, Lee’s deposition of the gate dielectric and gate conductor would have
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`to be applied on top of Noble’s pre-existing structure, making the combined
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`device inoperative; (2) “it would completely undermine the Noble process to
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`go directly to trench isolation formation, and leave out the initial formation
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`of the gate dielectric and gate conductor”; and (3) following Noble’s
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`ordering in Lee’s fabrication process “would completely destroy the Lee
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`structure and undermine its design because Lee’s design would lose its
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`hallmark feature of using the same layer stack for the gate and interconnect
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`stack.” Id. at 33–36 (citing Ex. 2001 ¶¶ 121–27).
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`We have reviewed Patent Owner’s arguments and the testimony of
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`Dr. Schubert, but do not find them persuasive based on the current record
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`and stage of the proceeding. Claim 1 is an apparatus claim, not a method
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`claim. It recites a “semiconductor device” comprising various physical
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`components, including a “trench isolation,” but does not recite anything
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`about how those components are formed. Thus, Petitioner’s contentions
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`appropriately are directed to how the cited prior art teaches each component
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`of the claimed device. See Pet. 21–44. Indeed, Patent Owner does not
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`appear to dispute in its Preliminary Response that Lee and Noble,
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`collectively, teach all of the recited components.6 The record further
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`indicates, as explained above, that there were known ways to fabricate a
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`semiconductor device with a LOCOS isolation structure and known ways to
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`fabricate a semiconductor device with a trench isolation, both of which were
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`within the skill level of an ordinarily skilled artisan. See id. at 4–7, 22–23,
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`31–33; Ex. 1002, col. 6, l. 46–col. 7, l. 52 (Lee’s fabrication process,
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`including forming field oxide 113); Ex. 1015, col. 3, l. 35–col. 6, l. 31
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`(Noble’s fabrication process, including forming STI 30); Ex. 1001, col. 1,
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`ll. 17–51 (the ’174 patent stating that both methods were known and that
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`trench isolation was known to be “more advantageous for manufacturing a
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`refined semiconductor device”); Prelim. Resp. 16 (acknowledging the
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`’174 patent’s disclosure of trench isolation in the prior art).
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`Petitioner also provides reasons why a person of ordinary skill in the
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`art would have been motivated to replace Lee’s LOCOS with Noble’s trench
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`isolation, and, importantly, evidence that persons of ordinary skill in the art
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`viewed the two methods as substitutes, with trench isolation having certain
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`known advantages over LOCOS (such as eliminating the bird’s beak). See
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`Pet. 21–30. Finally, Dr. Banerjee opines that a person of ordinary skill in
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`the art would have been able to replace Lee’s LOCOS with Noble’s trench
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`isolation and fabricate the resulting device. See Ex. 1004 ¶ 82; Pet. 24–25.
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`Given this evidence, we conclude that Dr. Schubert’s conflicting
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`testimony creates genuine issues of material fact as to whether a person of
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`6 Patent Owner argues that “Petitioner has failed to provide the actual
`process sequence it is contemplating [for the combined device of Lee and
`Noble]. To properly establish obviousness, disclosure of the sequence is
`necessary.” Prelim. Resp. 36–37. Patent Owner does not cite any authority
`for this proposition, and we are aware of none.
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`ordinary skill in the art would have been motivated and able to fabricate the
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`semiconductor device of Lee, replacing its LOCOS with trench isolation as
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`taught by Noble. Compare Ex. 1004 ¶¶ 82–96, with Ex. 2001 ¶¶ 109–30.
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`We view those issues in the light most favorable to Petitioner at this stage of
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`the proceeding. 37 C.F.R. § 42.108(c). Based on the current record,
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`Petitioner’s evidence is sufficient to demonstrate a reasonable likelihood of
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`prevailing on its asserted ground as to claim 1. The ultimate assessment of
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`that evidence will be based on the complete record at the end of trial, after
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`cross-examination of the parties’ declarants and briefing from the parties.
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`Second, Patent Owner argues that Noble’s gate stack and
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`interconnection stack have different heights, such that fabricating “L-shaped
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`sidewalls” on such structures as recited in claim 1 “would require
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`re-engineering of Lee’s sidewall fabrication module,” and Petitioner does
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`not explain how such re-engineering would be done. Prelim. Resp. 38
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`(citing Ex. 2001 ¶ 131). We are not persuaded based on the current record.
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`Petitioner relies on Lee for the “L-shaped sidewalls,” “gate electrode,” and
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`“interconnection” limitations of apparatus claim 1, and relies on Noble for
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`the “trench isolation.” See Pet. 30–44. As Petitioner points out, Lee
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`discloses a process for forming the L-shaped sidewalls on the sides of the
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`gate electrode and interconnection. See id. at 37–38, 43–44 (citing
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`Ex. 1002). It is unclear why the fact that Noble has different heights for its
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`stacks would impact the combination, as Petitioner relies on Lee—not
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`Noble—for the stack components.
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`Third, Patent Owner contends that in Petitioner’s asserted
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`combination (substituting Noble’s trench isolation for Lee’s LOCOS),
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`Petitioner does not explain “how the salicidation of Lee could be
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`accomplished given the difference in how the structures of Lee and Noble
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`are formed.” Prelim. Resp. 39 (citing Ex. 2001 ¶¶ 132–33). Again, Patent
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`Owner’s arguments are not persuasive on this record. Petitioner relies on
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`Lee for the “silicide layers,” and explains sufficiently how Lee teaches a
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`process for forming those layers on the sides of the L-shaped sidewalls
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`(a component for which Petitioner also relies on Lee). See Pet. 36–40.
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`Based on the current record, we are persuaded that Petitioner’s
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`evidence is sufficient to demonstrate a reasonable likelihood of prevailing as
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`to claim 1. We also have reviewed Petitioner’s arguments and supporting
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`evidence regarding dependent claims 2, 3, 5–7, 9–12, and 14–18, which
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`Patent Owner does not argue separately in its Preliminary Response.
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`Petitioner has demonstrated, on this record, a reasonable likelihood of
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`prevailing on its assertion that claims 1–3, 5–7, 9–12, and 14–18 are
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`unpatentable over Lee and Noble.
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`
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`B. Obviousness Ground Based on Lee and Ogawa
`(Claims 1–3, 5–7, 9–12, and 14–18)
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`Petitioner contends that claims 1–3, 5–7, 9–12, and 14–18 are
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`unpatentable over Lee and Ogawa under 35 U.S.C. § 103(a), citing the
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`testimony of Dr. Banerjee as support. Pet. 70–85 (citing Ex. 1004). We are
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`persuaded that Petitioner has established a reasonable likelihood of
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`prevailing on its asserted ground for the reasons explained below.
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`1. Ogawa
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`Ogawa describes “methods for production of buried insulating layers
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`each of which surrounds a portion of a semiconductor substrate in which
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`elements are fabricated, the buried insulating layers functioning to isolate
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`from one another.” Ex. 1010, col. 1, ll. 8–15. Ogawa describes LOCOS and
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`its associated “bird’s beak” problem. Id. at col. 1, ll. 17–60. According to
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`Ogawa, LOCOS “is not necessarily satisfactory for the production of a
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`semiconductor device having minute patterns,” and other methods, such as
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`where “each element is isolated from one another by buried insulating layers
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`which are grown to fill grooves produced along the surface of a silicon (Si)
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`substrate to surround each element,” were developed to overcome the
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`drawbacks of LOCOS. Id. at col. 1, ll. 58–68. Ogawa describes a
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`fabrication process depicted in Figures 4(a)–(c) and 5(a)–(c). Figure 5(c) of
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`Ogawa is reproduced below.
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`The figure above shows a device including, inter alia, portion 52, created by
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`etching to form a groove that is filled with silicon dioxide. Id. at col. 6,
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`ll. 16–59, col. 7, ll. 40–47, Figs. 4(b)–(c) (silicon dioxide layer 47 in groove
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`
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`45).
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`
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`2. Analysis
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`Petitioner’s arguments regarding the combination of Lee and Ogawa
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`are similar to those made with respect to Lee and Noble. Petitioner relies on
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`Lee as allegedly teaching the majority of