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`USU06161 160A
`
`United States Patent
`Niu et at.
`
`[19]
`
`[11] Patent Number:
`
`6,161,160
`
`[45] Date of Patent:
`
`I)ec. I2, 2000
`
`[54] NETWORK INTERFACE DEVICE
`ARCHITECTURF. FOR STORING TRANSMIT
`AND RECEIVE DATA IN A RANDOM
`ACCESS BUFFER MEMORY ACROSS
`INDEPENDENT CDOCK DOMAINS
`
`[75]
`
`Inventors: Autumn J. Nlu, Sunnyvale; Jerry
`Chttn-Jen Kilo; Po-shen Lai, both of
`San Jose, all of Calif.
`
`W3] Assignce: Advanced Micro Devices, Inc.,
`Sunnyvale, Calif.
`
`[21] Appl. No; 09,t'l46,l63
`
`[22
`
`Filed:
`
`Sep. 3, 1998
`
`[S2] U.S. Cl.
`
`[51]
`
`[58]
`
`[56]
`
`Int. (31.7 .......................... .. G(l6F 13,86; (10617 13,312;
`GOGF ISI76; H041. 12;‘54; HU4l.
`l2i’413
`............................ ..
`':'lll,t129; ?l0;‘52; 710,66;
`710957; 710158; 71Ui’t‘JU; 710E130; 709E213;
`7092234; '}’{)9f236; 714-I805; 714811
`Field of Search
`...... .. 7].Ur’61, 52, 56,
`710.557, 58, 60, 1-9, 105, 130; 713E400,
`600; 709213, 334, 236; 71332; 714805,
`811; 370x381, 517, 463
`
`References Cited
`U.S. l’Al"1-lN'l' DOCUMlE.N'l‘S
`
`5,406,554 M1995 Parry ..................................... .. 3?EL"38l
`5_.434.8?2
`7i"l995 Petersen et al.
`.. 714E811
`5,524,218
`631996 Byers et al.
`.
`.. 710E129
`5,53:;5ss meets. Mundku:
`.. 11n,vt2<.:
`.
`5,592,630
`lg'l99'i-" Yamagztmi el al.
`..
`'.-"ll,-'11?
`5.659.799
`3.-“I997 Wtl et all.
`.......... ..
`TIU.-'57
`S,?32,tl‘J4 M1998 Petersen et al.
`.. 714E805
`S,8(t(J,02l
`1.-‘I999 Klingntan ................................ .. ?12i’32
`
`
`
`Printarjv Exaritiner—Thornas C. Lee
`/t.';s.rlstam Exmttiner—-l(atharina Schuster
`
`[57]
`
`ABSTRACT
`
`A network interface device includes a random access trans-
`rrtit buffer and a random access receive butler [or transmis-
`sion and reception of transmission and receive data frames
`between a host computer bus and a packet switched network.
`The network interface device includes a memory manage-
`ment unit having read and write controllers for each of the
`transmit and receive bullets, where each write controller
`operates in a clock domain separate from the corresponding
`read controller. The memory management unit also includes
`a synchronization circuit that controls arbitration for access
`ing the random access memories between the read and write
`controllers. The synchronization circuit asynchronously
`monitors the amount of data stored in the random access
`transmit and receive buffer by asynchronously comparing
`write pointer and read pointer values stored in gray code
`counters, where each counter is configured for changing a
`single bit of a counter value in response to an increment
`signal. A descriptor management unit
`is used to control
`DMA reading and writing of transmit data and receive data
`from and to system memory, respectively, based on descrip-
`tor lists, respectively. A pipelining architecture also opti-
`mizes transfer of data between the buffers, the PCI bus, and
`the media access controller.
`
`38 Claims, 11 Drawing Sheets
`
`‘t‘1t},t5’i'
`'.r'IU,’fi1
`3'.-l[!,.’5 i7
`.. 386,390
`37r.ir4e3
`7'09,-"236
`7'09.-"213
`'.n't)9t'234
`'t'1t.iflf.l5
`
`.
`
`..
`..................... __
`
`5,rt9*:2 llikosaka ................................ ..
`_3_,sr;5,41o
`4,tl9Tr‘3 Koe elal.
`..
`3.?29,?l?
`H1978 l-lenrion el al.
`4_I|7o,‘)64
`831986 I-lihino et al.
`4_.604_,658
`3.=t99t_t Uulick cl al.
`4,907,225
`5,2?4,?()S l2,"l9FJ3 Traw at al.
`5,276,896
`H1994 Rimmer el al.
`5,299,313
`3.31994 Petersen ct al.
`5,315,706 H1994 Tltomsort ct al.
`
`
`
`u_mI_srro gr. Ilust. aim. 11}
`taunt
`r:_sm_otI-rt [Tn Don-. um... :4}
`term
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`
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`32
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`‘flu Du: l!_||_t14l
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`ElWrill PII.
`m
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`i:t_sm _A'HtIl [Tu um. um, 24:
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`t:_5i.tu_Etm\' [Ia Dost. Ilgmt. til
`
`APPLE 1012
`
`APPLE 1012
`
`1
`
`

`
`U.S. Patent
`
`Dec. 12, 2000
`
`Sheet 1 of 11
`
`6,161,160
`
`Figure 1
`
`Figure 1A
`
`Figure 1B
`
`TRAN SMIT LL
`
`2
`
`

`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 2 of 11
`
`6,161,160
`
`A t
`"° II
`Negotiation
`
`3
`
`

`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 3 of 11
`
`6,161,160
`
`4
`
`

`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 4 of 11
`
`6,161,160
`
`Figure 3
`
`64/V7
`
`D LAST
`
`STATUS LowerT
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`
`TX_BUF_ADDR_!.WR
`TX_BUF_ADDRwUPR
`0551 SPACE
`
`BUF LENGTH
`
`5
`
`

`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 5 of 11
`
`6,161,160
`
`Figure 4
`
`22a
`
`TX_FREE_BYTES [To Desc. Mgmi. 24)
`[BCLK)
`
`TX_SRAM_EMPTY (Tu Dost. Mgmt. 24)
`(BCLK)
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`6
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`

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`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 7 0f 11
`
`6,161,160
`
`209
`
`202
`
`Receive Descriptor Index for Tx/Rx
`Descriptor Information from Host
`
`Retrieve Tx/Rx Descriptor Info from
`System Memory
`
`204
`
`Decode Descriptor Info (System Address,
`Length, Etc.)
`
`205
`
`Transfer Tx/Rx Frame Data Between
`System Memory via PCI bus
`
`208
`
`Write Txl Rx Status Info to
`
`System Memory
`
`Figure 7
`
`8
`
`

`
`U.S. Patent
`
`Dec. 12,2000
`
`Sheet 8 of 11
`
`6,161,160
`
`5SEE
`
`9
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`

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`Dec. 12, 2000
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`

`
`6,161,160
`
`1
`NETWORK INTERFACE DEVICE
`ARCHI'I‘EC"I'URlE FOR STORING TRANSMIT
`AND RECEIVE DAT/\ IN A RANDOM
`ACCESS BUFFER MEMORY ACROSS
`INl)EPENI)IiJN'I‘ CLOCK DOMAINS
`
`BACKGROUND OI’ TI-IE INVl:‘N'1'l0N
`
`1. Technical Field
`
`The present invention relates to network interfacing and
`more particularly, to methods and systems for buffering data
`between a host bus interface and a media access controller
`accessing Ethernet (IEEE 802.3) media.
`2. Background Art
`Network interface devices handle packets of data for
`transmission between a host computer and a network com-
`mu nications system, such as a local area network. The host
`computer may be implemented as a client station, a server,
`or a switched hub. One primary function of the network
`interface device is to buffer data to compensate for timing
`discrepancies between the clock domain of the host com-
`puter and the clock domain of the network.
`Network interface devices typically include a first in, first
`out (FIFO) bulfer memory for storing transmit and receive
`data, where the transmit data is stored in a transmit FIFO
`prior to transmission on the network media by the MAC, and
`receive data is stored in a receive F II"O by the MAC prior
`to transfer to the host computer via the host computer bus
`interface.
`
`One disadvantage with the use of a FIFO for a transmit
`bu ifer or a receive butfer is the increased latency encoun~
`tercd during the buffering process. The latency of the
`network interface device is the time delay between the time
`that it data frame is supplied to the network interface device
`and the time the data is transmitted on the network media,
`or vice versa.
`
`An additional disadvantage with the use of a FIFO for
`transmit buffer or receive buffer is the increasing complexity
`associated with maintaining status information for each data
`frame stored in the FIFO butler. If a stored data frame is to
`have corresponding status information, then an additional
`FIFO buffer would be required for storing the status infor-
`mation for each stored data frame. Hence, a transmit buffer
`may require a data frame FIFO for the actual frame data, and
`a status FIFO for storing the corresponding status informa-
`tion for each data frame. Such an arrangement would result
`in a substantial increase in the amount of area required on a
`chip for the status FIFO. In addition, additional synchroni-
`zation logic would be required to maintain correspondence
`between the stored frame data and the corresponding status
`data,
`increasing the cost and complexity of the network
`interface device.
`
`10
`
`15
`
`30
`
`35
`
`40
`
`45
`
`50
`
`An additional problem caused by the buffering of data
`between the clock domain of the host computer and the
`clock domain of the network interface device is buffer _
`overflow or underflow. For example, buffer overflow can
`occur when the time domains between the host bus and the
`network media are uncontrollable to the extent that data is
`stored in the buffer at a rate faster than the data can be
`removed, resulting in an overflow situation. Conversely,
`underflow occurs if data is removed from the FIFO buffer
`faster than the data can be supplied.
`Hence,
`the non—synchronous relationship between the
`host bus clock domain and the network clock domain have
`required the necessity of FIFO buffers to compensate for
`timing discrepancies between the host computer and the
`network.
`
`60
`
`65
`
`2
`Another fundamental problem with use of a FIFO as a
`transmit buffer or receive bulfer is that there is no convenient
`way for the network interface device to bypass, or "flush,"
`invalid data. For example, if the media access controller
`receives a mat packet from the network (i.e., an invalid
`packet
`less than the minimum required frame size of 64
`bytes), the MAC cannot cause the invalid data stored in the
`FIFO to be llushed, without eliminating the entire contents
`of the receive FIFO. Hence, the invalid data is transferred
`via the host computer bus and stored in host computer
`memory, before the host computer can determine that the
`transferred data is invalid. The reduction in throughput may
`have substantial elfects, especially in full-duplex networks,
`where the host computer bus is heavily utilized by the
`network interface device for simultaneous transmission and
`reception of data frames on the network medium.
`An additional problem encountered with conventional
`network interface devices is the latency encountered during
`host bus transfers. In particular, two types of bus transfers
`may be used, namely master mode and slave mode.
`In
`master mode,
`the network interface device operates as a
`master, and initiates the transfer of data across the host bus
`by requesting use of the bus, and then transferring the data
`as a data burst. One example of a host bus is the peripheral
`component interconnect (I-‘C'I) local bus, where a transfer of
`data over a PCI bus includes an address phase followed by
`one or more contiguous data phases. The PCI bus protocol
`makes use of a centralized, synchronous arbitration scheme
`in which each PCI master must arbitrate for each transaction
`by use of a request signal and a grant signal. For example,
`at network interface device having data to transfer (e.g..
`either receive data or transmit data) will assert a request
`signal to request use of the bus. Typically, a host CPU will
`respond with a grant signal which is followed by assertion
`of a frame signal
`that together identify when the bus is
`available for use by the network interface.
`One problem in conventional network interface devices is
`the occurrence of wait states following an address phase on
`the PCI bus. Such wait states cause increased latency on the
`PCI bus, further reducing the overall
`throughput of the
`network interface device.
`
`An additional problem with conventional network inter-
`face devices is the occurrence of wait states encountered
`during a complex bus termination condition, where certain
`events on the PCI bus forcibly halt a PCI bus data transfer.
`Two examples of complex conditions include when a host
`memory is not ready to receive a data transfer after the bus
`has been secured, or when the host memory becomes unable
`to continue receiving Qlata following initiation of the data
`transfer. In either case, the target asserts a STOW?‘ signal on
`the PCI bus to terminate the data transfer. Prior art systems
`frequently lose data from the FIFO bulfer memory in
`response to encountering such complex conditions,
`for
`example retry or disconnect states. Hence, complicated
`recovery arrangements are conventionally required in prior
`art systems to mitigate the loss of data. For example, higher
`network protocol layers may need to send a message across
`the network, requesting the transmitting station to resend a
`data packet.
`DISCLOSURE OF THE IN Vl:‘.N'l'lON
`
`There is a need for an arrangement that enables use of a
`random access memory in a network controller, as opposed
`to a l"'Il"O bulfer, to compensate for timing discrepancies
`between the host computer and the network.
`There is also a need for an arrangement enabling the use
`of a random access memory as a bulier
`in a network
`
`13
`
`13
`
`

`
`6,161,160
`
`3
`interface device, where potential synchronization problems
`between the clock domain of the host computer and the
`clock domain of the network are resolved to enable efficient
`control of the random access memory during the writing and
`reading of transmit or receive data.
`in a network
`There is also a need for an arrangement
`interface device, where a synchronization circuit controls
`priority between writing and reading operations to and from
`the random access memory to enable efficient memory
`management for monitoring the status of stored frame data.
`There is also a need for an arrangement in a network
`interface device, where a network interface architecture
`asynchronously monitors the status of data stored in a
`random access transmit bu tIer and a random access receive
`buffer to enable multiple memory controllers to store and
`read data into the random access memories using multiple
`clock domains.
`
`an
`
`ID
`
`tour-
`
`40
`
`in a network
`There is also a need for an arrangement
`interface device having a memory controller that enables
`¢':lC»l'.'CSS I0 3 I'EIl'l(_l{.)f1'l access T.l'¢':ll'lSlTIll bll fl"C]' OI’ 3 ffl['ILlOI'['I EICCBE-i-5':
`receive buffer according to either a direct memory access
`(DMA) or slave access.
`in a network
`There is also a need for an arrangement
`interface device having a circuit that asynchronously moni-
`tors the status of a random access transmit buffer and a
`random access receive buffer, enabling memory controllers
`to operate in response to prescribed conditions detected by
`the synchronization circuit.
`These and other needs are attained by the present
`invention, where a memory management unit, configured for
`controlling transfer of transmit data and receive data into
`respective random access transmit and receive but]'ers,
`includes a synchronization circuit for asynchronously moni-
`toring the amount of data stored in the random access ‘
`transmit hutIer and the random access receive butler. The
`asynchronous monitoring by the synchronization circuit
`enables memory management unit operations to be per-
`formed in respective independent clock domains.
`According to one aspect of the present
`invention, a
`method in a network interface device for sending data
`frames from a host computer to a network medium com-
`prises storing transmit data received from a host bus into a
`random access transmit buffer according to a host bus clock,
`asynchronously monitoring the amount of data stored in the
`random access transmit buffer, and outputting the stored
`transmit data from the random access transmit buflfer to a
`media access controller according to a transmit clock inde-
`pendent from the host bus clock and based on the asynchro-
`nously monitoring step, for transmission on the network
`medium. The asynchronous monitoring of the amount of
`data stored in the random access transmit buffer enables the
`transmit data to be stored in the random access transmit
`buffer according to the host bus clock domain, and also
`enables the transmit data to be output from the random
`access transmit butfer according to a network transmit clock,
`independent from the host bus clock, with minimal latency
`in the network interface device. Since the amount of data
`stored in the random access transmit buffer is monitored
`asynchronously, operations in the network interface device
`may be performed on an event-driven basis, where the
`asynchronous detection of events within the random access
`transmit buffer enables optimized performance in the appro-
`priate clock domain.
`Another aspect of the invention provides a method in a
`network interface device for receiving data frames from a
`network medium to a host computer, comprising storing
`
`60
`
`65
`
`14
`
`4
`receive data received from a media access controller into a
`random access receive buffer according to a network receive
`clock, asynchronously monitoring the amount of data stored
`in the random access receive butter, and outputting the
`stored receive data from the random access receive buffer to
`a host bus interface according to a host bus clock indepen-
`dent from the network receive clock and based on the
`asynchronously monitoring step, for transmission on a host
`bus.
`
`Still another aspect of the present invention provides a
`network interface device comprising a media access con-
`troller configured for simultaneously outputting transmit
`data according to a network transmit clock, and receiving
`receive data from a network medium according to a network
`receive clock, a bus interface unit configured for transferring
`via a host bus the receive data and the transmit data to and
`from a host computer memory according to a host bus clock,
`a random access receive buffer configured for storing the
`receive data received by the media access controller accord-
`ing to the network receive clock, and outputting the stored
`receive data to the bus interface unit according to the host
`bus clock, a random access transmit butfer configured for
`storing the transmit data supplied by the bus interface unit
`according to the host bus clock, and outputting the stored
`transmit data to the media access controller according to the
`network transmit clock, and a memory management unit.
`The memory management unit is configured for controlling
`the transfer of the transmit data and receive data in the
`random access transmit buffer and the random access
`receive buffer, and includes a synchronization circuit for
`asynchronously monitoring the amount of data stored in the
`random access transmit butIer and the random access
`receive buffer. The asynchronous monitoring by the syn-
`chronization circuit enables the memory management unit to
`interact with the media access controller, the bus interface
`unit, and the random access transmit and receive buffers on
`an event-driven basis, where operations can be performed in
`the appropriate clock domain based on the asynchronous
`monitoring of events in the synchronization circuit.
`This aspect of the network interface device is particularly
`advantageous in the case where the memory management
`unit
`includes first, second, third, and fourth management
`blocks configured for controlling the transfer of transmit
`data to and from the random access transmit bufler, and
`receive data to and from the random access receive bu ffer,
`respectively. Hence, each of the management blocks can be
`optimized for performing its corresponding memory func-
`tions in its corresponding clock domain by obtaining any
`relevant status information from the synchronization circuit.
`llence, the network interface device can be configured for
`eificient transfer of transmit and receive data. in a manner
`that eliminates any contention issues between the host bus
`clock, the network transmit clock or the network receive
`clock.
`
`Additional objects, advantages and novel features of the
`invention will be set forth in part in the description which
`follows, and in part will become apparent to those skilled in
`the art upon examination of the following or may be learned
`by practice of the invention. The objects and advantages of
`the invention may be realized and attained by means of the
`instrumentalities and combinations particularly pointed out
`in th e appended claims.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Reference is made to the attached drawings, wherein
`elements having the same reference numeral designations
`represent like elements throughout and wherein:
`
`14
`
`

`
`6,161,160
`
`5
`FIGS. 1A and 1B show block diagrams illustrating how
`the systems in FIGS. IA and 1B are coupled together;
`FIGS. 1A and 1B illustrate an exemplary network inter-
`face device including a synchronization circuit for control-
`ling buffer memory controllers according to an embodiment
`of the present invention;
`FIG. 2 is a block diagram illustrating the bul1"er architec-
`ture of the network interface device of FIG. 1 according to
`an embodiment of the present invention.
`FIG. 3 is a diagram illustrating an exemplary data struc-
`ture of a data frame stored in the random access memory of
`FIGS. 1 and 2.
`
`FIG. 4 is a block diagram illustrating in detail the archi-
`tecture of the memory management unit of FIG. 2 according
`to an embodiment of the present invention.
`FIGS. 5/-\ and 513 are diagrams illustrating storage con-
`ditions when the receive memory of FIG. 2 stores at least
`one full frame of data and less than one full frame of data,
`respectively.
`FIG. 6 is a diagram illustrating descriptor lists stored in
`system memory for use by the descriptor management
`controller of FIG. 2.
`
`FIG. 7 is a diagram illustrating a method of transferring
`frame data by the descriptor management 18 between sys-
`tern memory and the random access buffer memories.
`FIGS. 8A, 8B, 8C, and SD are block diagrams illustrating
`holding registers used to butler data input to the transmit
`random access memory, output from the transmit random
`access memory, input to the receive random access buffer
`memory, and output from the receive random access buffer
`memory, respectively.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`The present invention will be described with the example
`of a network interface device in a packet switched network,
`such as an Ethernet (IEEE 802.3} network. A description
`will
`first be given of a network interface architecture,
`followed by the arrangement for monitoring the storage of a
`data frame in a buffer memory, independent of host com-
`puter clock and network data clock domains. It will become
`apparent, however, that the present invention is also appli-
`cable to other network interface device systems.
`
`Nl:iTWORK lN'I“l£Rl"ACE ARCHI'I'l:'('.T'I'URl£
`
`is a block diagram of an exemplary network
`1
`FIG.
`interface device 10 that accesses the media of an Ethernet
`(ANSUIEEE 802.3) network according to an embodiment of
`the present invention.
`The network interface device 10, preferably a single-chip,
`32-hit Ethernet controller, provides an interface between a
`local bus 12 of a computer,
`for example a peripheral
`component interconnect (PCI) local bus, and an Ethernet-
`based media 50.
`
`The interface 10 includes a PCI bus interface unit 16, a
`buffer memory portion 18, and a media access controller
`interface device (MAC) 20. The PCI bus interface unit 16
`includes a PCI slave interface 16:: and a DMA interface 16b.
`The slave interface l6rt manages PCI control and status
`information including reading and programming of the PCI
`status registers, but may also be configured for managing
`slave transfers via the PCI bus with a host CPU. The DMA
`interface 16!) manages DMA transfers by the network inter-
`face device 10 to and from system memory. Hence, the PCI
`
`6
`bus interface unit 16 can be selectively configured lhr PCI
`transfers in slave andfior master (e.g., DMA) mode.
`The memory portion 18 includes a 32-bit SRAM imple-
`mented directly on the network interface device 10. Accord-
`ing to the disclosed embodiment,
`the SRAM 18 may be
`accessed in a random access manner under the control of a
`memory management unit 22, or may be segmented into a
`receive portion 18:: and a transmit portion 18b for receive
`and transmit paths, respectively.
`The network interface device 10 also includes a butler
`management unit 24 configured for managing DMA trans-
`fers via the DMA interface 16b. The buffer management unit
`24 manages DMA transfers based on DMA descriptors in
`host memory that specify start address,
`length, etc. The
`buffer management unit 24 initiates a DMA read from
`system memory into the transmit bulfer 18!: by issuing an
`instruction to the DMA interface 16b, which translates the
`instructions into PCI bus cycles. Hence, the buffer manage-
`ment unit 24 contains descriptor management for DMA
`transfers, as well as pointers associated with storing and
`reading data from the memory portion 18. Although the
`buffer management unit 24 and the memory management
`unit 22 are shown as discrete components, the two units may
`be integrated to form a memory management unit control-
`ling all transfers of data to and from the memory unit 18.
`The MAC‘ 20 includes a MAC core 26, a general purpose
`serial
`interface (GPSI) 28, a media independent
`interface
`(Mil) 30 for connecting to external 10 Mbfs or 100 Mhfs
`physical (PHY) transceivers, an external address detection
`interface (EADI) 32. an attachment unit interface (AUI) 34
`having a Manchester encoder and decoder, and a 1Uf.I.UU
`Mbls twisted pair transceiver media attachment unit (MAU)
`36.
`The network interface device 10 also includes a network
`port rnanager38 configured for performing MII handshaking
`between two devices on an M11 bus via the M11 port 30. Such
`Mil handshaking may include link information, program-
`ming information at the MI] layer using a management data
`clock (MDC), and management data inputfoutput (MDIO)
`paths.
`The auto-negotiation portion 40 performs lEEE-
`compliant negotiation with a link partner on the PHY layer
`to exchange data indicating whether the link partner is
`capable of operating at 10 Mbfs, 100 Mbfs, and whether the
`link should be half—duplex or full—duplex.
`The LED controller 44 selectively controls the generation
`of LED output signals based upon the internal decoding
`logic and network interface device status registers (not
`shown). The network interface device 10 also includes an
`IEEE 1149.1-compliant ITAG boundary scan test access
`port interface 36.
`The EEPROM interface 42 connects to an E-Ll_il’ROM on
`either a network interface device adapter card or the moth-
`erboard of the host computer via a serial interface link. The
`EEPROM (not shown in FIG. 1) will be programmed with
`configuration information related to the network interface
`device, enabling the network interface device to be config-
`ured during initialization via the EEPROM interface 42.
`Once initialized.
`the network interface device stores the
`configuration information in internal registers (not shown),
`enabling the network interface device to operate indepen-
`dently of the host computer in the event the host computer
`is powered down. Hence, the network interface device can
`be configured to operate while the host computer is in a
`stand-by mode, enabling the network interface device to
`output power up information to logic within the host com-
`
`I0
`
`15
`
`“
`
`30
`
`35
`
`40
`
`45
`
`50
`
`_
`
`60
`
`65
`
`15
`
`15
`
`

`
`6,161,160
`
`7
`puter to enable the host computer to automatically turn on in
`response to data packets received from the network and
`having a specific protocol, described below.
`
`MEMORY MANAGEMENT ARCHITECTURE
`
`8
`RX_SRAM 180 is read and output to the BIU 16 via data
`path 62:: under the control ofthe receive-data read controller
`22-tr, which reads the frame synchronous to the PCI bus clock
`signal.
`Similarly, transmit data to be output onto the network by
`the MAC 20 is written into the TX SRAM 18b via data
`path 62!) under the control of the transmit-data write con-
`troller 22a, configured for writing the frame data synchro-
`nized to the PCI bus clock (CLK). The stored transmit data
`is read and output from the 'I‘X__SR/\M 18b to the MAC 20
`under the control of the transmit-data read controller 22!)
`according to the MAC transmit clock (TX _CI.K) within the
`network clock domain 56b.
`
`The presence of two separate clock domains 56:: and 56!:
`in writing and reading to a random access memory 18
`requires that the write controller and read controller devices
`be coordinated and synchronized to ensure that no conten-
`tion issues arise due to the relative independence of the two
`clock domains 56:: and 56b. The SRAM MMU 22 includes
`a synchronization circuit 60 that asynchronously monitors
`the status of the RX_SRAM 18:: and the 'l‘X_SRAM 18b,
`enabling the memory management blocks 22a, 22b, 22c, and
`220? to read and write to the memory 18 between the two
`clock domains 56a and 56:‘). Thus, problems that would
`ordinarily arise between the three clock domains (RMCLK,
`XMCLK, BCLK) in the individual memory management
`units 226*, 22!), 22c and 22d are avoided by use of the
`synchronization circuit 60 according to a prescribed arbi-
`tration logic.
`FIG. 3 is a diagram illustrating a data structure of a
`receive data unit in the RX__SRAM 18:1. Asimilar structure
`also may be used for storing data in the TX_ SRAM 18b. As
`shown in FIG. 3, each stored data frame 64 includes a frame
`track field 66 preceding a group of data bytes representing
`the frame data 68 (i.e., the packet data to be transmitted by
`the MAC 20), followed by a control held 70. In this case, the
`RM_MMU 22d stores frame track information 66 and the
`control field 70 related to the receive data frame 68. The
`frame track lield 66 is used by the RB_MMU 22c to keep
`track of the location of the corresponding receive data frame
`68 in the RX_SRAM 18:1. Hence,
`the frame track 66
`enables the RB MMU 22c to quickly flush a stored data
`frame 64 having receive data 68 and jump to the beginning
`of the next stored data frame (cg, 642}, based on an end of
`frame address field (l‘.Nl~‘ ADDR), a count (CN'l'} field
`specifying the number ofDW()RDS(D(), D1,. .
`.
`, DLAST),
`and an end of frame {l’RM) bit indicating whether the data
`frame 64 contains valid data ready for reading. The byte
`enable-last Iield (BE_I.} specifies how many of the bytes in
`the DLAST field are valid.
`
`FIG. 5A is a diagram illustrating multiple data frames (F 1,
`F2, etc.) stored in the RX __SRAM 18:1. Assume that the
`RM MMU 22d is writing a sequence of data frames 64
`(frame 1, frame 2, etc.) into RX__SRAM 180 using a write
`pointer (WP), while the read controller 22c is reading out the
`data frames from the RX_SRAM 180 to the BIU 16 using
`a read pointer (RP).
`II’ the read controller discards (e.g.,
`flushes) a transmit data frame and desires to jump to the
`beginning of the next data frame, the synchronization circuit
`60 must be able to track the start and beginning of each data
`frame to ensure that the read controller 22c properly locates
`the beginning of the next data frame.
`FIG. 4 is a block diagram illustrating in detail the MMU
`22. The synchronization circuit 60 includes asynchronous
`monitors 820 and 82b for asynchronously monitoring the
`amount of stored receive data and transmit data in the
`
`FIG. 2 is a block diagram illustrating the buffer architec-
`ture of the network interface device 10 according to an
`embodiment of the present invention. As shown in FIG. 2,
`transfer of data frames between the PCI bus interface unit
`16, also referred to as the bus interface unit (BIU), and the
`MAC 20 is controlled by a memory management unit
`(MMU) 52 including the buffer management unit 24 and the
`SRAM MMU 22 of FIG. 1. The MMU 52 controls the
`reading and writing of data to the SRAM 18, illustrated in
`FIG. 2 as a dual-port receive SRAM portion lfln and a
`dual-port transmit SRAM portion 18b for convenience. It
`will be recognized in the art that the receive SRAM {RX_
`SRAM) 18a and the transmit SRAM ('I‘X_SRAM} 18!) may
`be implemented as a single memory device, or alternatively
`as two separate SRAM devices.
`As shown in FIG. 2,
`the memory management unit
`includes the buffer management unit 24, also referred to as
`the descriptor management unit, the SRAM MMU 22, and
`an arbitration unit 54. The descriptor management unit 24 is
`configured for fetching,
`from host computer memory,
`descriptor information (i.e., transfer information) specifying
`host computer memory locations for retrieving and storing
`transmit data and receive data, respectively. The arbitration
`unit 54 arbitratcs DMA requests for data transmission, data
`reception, descriptor lists from the descriptor management
`block 24, and status.
`']he SRAM MMU 22 includes separate controllers (i.e.,
`management blocks) for each SRAM 18a and 18b, for both
`read and write operations. According to the disclosed
`embodiment, the network interface device 10 operates in
`two generic clock domains, namely a host computer bus
`clock domain 56rr, and a network clock domain 56!). Since
`the network interface device 10 needs to send and receive
`data across two independent clock domains 56, divided by
`the dotted line 58, the SRAM MMU