`
`
`Paper:
`Entered:
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`HTC CORPORATION, HTC AMERICA, INC., AND APPLE INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC
`Patent Owner
`
`_____________________
`
`
`Case IPR2016-011351
`Patent No. 5,812,789
`
`_____________________
`
`
`PETITIONER’S REPLY
`
`
`
`
`1 Case IPR2017-00512 has been joined with this proceeding.
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`
`
`
`
`
`
`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`TABLE OF CONTENTS
`
`I.
`
`II.
`
`Introduction ...................................................................................................... 1
`
`The combination of Bowes, TMS, and Thomas renders claims
`1-5 and 12-14 obvious. .................................................................................... 2
`
`A.
`
`The combination of Bowes, TMS, and Thomas teaches
`“the bus having a sufficient bandwidth to enable the
`decoder to access the memory and operate in real time
`when the first device simultaneously accesses the bus.” ...................... 2
`
`1.
`
`2.
`
`The Petition sets forth that the combination of
`Bowes and Thomas renders obvious “the bus
`having a sufficient bandwidth to enable the
`decoder to access the memory and operate in real
`time when the first device simultaneously accesses
`the bus.” ...................................................................................... 3
`
`Patent Owner’s argument that a POSITA would
`not combine Bowes and Thomas is incorrect
`because it relies on partial teachings of Thomas
`and ignores other relevant teachings. .......................................... 5
`
`III. The combination of Bowes, Thomas, TMS, and Gove renders
`claims 6 and 8 obvious. .................................................................................10
`
`IV. The combination of Bowes, Thomas, TMS, and Ran renders
`claim 7 obvious. .............................................................................................10
`
`V.
`
`The combination of Bowes, Thomas, TMS, and Celi renders
`claim 11 obvious. ...........................................................................................11
`
`VI. Conclusion .....................................................................................................12
`
`VII. Certificate of Word Count .............................................................................13
`
`
`
`
`
`i
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`
`
`
`June 9, 2017
`
`U.S. Patent No. 5,812,789
`Prosecution History of U.S. Patent No. 5,812,789
`Declaration of Robert Colwell, Ph.D., Under 37 C.F.R. § 1.68
`Curriculum Vitae of Robert Colwell, Ph.D.
`U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”)
`Texas Instruments, Inc., Houston, TX, “TMS320C8x System Level
`Synopsis,” (September 1995) (Literature Ref. SPRU113) (“TMS”)
`U.S. Patent No. 5, 001,625 to Thomas et al. (“Thomas”)
`R. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip”, IEEE 1994 (“Gove”)
`U.S. Patent No. 5,768,533 to Ran (“Ran”)
`U.S. Patent No. 5,742,797 to Celi et al. (“Celi”)
`Joint Claim Construction and Prehearing Statement, Parthenon
`Unified Memory Architecture LLC v. Apple Inc., case no. 2:15-cv-
`632-JRG-RSP (Feb. 16, 2016, E.D. Tex.)
`Decision of Institution of Inter Partes Review, Samsung Elec. Co.,
`Ltd., et al. v. Parthenon Unified Memory Architecture LLC,
`IPR2015-01944 (Paper No. 7)
`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. ZTE Corp. et al., No. 2:15-
`CV-00225 (E.D. Tex.)
`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd. et al.,
`No. 2:14-CV-00902 (E.D. Tex.)
`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. HTC Corp. et al., 2:14-CV-
`00690 (E.D. Tex.)
`
`ii
`
`
`
`
`
`Ex. 1001
`Ex. 1002
`Ex. 1003
`Ex. 1004
`Ex. 1005
`Ex. 1006
`
`Ex. 1007
`Ex. 1008
`
`Ex. 1009
`Ex. 1010
`Ex. 1011
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`Ex. 1012
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`Ex. 1013
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`Ex. 1014
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`Ex. 1015
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`
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`Ex. 1016
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`Ex. 1017
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`Ex. 1018
`
`Ex. 1019
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`Ex. 1020
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`Ex. 1021
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`Ex. 1022
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`Claim Construction Memorandum Opinion and Order, ST
`Microelectronics, Inc. v. Motorola, Inc. et al., No. 4:03-CV-00276
`(E.D. Tex.)
`“Pentium and Pentium Pro Processors and Related Products,” ISBN
`1-55512-265-5
`Parthenon Unified Memory Architecture LLC v. Apple Inc., case no.
`2:15-cv-632-JRG-RSP, Document No. 10 (June 16, 2015, E.D.
`Tex.)
`Texas Instruments, Inc., Houston, TX, “TMS320C80 to
`TMS320C82 Software Compatibility, User’s Guide,” (November
`1995) (Literature Ref. SPRU154)
`Bader Declaration (including Appendix A)
`
`Declaration of Yakov Zolotorev in Support of Motion for Pro Hac
`Vice Admission
`Deposition Transcript of Dr. Mitchell A. Thornton
`
`
`
`iii
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`
`
`
`
`
`Introduction
`
`I.
`
`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`The Petition and the record as a whole provides detailed reasons why a
`
`person of skill in the art (“POSITA”) would have understood the combination of
`
`Bowes, TMS, and Thomas (in addition to other cited art) to render obvious each
`
`and every limitation of the challenged claims of the ’789 patent.
`
`Patent Owner does not dispute the teachings of Bowes, TMS, Thomas or the
`
`other cited references as applied to the claims. Instead, Patent Owner only argues
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`that a POSITA would not combine Bowes and Thomas because such a
`
`combination would reduce the bus bandwidth for the DSP below the bandwidth
`
`necessary to operate in real time. As shown below, this argument fails because it
`
`ignores the entirety of Thomas, as well as the teachings of Bowes and TMS, in
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`that, as Patent Owner’s expert effectively admits, Thomas discloses a bus with
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`more than twice the bandwidth necessary to support real time operations in Bowes.
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`As discussed in more detail below, Thomas teaches using two processing
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`units, each using half the bus, where the bus is at least twice the size of the
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`memory bus that is needed for real time operation in Bowes. Accordingly, Patent
`
`Owner’s argument fails because it ignores the fact that the bus teachings from
`
`Thomas, when combined with Bowes’s system, would provide more than
`
`sufficient bandwidth for the DSP to operate in real time even when sharing the bus
`
`with another device.
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`
`
`1
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`For the reasons shown in the Petition and below, the combination of Bowes,
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`
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`
`
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`TMS, and Thomas renders obvious claims 1-5 and 12-14, claims 6 and 8 (in
`
`combination with Gove), claim 7 (in combination with Ran), and claim 11 (in
`
`combination with Celi). Accordingly, these claims of the ’789 patent should be
`
`deemed unpatentable.
`
`II. The combination of Bowes, TMS, and Thomas renders claims 1-5 and
`12-14 obvious.
`
`Patent Owner argues that the combination of Bowes, TMS, and Thomas
`
`does not render claims 1-5 and 12-14 obvious. Patent Owner focuses its arguments
`
`solely on whether the combination teaches “the bus having a sufficient bandwidth
`
`to enable the decoder to access the memory and operate in real time when the first
`
`device simultaneously accesses the bus” recited in claim 1. Contrary to Patent
`
`Owner’s arguments, the combination renders this limitation obvious.
`
`A. The combination of Bowes, TMS, and Thomas teaches “the bus
`having a sufficient bandwidth to enable the decoder to access the
`memory and operate in real time when the first device
`simultaneously accesses the bus.”
`
`According to Patent Owner, the combination of Bowes, TMS, and Thomas
`
`fails to render the above referenced limitation obvious. See Response, Paper No.
`
`25, at 5. Patent Owner’s only argument is that “[a] POSA would not be motivated
`
`to combine Bowes with Thomas” because “[t]he DSP of Bowes requires an
`
`extraordinarily large amount of bus bandwidth” and combining Bowes with
`
`
`
`2
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`Thomas “would not support the DSP’s real-time operations” because “the DSP in a
`
`
`
`
`
`
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`combined Bowes/Thomas system will be limited to half the bandwidth that it
`
`would otherwise have in its original Bowes system.” Id. at 8. As disclosed in the
`
`references and as admitted by PUMA’s expert, however, the bus in the combined
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`Bowes/Thomas system would have more than twice the bandwidth required for
`
`real time operations.
`
`1.
`
`The Petition sets forth that the combination of Bowes and
`Thomas renders obvious “the bus having a sufficient
`bandwidth to enable the decoder to access the memory and
`operate in real time when the first device simultaneously
`accesses the bus.”
`
`As set forth in the Petition, the combination of Bowes, TMS, and Thomas
`
`teaches a bus with “sufficient bandwidth” to enable a decoder, such as a DSP, “to
`
`access the memory and operate in real time” when a first device, such as a CPU,
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`“simultaneously accesses the bus.” See Petition, Paper No. 2, at 42-44. In
`
`particular, Bowes teaches a computer system with a memory bus that is “optimized
`
`to meet” the needs of a DSP to “support its real-time operations.” Ex. 1005
`
`(Bowes) at 8:40-42; see also 7:26-30. In Bowes, the DSP may be an off-the-shelf
`
`DSP such as the single chip DSP system taught in TMS. Ex. 1003 (Colwell Decl.)
`
`at p.54-55.
`
`To the extent Bowes does not explicitly teach a memory bus that allows its
`
`DSP to access memory and operate in real time when a first device such as a CPU
`
`
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`3
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`simultaneously accesses the bus, a POSITA would have looked to existing known
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`
`
`
`
`
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`system/memory bus teachings for use in such a system, such as those in Thomas.
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`Id. Specifically, Thomas expands on Bowes by teaching “an improved system bus
`
`structure” that supports “high speed, high reliability, parallel processing of bi-
`
`directional signal transfers” in a multiprocessor environment. Ex. 1007 (Thomas),
`
`Abstract. In Thomas, one system unit (e.g., a DSP) may request a “memory read
`
`transfer” from the “main memory unit” and duly indicate “that only the half bus
`
`[is] needed to perform a memory read transfer.” Id. at 15:45-57. “[A]t the same
`
`time,” another system unit (e.g., a CPU) may be attempting to have the same “main
`
`memory unit” perform a “data return” by the other half of the system bus “to
`
`perform a simultaneous data return.” Id. at 15:57-16:2. In other words, Thomas
`
`teaches “a duplex functioning of the system bus by allowing memory read transfers
`
`and data returns to take place on the same bus cycle” from two different processing
`
`units. Id. at 16:2-4.
`
`Accordingly, a POSITA “would have been motivated to combine Bowes’
`
`teachings regarding a computer system with a generic memory bus with Thomas’
`
`teachings regarding an exemplary system bus.” See Petition at 32; Ex. 1003
`
`(Colwell Decl.) ¶ 94. Such a combination “is advantageous to support Bowes’
`
`stated desire to support ‘real-time applications’ including the decoding performed
`
`by TMS’ single chip DSP system sharing the main memory of Bowes.” Petition at
`
`
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`4
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`32; Ex. 1003 (Colwell Decl.) ¶ 94. Indeed, “Thomas’ objective of supporting high
`
`
`
`
`
`
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`speed operations would have further motivated a person having ordinary skill in
`
`the art to select teachings from Thomas’ bus implementation to support the real
`
`time objectives of Bowes.” Ex. 1003 ¶ 87.
`
`Thus, Bowes’s computer system modified with the bus architecture
`
`described in Thomas provides a memory bus with sufficient bandwidth for the
`
`DSP to operate in real time while another device such as a CPU simultaneously
`
`accesses the bus. See Ex. 1003 (Colwell Decl.) at p.54-56.
`
`2.
`
`Patent Owner’s argument that a POSITA would not
`combine Bowes and Thomas is incorrect because it relies on
`partial teachings of Thomas and ignores other relevant
`teachings.
`
`Patent Owner’s argument that a POSITA would not seek to combine
`
`Thomas’s bus architecture with Bowes’s system—because Thomas’s halved bus
`
`would not support Bowes’s DSP—is incorrect. Patent Owner’s argument is based
`
`on the false premise that “the DSP in a combined Bowes/Thomas system will be
`
`limited to half the bandwidth than it would otherwise have in the original Bowes
`
`system.” Response at 8. From this, Patent Owner wrongly concludes that a “POSA
`
`would not be motivated to reduce Bowes DSP’s available bus bandwidth by 50%
`
`(or more).” Id. at 10. As shown below, though, the bus disclosed in Thomas has
`
`more than twice the bandwidth needed for a DSP to operate in real time.
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`
`
`5
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`Patent Owner’s argument fails because it relies on a single teaching of
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`
`
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`
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`Thomas and ignores other relevant disclosures. Patent Owner’s argument focuses
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`exclusively on whether Thomas’s teachings related to splitting the system bus
`
`between two processing units would work with Bowes’s bus. But the combination
`
`set forth in the Petition and Dr. Colwell’s declaration establishes that a POSITA
`
`would combine the teachings of Thomas’s system bus in its entirety, not just the
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`splitting aspect that Patent Owner relies on. See Petition at 32; Ex. 1003 (Colwell
`
`Decl.) ¶ 94 (a POSITA would have been motivated to combine the “known system
`
`bus architecture teachings from Thomas with the Bowes’ known computer system
`
`for the memory bus”). This is an important distinction because Thomas’s bus
`
`architecture not only provides for splitting between two processing units but also
`
`offers twice the bus width of the memory bus in Bowes.
`
`Patent Owner does not dispute Thomas’s teaching of a bus architecture that
`
`can “perform a full bus transfer or a half bus transfer,” see Ex. 1007 (Thomas) at
`
`15:43-44 (cited by Patent Owner at Response at 8). But in seizing upon only that
`
`part of the disclosure to support its flawed conclusion, Patent Owner ignores the
`
`fact that Thomas also teaches “[a]n improved system bus structure for versatile use
`
`in various digital computer architecture configurations” that is “designed to
`
`support high speed, high reliability, parallel processing of bi-directional signal
`
`transfers in a multiport and multiple central processor unit (CPU) communication
`
`
`
`6
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
`
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`environment as between system bus units or devices.” Ex. 1007 (Thomas),
`
`
`
`
`
`
`
`Abstract (emphasis added). To accomplish that end, Thomas’s bus structure
`
`provides more than sufficient capacity for high speed or real time operations.
`
`Specifically, Thomas’s bus structure includes “seventy-two lines of the main data
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`bus” and “seventy-two lines of the expanded data bus” that can “facilitate the
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`transfer of standard 64-bit or expanded 128-bit data transfers.” Id. at 6:54-58. This
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`structure “provides sufficient versatility to specify data transfers by byte, halfword,
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`doubleword, and quadword lengths.” Id. at 13:20-22.
`
`While Bowes is silent on the size of its memory bus, Patent Owner’s expert,
`
`Dr. Thornton, agrees that “[i]t could be any number” but that a 32 bit bus width
`
`“would be the most logical choice.” See Ex. 1022 at 81:8-11; 84:7-22. With such a
`
`configuration, Bowes allows the DSP to operate in real time. See Ex. 1005 at 6:32-
`
`37; 8:40-42; see also Ex. 1003 at p.54-55. It is apparent, then, that the bus in
`
`Thomas—which facilitates 64-bit and 128-bit transfers—would provide at least
`
`twice the bus bandwidth when combined with Bowes (which facilitates at least 32-
`
`bit transfers). Consequently, the combination of Bowes and Thomas provides more
`
`than enough bus width (64 or 128 versus 32) for a DSP (including the DSP in
`
`TMS) to operate in real time, even when operating in Thomas’s half transfer mode.
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`Moreover, the teachings of TMS when combined with Bowes and Thomas
`
`would operate in real time with the TMS chip even when the bus is in half transfer
`
`
`
`7
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`mode. This is because the TMS specification states that the TMS320C8x DSP
`
`
`
`
`
`
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`(TMS chip) includes “[a] 64-bit transfer controller capable of up to 400 MB/s in
`
`on-chip and off-chip memory transfers.” Ex. 1006 at 13. The TMS chip is also
`
`capable of “[d]ynamic sizing of bus width for 64, 32, 16, or 8 bits.” Id. Based on
`
`this, Dr. Thornton agrees that the TMS chip is capable of operating at 400 MB/s on
`
`a 64-bit bus and 200 MB/s on a 32-bit bus. See Ex. 1022 at 83:6-19 (“Q. At 64 bits
`
`it would operate at the maximum, 400 megabytes per second. Is that right? A. It
`
`could. It's capable of that, yeah. Q. But if it's using 32, that would only be capable
`
`of . . . 200 megabytes per second? A. Roughly, depending on any overhead.”). As a
`
`result, even when the TMS chip is operating at half of its maximum bus width, it
`
`would still be capable of operating at speeds that the ’789 patent describes as being
`
`sufficient for real time data transfers. Ex. 1001 at 8:57-63 (“the fast bus 70 . . . is
`
`capable of having a bandwidth of approximately 400 Mbytes/s. This bandwidth is
`
`at least twice the bandwidth required for an optimized decoder/encoder 45,
`
`allowing the decoder/encoder 45 to operate in real time.”).
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`Accordingly, the combination of Bowes, TMS, and Thomas literally teaches
`
`the exact opposite of what Patent Owner argues because the combination teaches a
`
`bus (e.g., Thomas’s 64-bit or 128-bit bus) with sufficient bandwidth to allow the
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`TMS chip to operate in real time using half of the bus (e.g., with as few as a 32 bit
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`width) while another device, such as a CPU, uses the other half of the bus. Patent
`
`
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`8
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
`
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`Owner’s argument that a POSITA would not combine Bowes and Thomas because
`
`
`
`
`
`
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`the bus would not be able to operate in real time when in half transfer mode
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`therefore fails because, as discussed, it ignores all of the relevant teachings from
`
`Bowes, Thomas, and TMS.
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`Moreover, Patent Owner’s argument fails because it is based on improperly
`
`incorporating the teachings of Thomas’s bus splitting into Bowes’s memory bus.
`
`See In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012) (“It is well-established
`
`that a determination of obviousness based on teachings from multiple references
`
`does not require an actual, physical substitution of elements.”). The Federal Circuit
`
`has previously struck down similar types of arguments. Id. citing In re Keller, 642
`
`F.2d 413, 425 (CCPA 1981) (“The test for obviousness is not whether the features
`
`of a secondary reference may be bodily incorporated into the structure of the
`
`primary reference . . . . Rather, the test is what the combined teachings of the
`
`references would have suggested to those of ordinary skill in the art.”); In re
`
`Sneed, 710 F.2d 1544, 1550 (Fed.Cir.1983) (“[I]t is not necessary that the
`
`inventions of the references be physically combinable to render obvious the
`
`invention under review.”); In re Etter, 756 F.2d 852, 859 (Fed.Cir.1985) (en banc)
`
`(“Etter’s assertions that Azure cannot be incorporated in Ambrosio are basically
`
`irrelevant, the criterion being not whether the references could be physically
`
`combined but whether the claimed inventions are rendered obvious by the
`
`
`
`9
`
`
`
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`teachings of the prior art as a whole.”).
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`Patent Owner’s argument that seeks to bodily incorporate the simultaneously
`
`halving aspect of Thomas is improper. The proper test is what would the
`
`combination of Bowes, TMS, and Thomas have suggested to a POSITA. In this
`
`instance, the combination teaches a bus (e.g., Thomas’s 64-bit or 128-bit bus) with
`
`sufficient bandwidth to allow the TMS chip to operate in real time using half of the
`
`bus (e.g., with as few as a 32 bit width) while another device, such as a CPU, uses
`
`the other half of the bus. Thus, Patent Owner’s argument is not only factually
`
`incorrect but relies on an improper application of the standard set forth by the
`
`Federal Circuit.
`
`III. The combination of Bowes, Thomas, TMS, and Gove renders claims 6
`and 8 obvious.
`
`Patent Owner argues that claims 6 and 8 are not rendered obvious by the
`
`combination of Bowes, Thomas, TMS, and Gove only because they depend from
`
`claim 1 and claim 1 is allegedly not obvious as discussed above. See Response at
`
`11. Since the combination of Bowes, Thomas, and TMS does in fact render claim 1
`
`obvious, as discussed above and as set forth in the Petition, the combination of
`
`Bowes, Thomas, TMS, and Gove renders claims 6 and 8 obvious.
`
`IV. The combination of Bowes, Thomas, TMS, and Ran renders claim 7
`obvious.
`
`Patent Owner argues that claim 7 is not rendered obvious by the
`
`
`
`10
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
`
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`combination of Bowes, Thomas, TMS, and Ran only because it depends from
`
`
`
`
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`
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`claim 1 and claim 1 is allegedly not obvious as discussed above. See Response at
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`11-12. Since the combination of Bowes, Thomas, and TMS does in fact render
`
`claim 1 obvious, as discussed above and as set forth in the Petition, the
`
`combination of Bowes, Thomas, TMS, and Ran renders claim 7 obvious.
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`V. The combination of Bowes, Thomas, TMS, and Celi renders claim 11
`obvious.
`
`Patent Owner argues that claim 11 is not rendered obvious by the
`
`combination of Bowes, Thomas, TMS, and Celi only because it depends from
`
`claim 1 and claim 1 is allegedly not obvious as discussed above. See Response at
`
`12. Since the combination of Bowes, Thomas, and TMS does in fact render claim 1
`
`obvious, as discussed above and as set forth in the Petition, the combination of
`
`Bowes, Thomas, TMS, and Celi renders claim 11 obvious.
`
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`11
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`VI. Conclusion
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`
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`None of PUMA’s arguments withstand scrutiny. For the reasons stated
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`above and the evidence as a whole, the Board should find the challenged claims
`
`unpatentable.
`
`Dated: June 9, 2017
`
`
`Respectfully submitted,
`
`
`
`
`
`/Andrew S. Ehmke/
`Andrew S. Ehmke
`Lead Counsel for Petitioner Apple, Inc.
`Registration No. 50,271
`
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 4000
`Dallas, Texas 75219
`Telephone: 214-651-5116
`Facsimile: 214-200-0853
`
`
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`12
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`VII. Certificate of Word Count
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`
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`Pursuant to 37 C.F.R. § 42.24, the undersigned attorney for the Petitioner,
`
`Apple Inc., declares that the argument section of this Petition (Sections I-VI) has a
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`total of 2669 words, according to the word count tool in Microsoft Word™.
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`
`
`
`
`/Andrew S. Ehmke/
`Andrew S. Ehmke
`Lead Counsel for Petitioner Apple, Inc.
`Registration No. 50,271
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`
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`13
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`Petitioner’s Reply
`IPR2016-01135 (Patent No. 5,812,789)
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. §§ 42.6(e) and 42.105(a), this is to certify that service
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`was made on Patent Owner as detailed below:
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`Date of service June 9, 2017
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`Manner of service Electronic Mail to: manjom@azalaw.com;
`aalavi@azalaw.com; sclark@azalaw.com;
`mmcbride@azalaw.com; jchen@azalaw.com;
`gonsalves@gonsalveslawfirm.com
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`Documents served PETITIONER’S REPLY;
`Petitioner’s Updated Exhibit List; and Exhibit 1022
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`Masood Anjom
`Amir Alavi
`Scott Clark
`Michael McBride
`Justin Chen
`Gregory J. Gonsalves
`AHMAD, ZAVITSANOS, ANAIPAKOS, ALAVI &
`MENSING P.C.
`1221 McKinney, Suite 2500
`Houston, TX 77010
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`Persons served
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`/Andrew S. Ehmke/
`Andrew S. Ehmke
`Lead Counsel for Petitioner Apple, Inc.
`Registration No. 50,271
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`14
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