IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONER
`
`v.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR2016-01135
`Patent 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
`
`
`
`
`
`
`
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONER
`
`v.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR2016-01135
`Patent 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
`
`
`
`
`
`
`
`
`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`TABLE OF CONTENTS
`
`I. INTRODUCTION .................................................................................................... 1
`II. STATE OF THE PRIOR ART & THE `789 PATENT ............................................. 2
`III. THE CHALLENGED CLAIMS ARE PATENTABLE ............................................... 5
`A. Bowes, TMS, and Thomas [claims 1–5 and 12–14] ..................................... 5
`1. TMS does not disclose or render obvious “the bus having a sufficient
`bandwidth to enable the decoder to access the memory and operate in real
`time when the first device simultaneously accesses the bus.” ........................... 6
`2. Bowes does not disclose “the bus having a sufficient bandwidth to enable
`the decoder to access the memory and operate in real time when the first
`device simultaneously accesses the bus.” ............................................................ 6
`3. Bowes in combination with Thomas does not render obvious “the bus
`having a sufficient bandwidth to enable the decoder to access the memory
`and operate in real time when the first device simultaneously accesses the
`bus.” ........................................................................................................................ 6
`B. Bowes, TMS, Thomas, and Gove [claims 6 and 8] .................................... 11
`C. Bowes, TMS, Thomas, and Ran [claim 7] .................................................. 12
`D. Bowes, TMS, Thomas, and Celi [claim 11] ................................................ 12
`IV. CONCLUSION .................................................................................................. 13
`
`
`
`
`
`ii
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`TABLE OF AUTHORITIES
`
`
`Cases
`In re Fine,
` 837 F.2d 1071 (Fed.Cir.1988) ................................................................. 11, 12, 13
`
`In re Wilson,
` 424 F.2d 1382 (CCPA 1970) .................................................................................. 5
`
`
`
`Rules
`
`35 U.S.C. § 103 .......................................................................................................... 1
`
`iii
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`
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`TABLE OF EXHIBITS
`
`Exhibit Description
`
`U.S. Patent No. 5,812,789 (“`789 Patent”)1
`U.S. Patent No. 5,546,547 (“Bowes”)
`U.S. Patent No. 5, 001,625 (“Thomas”)
`Declaration of Mitchell A. Thornton (Thornton Decl.”)
`Deposition testimony of Robert Colwell, Ph.D dated February 27,
`2017 (“Colwell Depo.”).
`
`
`
`Exhibit
`No.
`
`1001
`1005
`1007
`2011
`2012
`
`
`1 Ex. 1001, 1005, and 1007 are already of record and not attached to this Response.
`
`iv
`
`
`
`I.
`
`INTRODUCTION
`
`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) hereby submits the following response to the Petition for Inter Partes
`
`review (“Petition”) filed by Apple, Inc. (“Petitioner”) regarding certain claims of
`
`U.S. Patent No. 5,812,789 (“`789 Patent”) filed on June 2, 2016 and Decision
`
`Granting Institution of Inter Partes Review 37 C.F.R. 42.108 issued on December
`
`6, 2016 (“Institution Decision”).
`
`The Board instituted an Inter Partes review with respect to the following
`
`proposed grounds (collectively “Instituted Grounds”):
`
`1. Obviousness of claims 1–5 and 12–14 under 35 U.S.C. § 103 over
`
`Bowes, TMS, and Thomas;
`
`2. Obviousness of claims 6 and 8 under 35 U.S.C. § 103 over Bowes, TMS,
`
`Thomas, and Gove;
`
`3. Obviousness of claim 7 under 35 U.S.C. § 103 over Bowes, TMS,
`
`Thomas, and Ran; and
`
`4. Obviousness of claim 11 under 35 U.S.C. § 103 over Bowes, TMS,
`
`Thomas, and Celi.
`
`For the reasons discussed below, Bowes, TMS, and Thomas do not render
`
`claim 1 obvious. Because they depend on claim 1, claims 2–8 and 11–14 are
`
`1
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`allowable for at least the same reasons. The discussion below first discusses the
`
``789 Patent and claims. It then rebuts the adopted grounds of unpatentability on
`
`the merits.
`
`II. STATE OF THE PRIOR ART & THE `789 PATENT
`
`The computer memory storage requirements of a digital representation of an
`
`uncompressed image is dependent on its resolution, color depth, and size in pixels.
`
`Video files are comprised of sequences of images that are further enhanced with a
`
`corresponding audio track to accompany them. [Ex. 2011, Thornton Decl. at ¶ 29].
`
`As a result, a video file quickly becomes large in size. The transmission of
`
`uncompressed video files is prohibitively expensive. Id.
`
`Accordingly, video files are typically compressed at a transmitting device.
`
`[Ex. 2011, Thornton Decl. at ¶ 30]. The compressed file is then transmitted to a
`
`receiving device where it is decompressed. Id. To that end, an encoder at the
`
`transmitter compresses the video file and a decoder decompresses the file received
`
`at the receiver in order to retrieve a facsimile of the original video and audio data.
`
`Id. In order to ensure compatibility between devices, a number of standards for
`
`encoding and decoding video files were developed. Id. One of those standards was
`
`developed by the Motion Picture Experts Group (“MPEG”) and has been adopted
`
`as a standard for the communication of video. Id.
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`2
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`If a decoder does not operate in real time, the decoded video being displayed
`
`would stop periodically between images until the decoder can access the memory
`
`and process the subsequent image frame. [Ex. 2011, Thornton Decl. at ¶ 31].
`
`Moreover, when using a temporal (intercompression) technique such as the MPEG
`
`Standard, some of the images are decoded based on previous images and some
`
`based on previous and subsequent images. Id. Accordingly, dropping an image on
`
`which the decoding of other images depends is unacceptable as it can result in poor
`
`or unrecognizable decoded images. Id. Therefore, it is typically the case that a
`
`decoder requires its own dedicated memory. Id. For instance, traditional MPEG
`
`decoders require a 2 Mbyte dedicated memory that is utilized during the decoding
`
`process. Id. This dedicated memory is necessary to allow the decoder to decode
`
`images in real-time without dropping frames that would result in a deterioration of
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`the video quality at the receiver. Id.
`
`It is generally desirable to reduce the die area of an integrated circuit device
`
`for a given functionality. [Ex. 2011, Thornton Decl. at ¶ 32]. Such a reduction
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`allows for an increase in the number of the die that can be manufactured on a
`
`silicon wafer having a given size. Id. For example, a video decoder die would be
`
`reduced in size if it did not include a dedicated memory circuit. Id. Moreover, such
`
`a dedicated memory of a decoder may remain unused when an image is not being
`
`3
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`decoded which is inefficient. Id. Accordingly, it is desirable to permit the decoder
`
`to share the main memory of the system with other system components. Id.
`
`To that end, the `789 Patent is generally directed to sharing both a memory
`
`interface and a memory between a video and/or audio decoder and another device
`
`contained in an electronic system. [`789 Pat. [Ex. 1001], Abstract; 4:12-22; 4:30-
`
`34; 4:40-48; independent claim 1]. Accordingly, the electronic system includes a
`
`first device that requires access to the memory and a decoder that requires access
`
`to the memory sufficient to maintain real time operation. Id. at claim 1. A memory
`
`interface is coupled to the memory, the first device and the decoder. Id. The
`
`memory interface includes an arbiter for selectively providing access for the first
`
`device and the decoder to the memory. Id. A shared bus is coupled to the memory,
`
`the first device and the decoder. Id. The shared bus has sufficient bandwidth to
`
`enable the decoder to access the memory and operate in real time when the first
`
`device simultaneously accesses the shared bus. Id.
`
`A video decoder only requires access to memory during its operation. [Ex.
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`2011, Thornton Decl. at ¶ 34]. In accordance with the implementation of the `789
`
`Patent, other devices such as a first device may have exclusive access to a shared
`
`memory when the decoder is not operating. Id. In such instances, the first device
`
`can use the entire bandwidth of the fast bus to support memory accesses. Id.
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`4
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`The fast bus (70) of the `789 Patent has a bandwidth that is at least twice the
`
`required bandwidth to support the memory accesses needed to support real time
`
`video decoding. [`789 Pat., 6:67-7:2]. Accordingly, the video decoder will
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`typically be using less than 40% of the bandwidth of the fast bus (70) during
`
`decoding. [`789 Pat., 7:18-20]. This frees up the remaining bandwidth to be used
`
`by other devices such as a first device during the decoder operation. [`789 Pat.,
`
`7:20-22]. Because the decoder does not use the entire available bandwidth of the
`
`fast bus (70) during real time decoding, the remaining bus bandwidth may be used
`
`by other devices such as a first device simultaneously while real time decoding is
`
`occurring. [`789 Pat., 7:5-15].
`
`III. THE CHALLENGED CLAIMS ARE PATENTABLE
`
`
`A. Bowes, TMS, and Thomas [claims 1–5 and 12–14]
`
`Independent claim 1 is not invalid as obvious in view of Bowes, TMS, and
`
`Thomas because Bowes, TMS, and Thomas, alone or in combination, fail to
`
`disclose “the bus having a sufficient bandwidth to enable the decoder to access the
`
`memory and operate in real time when the first device simultaneously accesses the
`
`bus.” See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All words in a
`
`claim must be considered in judging the patentability of that claim against the prior
`
`art”).
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`5
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`1. TMS does not disclose or render obvious “the bus having a
`sufficient bandwidth to enable the decoder to access the
`memory and operate in real time when the first device
`simultaneously accesses the bus.”
`
`Petitioner does not rely on TMS to disclose or render obvious the “when the
`
`first device simultaneously accesses the bus” portion of this limitation. [See
`
`Petition at 42–44.] Indeed, Dr. Thornton confirms that TMS does not disclose or
`
`render obvious this portion of the limitation. [Ex. 2011, Thornton Decl. at ¶ 39.]
`
`Accordingly, TMS does not disclose or render obvious this portion of the
`
`limitation.
`
`2. Bowes does not disclose “the bus having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real
`time when the first device simultaneously accesses the bus.”
`
`It is unclear whether Petitioner argues that Bowes discloses the “when the
`
`first device simultaneously accesses the bus” portion of this limitation. [See
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`Petition at 43.] In any event, Bowes does not disclose this portion of the
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`limitation. [Ex. 2011, Thornton Decl. at ¶ 40.] Bowes never discloses the CPU
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`using the bus at the same time that the DSP is performing real-time decoding.
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`Indeed, Petitioner has not provided any analysis to support a conclusion that
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`Bowes discloses this portion of the limitation. [See Petition at 43.]
`
`3. Bowes in combination with Thomas does not render obvious
`“the bus having a sufficient bandwidth to enable the decoder to
`
`6
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`access the memory and operate in real time when the first
`device simultaneously accesses the bus.”
`
`Petitioner argues that Bowes in combination with Thomas renders the “when
`
`the first device simultaneously accesses the bus” portion of this limitation obvious.
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`[See Petition at 43–44.] This is incorrect. A POSA would not be motivated to
`
`combine Bowes with Thomas for the reasons described below. [Ex. 2011,
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`Thornton Decl. at ¶ 41].
`
`The DSP of Bowes requires an extraordinarily large amount of bus
`
`bandwidth. [See Ex. 2011, Thornton Decl. at ¶ 42; Ex. 1005 at 1:51–53 (“[A] DSP
`
`requires a large amount of bandwidth to memory for processing the sheer volume
`
`of data required to effectuate real-time computing.”); 2:25–26 (“the high
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`bandwidth required for real-time processing by a DSP”); 3:21–23 (“The arbitration
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`scheme is tuned to maximize accessibility of the memory bus to the DSP which
`
`has by far the greatest bandwidth requirements.”); 6:35–38 (“Many of these
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`functions are real-time operation and require a tremendous amount of the memory
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`bus bandwidth between the DSP and the DRAM of the main memory subsystem
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`14.”); 7:31–32 (“In addition to the DSP’s huge requirement for bandwidth on the
`
`memory bus . . . .”)] As a result, the Bowes system is “optimized” to support the
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`DSP and make sure that it has the bus bandwidth it needs to perform real-time
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`operations. [See Ex. 2011, Thornton Decl. at ¶ 42; Ex. 1005 at 8:40–42 (“Because
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`the DSP has the largest bus bandwidth requirement, the system is optimized to
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`meet its need and support its real-time operations.”)]
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`Combining Bowes with Thomas to meet this limitation would not support
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`the DSP’s real-time operations because the combined system would effectively
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`halve the bus bandwidth available to the DSP. [Ex. 2011, Thornton Decl. at ¶ 43].
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`To meet this limitation, the DSP in a combined Bowes/Thomas system must be
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`able to use the bus to operate in real-time while the CPU is using the bus at the
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`same time. [Id.] Given the teachings of Thomas, this means that the DSP and
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`CPU will each be using, at most, only half of the available bus bandwidth. [Id.]
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`For example, Thomas teaches bus units that request “system bus access to perform
`
`a full bus transfer or a half bus transfer.” [Ex. 1007 at 15:43–44.] The
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`“simultaneous data return” described by Thomas occurs only when the cache
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`memory requests a half bus transfer (as opposed to a full bus transfer), which
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`allows the main memory to use the other half of the bus. [See Ex. 2011, Thornton
`
`Decl. at ¶ 43; Ex. 1007 at 15:50–16:2.] Therefore, the DSP in a combined
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`Bowes/Thomas system will be limited to half the bandwidth that it would
`
`otherwise have in the original Bowes system. [Ex. 2011, Thornton Decl. at ¶ 43].
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`8
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`Petitioner’s expert agrees with this analysis of Thomas. For example, Dr.
`
`Colwell agrees that Thomas’ bus can support simultaneous bus transactions only
`
`when both of the transactions are half bus transfers:
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`[Ex. 2012, Colwell Depo. at 17:2–6.] Dr. Colwell further agrees that the bus units
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`in Thomas can use, at most, only half of the peak bus bandwidth when engaged in
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`a simultaneous bus transaction:
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`[Ex. 2012, Colwell Depo. at 15:3–21.]
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`A POSA would not be motivated to reduce the Bowes DSP’s available bus
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`bandwidth by 50% (or more) when the DSP requires a “tremendous” amount of
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`bandwidth, especially when the entire system should be optimized to guarantee
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`that the DSP has sufficient bandwidth. [Ex. 2011, Thornton Decl. at ¶ 45].
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`Combining Bowes with Thomas would not support the DSP’s real-time operations;
`
`it would achieve the exact opposite result. [Id.] Accordingly, a POSA would not
`
`be motivated to combine Bowes with Thomas. [Id.]
`
`At least for these reasons, independent claim 1 is not invalid as obvious in
`
`view of Bowes, TMS, and Thomas. Claims 2–5 and 12–14 depend on independent
`
`claim 1 and are therefore allowable for at least the same reasons. In re Fine, 837
`
`F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103
`
`if the independent claims from which they depend are nonobvious”).
`
`B. Bowes, TMS, Thomas, and Gove [claims 6 and 8]
`
`The Petition alleges that claims 6 and 8 are obvious in view of Bowes, TMS.
`
`Thomas, and Gove. Claims 6 and 8 depend on independent claim 1. As discussed
`
`in Section III.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
`
`and Thomas. The Petition relies on Gove only for its alleged disclosure of certain
`
`limitations in claims 6 and 8. [Petition at 57–59.] Therefore, independent claim 1
`
`is also not obvious in view of the proposed combination of Bowes, TMS, Thomas,
`
`and Gove. Dependent claims 6 and 8 are allowable at least for the same reasons.
`
`In re Fine, 837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are
`
`11
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`nonobvious under § 103 if the independent claims from which they depend are
`
`nonobvious”).
`
`C. Bowes, TMS, Thomas, and Ran [claim 7]
`
`The Petition alleges that claim 7 is obvious in view of Bowes, TMS,
`
`Thomas, and Ran. Claim 7 depends on independent claim 1. As discussed in
`
`Section III.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
`
`and Thomas. The Petition relies on Ran only for its alleged disclosure of certain
`
`limitations in claim 7. [Petition at 59–62.] Therefore, independent claim 1 is also
`
`not obvious in view of the proposed combination of Bowes, TMS. Thomas, and
`
`Ran. Dependent claim 7 is allowable at least for the same reasons. In re Fine, 837
`
`F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103
`
`if the independent claims from which they depend are nonobvious”).
`
`D. Bowes, TMS, Thomas, and Celi [claim 11]
`
`The Petition alleges that claim 7 is obvious in view of Bowes, TMS,
`
`Thomas, and Celi. Claim 11 depends on independent claim 1. As discussed in
`
`Section III.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
`
`and Thomas. The Petition relies on Celi only for its alleged disclosure of certain
`
`limitations in claim 11. [Petition at 62–69.] Therefore, independent claim 1 is also
`
`not obvious in view of the proposed combination of Bowes, TMS. Thomas, and
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`12
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`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`Celi. Dependent claim 11 is allowable at least for the same reasons. In re Fine,
`
`837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under §
`
`103 if the independent claims from which they depend are nonobvious”).
`
`IV. CONCLUSION
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`For the foregoing reasons, the Board should find that each of the claims
`
`under review is patentable.
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`13
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`By: /s/ Masood Anjom
`Masood Anjom, Lead Counsel
`Reg. No. 62,167
`Scott Clark, Back-Up Counsel
`Reg. No. 51,251
`Amir Alavi, Back-Up Counsel
`Michael McBride, Back-Up Counsel
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
`
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
`
`Dated: March 9, 2017
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`CERTIFICATE OF SERVICE
`I hereby certify that the Patent Owner’s Response Under 35 U.S.C. § 316
`
`AND 37 C.F.R. §42.120 was served on this Thursday, March 9, 2017 by electronic
`mail to the following:
`Lead Counsel for Apple Inc.
`David W. O’Brien, Reg. No. 40,107
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`Email: andy.ehmke.ipr@haynesboone.com
`
`IPR2016-01135
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`
`Back-up Counsel for Apple Inc.
`Andrew S. Ehmke, Reg. No. 50,271
`Michael S. Parsons, Reg. No. 58,767
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`david.obrien.ipr@haynesboone.com
`michael.parsons.ipr@haynesboone.com
`
`David L. Alberti, Reg. No. 43,465
`dalberti@feinday.com
`Yakov Zolotorev
`yzolotorev@feinday.com
`FEINBERG DAY ALBERTI &
`THOMPSON LLP
`1600 El Camino Real, Suite 280
`Menlo Park, CA 94025
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`Dated: March 9, 2017
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`By: /s/ Masood Anjom
`
`Masood Anjom, Lead Counsel
`
`Reg. No. 62,167
`
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
`
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
`
`
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`14
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