IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Petition for Inter Partes Review
`
`Attorney Docket No.: 52959.21
`Customer No.:
`27683
`
`Real Party in Interest:
`Apple Inc.
`
`
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`In re patent of Owen et al.
`
`U.S. Patent No. 7,542,045
`
`Issued: Jun 2, 2009
`Title: Electronic System and Method
`For Display Using a Decoder and
`Arbiter To Selectively Allow Access
`to a Shared Memory
`
`
`
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D.
`Under 37 C.F.R. § 1.68
`
`
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`Apple Exhibit 1003
`Page 1 of 87
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`Table of Contents
`Introduction .......................................................................................................... 3 
`I. 
`II.  Qualifications and Professional Experience ........................................................ 4 
`III.  Level of Ordinary Skill in the Art ....................................................................... 7 
`IV. Relevant Legal Standards .................................................................................... 8 
`V.  The ’045 Patent .................................................................................................. 10 
`A.  Overview ..................................................................................................... 10 
`B.  History of the ’045 Patent ........................................................................... 17 
`VI. Claim Construction ............................................................................................ 17 
`VII.  Overview of References .............................................................................. 21 
`A.  Overview of Bowes (U.S. Patent No. 5,546,547) ...................................... 21 
`B.  Overview of DSP3210 Data Sheet ............................................................. 24 
`C.  Overview of Artieri (translation of EP 0626653) ....................................... 27 
`D.  Overview of Gove ...................................................................................... 30 
`VIII.  Challenge #1: Claims 1, 4, 5, 7, 10, 12, 16, and 17 are invalid over
`Bowes as informed by the DSP3210 Data Sheet and in view of Artieri .... 31 
`A.  Bowes’ DSP as a “decoder” or “video decoder” ........................................ 35 
`B.  Use of a shared “main memory” was known ............................................. 45 
`C.  An arbiter circuit (or “memory arbiter” or “arbiter”) ................................. 50 
`D.  Reasons to Combine Bowes, DSP3210 Data Sheet, and Artieri ................ 53 
`E.  Detailed Analysis: Claims 1, 4, 5, 7, 10, 12, 16, and 17 ............................ 55 
`IX. Challenge #2: Claims 9 and 15 are invalid over Bowes in view of DSP3210
`Data Sheet, Artieri, and Gove ..................................................................... 82 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Gove ..... 82 
`B.  Detailed Analysis of Claims 9 and 15 ........................................................ 84 
`X.  Declaration ......................................................................................................... 87 
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`
`I.
`
`Introduction
`
`I, Robert Colwell, Ph.D., declare:
`
`1.
`
`I am making this declaration at the request of Apple Inc. in the matter
`
`of the Inter Partes Review of U.S. Patent No. 7,542,045 (“the ’045 Patent”) to
`
`Owen et al.
`
`2.
`
`I am being compensated for my work in this matter. I am also being
`
`reimbursed for reasonable and customary expenses associated with my work and
`
`testimony in this investigation. My compensation is not contingent on the outcome
`
`of this matter or the specifics of my testimony.
`
`3.
`
`In the preparation of this declaration, I have studied:
`
`(1) The ’045 Patent, Exhibit 1001;
`
`(2) The prosecution history of the ’045 Patent, Exhibit 1002;
`
`(3) U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”), Exhibit 1005;
`
`(4)
`
`“AT&T DSP3210 Digital Signal Processor The Multimedia Solution”
`
`Data Sheet March 1993 (“DSP3210 Data Sheet”), Exhibit 1006;
`
`(5) EP 0626653 to Artieri, English translation (“Artieri”), Exhibit 1007;
`
`(6) R. Gove, “The MVP: A Highly-Integrated Video Compression Chip”,
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`IEEE 1994 (“Gove”), Exhibit 1008;
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`(7)
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`other documentation as cited in the analysis below.
`
`4.
`
`In forming the opinions expressed below, I have considered:
`
`(1) The documents listed above,
`
`(2) The relevant legal standards, including the standard for obviousness
`
`provided in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007), and
`
`(3) My own knowledge and experience, including my work experience in
`
`the fields of electrical engineering, computer engineering, computer
`
`architectures, memory interfacing, and multimedia technologies, and my
`
`experience in working with others involved in those fields, as described
`
`below.
`
`II. Qualifications and Professional Experience
`
`5. My complete qualifications and professional experience are described
`
`in my curriculum vitae, a copy of which can be found in Exhibit 1004. The
`
`following is a brief summary of my relevant qualifications and professional
`
`experience.
`
`6.
`
`I have nearly 40 years of professional experience in the field of
`
`processor and system architecture design. I consider myself an expert in, among
`
`other things, CPU architecture and computer systems.
`
`7.
`
`
`
`I received an undergraduate Bachelor of Science degree in Electrical
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`–4–
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`Engineering from the University of Pittsburgh in 1977. I received a Master’s of
`
`Science degree in Computer Engineering from Carnegie Mellon University in 1978
`
`as well as a Ph.D. in Computer Engineering in 1985.
`
`8.
`
`From 1977 to 1980, I held an engineering position at Bell Telephone
`
`Laboratories where I worked on, among other things, microprocessor hardware
`
`design.
`
`9.
`
`From 1980 to 1984, I held an engineering position at Perq Systems,
`
`where I worked on hardware design in computer environments. From 1985 to
`
`1990, I held an engineering position at Multiflow Computer, where I served as a
`
`hardware architect. While at Multiflow Computer, I assisted in creating the first
`
`very long instruction word (VLIW) scientific supercomputer.
`
`10. From 1990 to 2001, I held various positions at Intel including Senior
`
`CPU Architect and later Chief Architect (for Intel’s IA-32, also known as x86). As
`
`part of my responsibilities at Intel, I co-invented Intel’s P6 microarchitecture that
`
`formed the core of the Pentium II manufactured by Intel (as well as the Pentium
`
`III, Celeron, Xeon, and Centrino families). The P6 core is still very influential
`
`today, in Intel’s top-of-the-line Core i3, i5, and i7 processors. In addition, I led
`
`Intel’s x86 Pentium CPU architecture endeavors. I was honored to be named an
`
`Intel fellow in 1997 in recognition of my contributions to the P6 microarchitecture
`
`development.
`
`
`
`–5–
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`11.
`
`I became a self-employed industry consultant in 2001, working with
`
`computer industry clients such as Safeware, the University of Pittsburgh, Intel,
`
`many venture capital companies, and the U.S. Department of Defense (DoD).
`
`12. From 2011 to 2014, I worked at the Defense Advanced Research
`
`Projects Agency (DARPA) first as Deputy Director, then Director, of the
`
`Microsystems Technology Office (MTO). MTO had an annual budget of
`
`approximately $600M, and my job as office leader was to invest that money in
`
`promising new technologies for the DoD, including new energy-efficient
`
`computing systems, modular and adaptable radars, position/navigation/timing
`
`systems for GPS-denied environments, computer-mediated prosthetics for military
`
`(and civilian) amputees, traumatic brain injury detection devices for soldiers, fused
`
`multiple-band night vision sensors, extremely high power lasers, and much more.
`
`13.
`
`I have been recognized by the industry for my contributions to
`
`processor design. I received the Eckert-Mauchly Award in 2005 for “outstanding
`
`achievements
`
`in
`
`the design and
`
`implementation of
`
`industry-changing
`
`microarchitectures, and for significant contributions to the RISC/CISC architecture
`
`debate.” The Eckert-Mauchly Award is generally viewed as the highest possible
`
`recognition in the field of computer architecture.
`
`14.
`
`I was inducted into the National Academy of Engineering in 2006, the
`
`nation’s highest honorary society for engineering achievement. In 2012 I was
`
`
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`inducted into the American Academy of Arts and Sciences; other inductees in my
`
`“class” that year included Sir Paul McCartney, Hillary Rodham Clinton, and Mel
`
`Brooks.
`
`15.
`
`In 2015 I received the Bob Rau Award from the Institute of Electrical
`
`and Electronics Engineers (IEEE), for “contributions to critical analysis of
`
`microarchitecture and the development of the Pentium Pro processor.”
`
`16.
`
`I have published many conference papers, sections of textbooks, and
`
`articles for magazines. I have also been named an inventor on 40 patents related to
`
`computer hardware and processor design. I have also been an editor for several
`
`IEEE publications.
`
`17. My curriculum vitae (Ex. 1004) includes a list of all publications I
`
`have authored in the last 10 years.
`
`18.
`
`In summary, I have extensive familiarity with multimedia systems,
`
`computer architectures, unified memory architectures, and methods related to
`
`controlling memory access, and am familiar with what the states of these
`
`technologies were at the relevant time of the ’045 Patent invention and before.
`
`III. Level of Ordinary Skill in the Art
`
`19.
`
`I am familiar with the knowledge and capabilities of persons of
`
`ordinary skill in the computer system architecture and multimedia processing arts
`
`
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`in the period around 1996. In addition to my own experiences, I worked with and
`
`spent 11 years leading an industrial microprocessor design team at Intel, which by
`
`the mid-1990s included more than 450 engineers. The majority of those engineers I
`
`personally interviewed as part of the recruiting and hiring process. My experience
`
`working in the industry and interactions with colleagues and supervision of
`
`practicing engineers has allowed me to become directly and personally familiar
`
`with the level of skill of individuals and the general state of the art as of 1996.
`
`20.
`
`I have been informed by counsel that the earliest alleged priority date
`
`for the ’045 Patent is August 26, 1996. Unless otherwise stated, my testimony
`
`below refers to the knowledge of one of ordinary skill in the computer system
`
`architecture and multimedia processing arts in the period around and prior to
`
`August 26, 1996. In my opinion, the level of ordinary skill in the art appropriate to
`
`understanding the scientific and engineering principles applicable to the ’045
`
`Patent is (i) a Bachelor of Science degree (or higher degree) in an academic area
`
`emphasizing electrical or computer engineering and (ii) three years of relevant
`
`industry experience.
`
`IV. Relevant Legal Standards
`
`21.
`
`I have been asked to provide my opinions regarding whether claims 1,
`
`4, 5, 7, 9, 10, 12, and 15-17 of the ’045 Patent would have been obvious to a
`
`person having ordinary skill in the art at the time of the alleged invention, in light
`
`
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`–8–
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`of the prior art. I have been informed by counsel that a claimed invention is
`
`unpatentable under 35 U.S.C. § 103 if the differences between the invention and
`
`the prior art are such that the subject matter as a whole would have been obvious at
`
`the time the invention was made to a person having ordinary skill in the art to
`
`which the subject matter pertains. I have also been informed by counsel that the
`
`obviousness analysis takes into account factual inquiries including the level of
`
`ordinary skill in the art, the scope and content of the prior art, and the differences
`
`between the prior art and the claimed subject matter.
`
`22.
`
`I have been informed by counsel that the Supreme Court has
`
`recognized several rationales for combining references or modifying a reference to
`
`show obviousness of claimed subject matter. Some of these rationales include the
`
`following: (a) combining prior art elements according to known methods to yield
`
`predictable results; (b) simple substitution of one known element for another to
`
`obtain predictable results; (c) use of a known technique to improve a similar device
`
`(method, or product) in the same way; (d) applying a known technique to a known
`
`device (method, or product) ready for improvement to yield predictable results; (e)
`
`choosing from a finite number of identified, predictable solutions, with a
`
`reasonable expectation of success; and (f) some teaching, suggestion, or motivation
`
`in the prior art that would have led one of ordinary skill to modify the prior art
`
`reference or to combine prior art reference teachings to arrive at the claimed
`
`
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`invention.
`
`V. The ’045 Patent
`
`A. Overview
`
`23. The ’045 Patent generally describes an electronic system with a first
`
`device and a “video/audio compression/decompression device such as a
`
`decoder/encoder” to share a memory. (Ex. 1001, Abstract). “An arbiter selectively
`
`provides access for the first device and/or the decoder/encoder to the memory
`
`based on priority.” (Ex. 1001, Abstract).
`
`24.
`
`In order to fit digital media, such as movies, onto a “conventional
`
`recording medium, such as a Compact Disc (CD),” the ’045 Patent recognizes it
`
`was already known to “compress video and audio sequences before they are
`
`transmitted or stored.” (Ex. 1001, 1:44-51). For compression/decompression, “[t]he
`
`MPEG standards are currently well accepted standards
`
`for one way
`
`communication. H.261, and H.263 are currently well accepted standards for video
`
`telephony.” (Ex. 1001, 2:6-9). The ’045 Patent further states that electronic
`
`systems added decoders to systems (such as a computer) in order to “allow them to
`
`display compressed sequences.” (Ex. 1001, 2:14-17).
`
`25. The ’045 Patent continues and explains that a decoder for MPEG
`
`sequences “typically … requires a 2 Mbyte memory,” and that such memory was
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`“dedicated to the MPEG decoder 10 and increases the price of adding a decoder 10
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`to the electronic system.” (Ex. 1001, 2:46-49). The ’045 Patent views this
`
`dedicated memory as a problem that increased the cost of the decoder. (Ex. 1001,
`
`2:49-51). The ’045 Patent allegedly addresses this problem by having the “video
`
`and/or audio decompression and/or compression device share[] a memory interface
`
`and the memory with the first device.” (Ex. 1001, 5:2-3). Figure 2 of the ’045
`
`Patent illustrates an electronic system containing a device (“first device”) having a
`
`shared memory with a decoder:
`
`’045 Patent (Ex. 1001), FIG. 2
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`The ’045 Patent explains that its proposed solution results in cost reduction “due to
`
`the fact that the video and/or audio decompression and/or compression device does
`
`not need its own dedicated memory but can share a memory with another device
`
`and still operate in real time.” (Ex. 1001, 5:48-51).
`
`26. The ’045 Patent further explains that the system, such as the system of
`
`FIG. 2, includes an arbiter, where requests for access to the memory are granted
`
`based on a priority scheme, which “can be any priority scheme that ensures that the
`
`decoder/encoder 80 gets access to the memory 50 often enough and for enough of
`
`a burst length to operate properly, yet not starve the other devices sharing the
`
`memory.” (Ex. 1001, 13:31-36). I note that below, in claim 1, the arbiter performs
`
`the function of “controlling access to said main memory by the video decoder and
`
`the microprocessor” and in claim 5 the function of “control[ling] access to the
`
`system memory.” (See also, claims 4 and 12, where the arbiter analogously
`
`performs the function by “controlling the access to bus.”) As set forth in the ’045
`
`Patent specification, I understand that the arbiter performs this function by
`
`allowing only one of the devices to access the main memory at a given time. Ex.
`
`1001, 13:11-30. The ’045 Patent states that its system includes a “bus 70 [FIG. 2
`
`above], that have a bandwidth greater than the bandwidth required for the
`
`decoder/encoder 80 to operate in real time. … A fast bus 70 is any bus whose
`
`bandwidth is equal to or greater than the required bandwidth.” (Ex. 1001, 7:49-
`
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`8:10). Exemplary buses that, according to the ’045 Patent, provide bandwidth to
`
`be considered “fast” include “a PCI bus,…VESA Local Bus (VLB), an
`
`Accelerated Graphics Port (AGP) bus, or any bus having the required bandwidth.”
`
`(Ex. 1001, 10:19-22, see also Ex. 1001, 5:26-33. PCI bus, VESA Local Bus
`
`(VLB), and Accelerated Graphics Port (AGP) bus were known, available bus
`
`architectures.
`
`27. As an initial matter, I note that the alleged solution presented in the
`
`’045 Patent—sharing a memory between multiple devices and arbitrating access
`
`thereto between the devices—was well known to persons of ordinary skill in the art
`
`before the earliest alleged priority date of the ’045 Patent. For example, others had
`
`previously identified the problem of dedicated “substantial block of static random
`
`access memory … SRAMs are significantly more expensive than DRAM which
`
`greatly increases the cost of computer systems which incorporate SRAM.” (Ex.
`
`1005, 2:36-41). Further, others had identified the same solution to the problem,
`
`namely providing “a mechanism and method for arbitrating the memory bus
`
`bandwidth to efficiently allow the use of a digital signal processor and a CPU over
`
`a common memory bus sharing the system's dynamic random access memory
`
`subsystem without requiring an expensive block static random access memory.”
`
`(Ex. 1005, 2:57-63).
`
`28. Additionally, digital signal processors were known to provide
`
`
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`compression and decompression (e.g., MPEG) processing before the ’045 Patent.
`
`(See, e.g., Ex. 1010, “TMS” (TMS teaches that the single-chip multiprocessor DSP
`
`(“TMS320C8x” p. iii) may be used to accelerate applications “such as video
`
`compression and decompression, image processing, and graphics manipulation.”
`
`(See also Ex. 1010, p. A-6; Ex. 1008, p. 216).
`
`29.
`
`In claim 1 of the ’045 Patent, which is exemplary, a “microprocessor
`
`system” and a “video decoder” both require access to a main memory. (Ex. 1001,
`
`15:35-56). Claim 1 of the ’045 Patent recites:
`
`An electronic system comprising:
`
`a bus coupleable to a main memory having stored therein data
`
`corresponding to video images to be decoded and also decoded data
`
`corresponding to video images that have previously been decoded;
`
`a video decoder coupled to the bus for receiving encoded video
`
`images and for outputting data for displaying the decoded video images on a
`
`display device, the decoder configured to receive data from the main
`
`memory corresponding to at least one previously decoded video image and
`
`to a current video image to be decoded and outputting decoded data
`
`corresponding to a current video image to be displayed, the current video
`
`image to be displayed adapted to be stored in the main memory;
`
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`a microprocessor system configured to be coupled to the main
`
`memory, the microprocessor system for storing non-image data in and
`
`retrieving non-image data from the main memory; and
`
`an arbiter circuit coupled to both the microprocessor system and the
`
`video decoder for controlling the access to said main memory by the video
`
`decoder and the microprocessor.
`
`30. Based on my experience, the electronic system described in the ’045
`
`Patent and claimed in claim 1, as well as those systems of claims 4, 5, 7, 9, 10, 12,
`
`and 15-17, were already well known to persons of ordinary skill in the art before
`
`the earliest alleged priority date. For instance, others had already taught the
`
`usefulness of unified memory architectures with arbitration to access the shared
`
`memory. (See Bowes, Ex. 1005). One of ordinary skill in the art would recognize
`
`that arbitration must be present in any system that shares access to a resource (e.g.,
`
`memory) in order to prevent conflicts. Arbitration schemes that were based on
`
`priority were well known. (See, e.g., Ex. 1005, 3:29-33; Ex. 1013, 1:16-19)
`
`31. Prior to the earliest alleged priority date of the ’045 Patent, others had
`
`also taught the usefulness of video decoder (or a decoder) interacting with a
`
`memory in order to receive encoded data and output decoded data. (Ex. 1007,
`
`Figure 2). In fact, the International Organization for Standardization document
`
`“ISO/IEC 11172-2:1993:Information technology – Coding of moving pictures and
`
`
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`associated audio for digital storage media at up to about 1,5 Mbit/s-Part 2:Video,”
`
`1st ed., August 1, 1993 (“MPEG Standard”), was publically available as of August
`
`1993, years before the earliest alleged priority date of the ’045 Patent. (Ex. 1009.)
`
`The MPEG Standard was a well-accepted industry standard. (See Ex. 1001, 2:6-7).
`
`The compression disclosed in the MPEG Standard allows videos to be encoded to
`
`reduce the bandwidth or memory requirements during storage or transmission; the
`
`compressed images are subsequently decoded for display. (Ex. 1009, at 52 (Figure
`
`D.1)). The MPEG Standard provides for a decoder interacting with a “Picture
`
`store” or a memory. (Ex. 1009, p. viii).
`
`Ex. 1009, MPEG Standard, Figure 4
`
`
`
`32. Accordingly, as I show below, it is my opinion that the elements and
`
`functionality recited in claims 1, 4, 5, 7, 9, 10, 12, and 15-17 of the ’045 Patent
`
`were already well known before the earliest claimed priority date of the ’045
`
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`Patent.
`
`B. History of the ’045 Patent
`
`33. The ’045 Patent issued on June 2, 2009 from U.S. Patent Application
`
`No. 11/956,165 by Jefferson Eugene Owen, Raul Zegers Diaz, and Osvaldo
`
`Colavin. Again, I have been informed by counsel that the earliest alleged priority
`
`date for the ’045 Patent is August 26, 1996.
`
`34.
`
`I have reviewed the prosecution history of the ’045 Patent and it is my
`
`understanding that none of the references cited in this declaration were discussed
`
`by the United States Patent Office during prosecution that led to the ’045 Patent. I
`
`also understand that the Office stated that the prior art did not teach “an arbiter
`
`circuit coupled to both the microprocessor system and the video decoder for
`
`controlling access
`
`to
`
`the main memory by
`
`the video decoder and
`
`the
`
`microprocessor.” (Ex. 1002, p. 251). I disagree that this was not known in the art
`
`as discussed with reference to Bowes below.
`
`VI. Claim Construction
`
`35.
`
`It is my understanding that in order to properly evaluate the ’045
`
`Patent, the terms of the claims must first be interpreted. It is my understanding that
`
`for the purposes of this inter partes review the claims are to be given their broadest
`
`reasonable interpretation in light of the specification. It is my further understanding
`
`
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`that claim terms are given their ordinary and customary meaning as would be
`
`understood by one of ordinary skill in the art, unless the inventor has set forth a
`
`special meaning for a term.
`
`36.
`
`In addition to the broadest reasonable interpretation set forth herein, I
`
`have been informed that the ’045 Patent appears set to expire in August 2016. In
`
`such cases, I have been told that the Board may construe patent claims, once
`
`expired, according to the standard applied in the district courts by applying the
`
`principles set forth in Philips v. AWH Corp., 415 F.3d 1030, 1312 (Fed. Cir. 2005)
`
`(en banc). I am told under Philips principles, the words of the claims are generally
`
`given their ordinary and customary meaning as understood by a person of ordinary
`
`skill in the art in question, at the time of the alleged invention. It is my opinion
`
`that this change of standards would not affect any of the invalidity grounds
`
`discussed herein should construction of the claims remain as provided herein.
`
`37.
`
`In order to construe the following claim terms, I have reviewed the
`
`entirety of the ’045 Patent as well as its prosecution history.
`
`38.
`
`“decoder” and “video decoder”
`
`39. The term “decoder” is found in claim 12, as well as in the detailed
`
`description. The term “video decoder” is used in independent claims 1, 4, and 5 of
`
`the ’045 Patent.
`
`
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`40. The ’045 Patent sets forth a special meaning for “decoder” as follows:
`
`“[t]he resulting bitstream is decoded by a video and/or audio decompression
`
`device (hereinafter decoder) before the video and/or audio sequence is displayed.”
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`(Ex. 1001, 1:65-2:1) (emphasis added). The ’045 Patent continues in the detailed
`
`description: “[a]ny conventional decoder including a decoder complying to the
`
`MPEG-1, MPEG-2, H.261, or H.261 standards, or any combination of them, of any
`
`conventional standard can be used as the decoder/encoder.” (Ex. 1001, 15:30-33).
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`A person of skill in the art would recognize that such a decoder would ordinarily
`
`be implemented using a combination of hardware, such as a digital signal
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`processor (DSP) with or without specialized computational pipelines, and software.
`
`41.
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`It is therefore my opinion based on my review of the ’045 Patent that
`
`one of ordinary skill in the art would understand that “decoder” means video
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`and/or audio decompression device. In context of claim 12, the “decoder” is
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`directed to image processing as the claim recites that the decoder is coupled to a
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`bus for “receiving encoded video images and for outputting data for displaying the
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`decoded video images ….” (Ex. 1001, 16:57-59). The “video decoder” in the
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`context of independent claims 1, 4, and 5 is for “receiving encoded video images
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`and for outputting data for displaying the decoded video images” (using claim 1 as
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`representative). (Ex. 1001, 15:41-42).
`
`42. Thus, “decoder” in the context of claims 12 and 15-17 and “video
`
`
`
`–19–
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`decoder” in the context of claims 1, 4, 5, 7, 9, and 10 means video decompression
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`device.
`
`43.
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` “fast bus”
`
`44. The ’045 Patent identifies several known bus architectures as
`
`exemplary “fast bus[es]” – “a fast bus (such as a memory bus, a PCI– “Peripheral
`
`Component Interconnect”–bus, a VLB – “VESA (Video Electronics Standards
`
`Association) Local Bus”, or an AGP– “Advanced Graphics Port”– bus, or any bus
`
`having a bandwidth sufficient to allow the system to operate in real time)[.]” (Ex.
`
`1001, 5:26-31). More generally, the ’045 Patent describes a “fast bus” as “any bus
`
`having a bandwidth sufficient to allow the system to operate in real time.” (Ex.
`
`1001, 5:26-31). (Emphasis added). (See also, 7:51-58). For the purposes of my
`
`analysis herein, “fast bus” is any bus having a bandwidth sufficient to allow the
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`system to operate in real time.
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`45. Other claim terms
`
`46.
`
`I have reviewed Ex. 1014, which is a Joint Claim Construction and
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`Prehearing Statement, which identifies several terms to which construction has
`
`been agreed between parties. Unless otherwise noted, these agreed constructions
`
`(including “bus,” “display device,” “display adapter,” “arbiter,” “arbiter circuit,”
`
`and “memory arbiter”) are applied in the present invalidity analysis to the extent
`
`they are recited in the claims.
`
`
`
`–20–
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`Page 20 of 87
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`VII. Overview of References
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`A. Overview of Bowes (U.S. Patent No. 5,546,547)
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`47. Bowes describes the components and operation of an arbitration
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`scheme “for a computer system in which a digital signal processor resides on the
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`computer system’s memory bus without requiring a block of dedicated static
`
`random access memory.” (Ex. 1005, Abstract). Bowes recognizes that “SRAMs
`
`are significantly more expensive than DRAM which greatly increases the cost of
`
`computer systems which incorporate SRAM.” (Ex. 1005, 2:36-41).
`
`48. Bowes teaches that the computer system includes multiple “bus
`
`masters” coupled to a common memory bus. (Ex. 1005, 2:52-3:2, 4:15-17). The
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`examples given in Bowes of “bus masters” include “the CPU, the DSP, the I/O
`
`interface and the NuBus controller.” (Ex. 1005, 7:66-67). These devices are
`
`illustrated in the computer system architecture of FIG. 2:
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`
`
`–21–
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`Page 21 of 87
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`Ex. 1005, Bowes, Figure 2
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`
`
`49. The computer system includes the CPU 10, which is coupled to the
`
`memory bus 110. The DSP 20 also resides “on the system's memory bus and
`
`operate[s] from the computer system's main memory subsystem 14.” (Ex. 1005,
`
`6:23-25). Other bus masters, including the I/O interface 30 and NuBus controller
`
`40, are also coupled to the memory bus 110. Bowes acknowledges that its
`
`teachings regarding the “broad concept of providing for a DSP on a memory bus
`
`and sharing the system's DRAM may be extended to other more complicated
`
`systems, or generalized to simpler systems.” (Ex. 1005, 5:3-6).
`
`
`
`–22–
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`50. Each bus master may, at some point, access the main memory
`
`subsystem 14 illustrated in FIG. 2. A person having ordinary skill in the art would
`
`recognize that any of the bus masters (e.g., CPU 10, DSP 20, I/O interface 30, and
`
`NuBus controller 40) would have access to the shared main memory subsystem 14
`
`through their respective access and control of the common memory bus 110.
`
`51. Bowes teaches that access to the memory is controlled by arbitration
`
`of control for the memory bus 110. Bowes does so by providing “a mechanism and
`
`method for arbitrating the memory bus bandwidth to efficiently allow the use of a
`
`digital signal processor and a CPU over a common memory bus sharing the
`
`system's dynamic random access memory subsystem without requiring an
`
`expensive block [of] static random access memory.” (Ex. 1005, 2:57-63). Bowes
`
`further teaches that the arbitration is an adaptive scheme “that varies access to the
`
`memory bus as a function of time and depends upon what operations the various
`
`bus masters are requesting.” (Ex. 1005, 3:15-18).
`
`52. Bowes teaches that the arbitration scheme is designed to enable the
`
`DSP to perform real-time processing for real-time operations, which require access
`
`to the main memory subsystem 14, while still allowing the other bus masters
`
`opportunity to obtain access. (See Ex. 1005, 6:35-38). “The scheme is implemented
`
`such that the DSP is provided with sufficient bandwidth to perform real-time
`
`digital signal processing using the system's dynamic random access memory
`
`
`
`–23–
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`(DRAM) and not requiring the incorporation of an expensive block of static
`
`random access memory (SRAM).” (Ex. 1005, 4:55-60) (emphasis added).
`
`53. Some of the real-time operations that Bowes teaches may be
`
`performed by the DSP 20 include speech processing, audio channel control,
`
`modem emulation, image processing and the like. (Ex. 1005, 6:33-35). While
`
`memory bandwidth requirements for some of these operations would have been
`
`considered substantial, busses commonly employed at the time would have been
`
`up to the task as discussed below.
`
`54.
`
` Bowes does not explicitly describe a DSP that performs video and/or
`
`audio decoding. However, Bowes suggests that “emerging digital-processing
`
`technologies” make possible new multimedia applications that include video and
`
`audio. (See Ex. 1005, 1:35-41). A person of ordinary skill in the art would
`
`interpret this reference to new multimedia applications including video as
`
`suggestive of at least video decoding workloads.
`
`B. Overview of DSP3210 Data Sheet
`
`55. As above, Bowes provides a digital signal processor (DSP 20 in FIG.
`
`2 of Bowes) that resides on the system’s memory bus and operates out of the
`
`computer’s main memory. (Ex. 1005, 6:22-26). Bowes suggests that in some
`
`embodiments this DSP 20 “is an AT&T DSP3210” device. (Ex. 1005, 6:28-30)