Trials@uspto.gov
`571-272-7822
`
`
`Paper 7
`Entered: December 7, 2016
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01114
`Patent 7,777,753 B2
`____________
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
`
`Paper 7
`Entered: December 7, 2016
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01114
`Patent 7,777,753 B2
`____________
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2016-01114
`Patent 7,777,753 B2
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`
`INTRODUCTION
`I.
`Apple Inc. (“Petitioner”) filed a Petition requesting inter partes
`review of claims 1, 2, 4, 7–10, and 12 (“the challenged claims”) of U.S.
`Patent No. 7,777,753 B2 (Ex. 1001, “the ’753 patent”). Paper 2 (“Pet.”).
`Parthenon Unified Memory Architecture LLC (“Patent Owner”) filed a
`Preliminary Response. Paper 6 (“Prelim. Resp.”). We review the Petition
`pursuant to 35 U.S.C. § 314, which provides that an inter partes review may
`be authorized only if “the information presented in the petition . . . and any
`[preliminary] response . . . shows that there is a reasonable likelihood that
`the petitioner would prevail with respect to at least 1 of the claims
`challenged in the petition.” 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a). Upon
`consideration of the Petition and the Preliminary Response, and the
`accompanying evidence, we determine that the information presented by
`Petitioner establishes that there is a reasonable likelihood that Petitioner
`would prevail in showing the unpatentability of at least one of the
`challenged claims of the ’753 patent. Accordingly, pursuant to 35 U.S.C.
`§ 314, we institute an inter partes review of claims 1, 2, 4, 7–10, and 12 of
`the ’753 patent.
`
`A. Related Proceedings
`
`The ’753 patent is involved in several cases pending in the Eastern
`District of Texas. Pet. 1–2; Paper 5, 1–2. The ’753 patent also is involved
`in Samsung Electronics, Ltd. v. Parthenon Unified Memory Architecture,
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`Case IPR2015-01501 (instituted)1 and was involved in ZTE USA, Inc. v.
`Parthenon Unified Memory Architecture, Case IPR2016-00670 (now
`terminated). Pet. 2. Petitioner also has filed other petitions seeking inter
`partes review of related patents.
`
`B. The ’753 patent
`The ’753 patent relates generally “to the field of electronic systems
`having a video and/or audio decompression and/or compression device, and
`is more specifically directed to sharing a memory interface between a video
`and/or audio decompression and/or compression device and another device
`contained in the electronic system.” Ex. 1001, col. 1, ll. 36–41. As of the
`effective filing date of the ’753 patent,2 a typical decoder included a
`dedicated memory, which represented a significant percentage of the cost of
`the decoder and which went unused most of the time. Id. at col. 2, ll. 21–63,
`col. 4, ll. 43–60, Figs. 1a–1c.
`
`
`1 The statutory deadline to issue a Final Written Decision in IPR2015-01501
`is January 6, 2017. Upon issuance of a Final Written Decision in that
`proceeding, the panel shall determine whether it is appropriate to maintain
`this proceeding against all or some of the claims, upon which review is
`instituted, or to terminate this proceeding and vacate this Decision on
`Institution. See 35 U.S.C. § 315(d).
`2 The ’753 patent claims the benefit of a string of earlier-filed U.S. patent
`applications, the earliest of which was filed on August 26, 1996. Pet. 7.
`Petitioner does not challenge the entitlement of the ’753 patent to this
`earliest filing date and “believes that the ’753 Patent will expire during
`pendency of the requested inter partes review proceeding.” Id. at 12. In a
`related proceeding, Patent Owner expressly stated that the expiration date for
`the ’045 patent is August 26, 2016. Case IPR2015-01501, Paper 8, 1; see
`Prelim. Resp. 3.
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`To address these and other concerns, the ’753 patent discloses an
`electronic system in which a first device and a video and/or audio
`decompression and/or compression device are coupled to a shared memory
`through a bus that may have bandwidth sufficient for the video and/or audio
`decompression and/or compression device to operate in real time. Id. at col.
`4, l. 64–col. 5, l. 7. Figure 2 of the ’753 patent is reproduced below.
`
`
`
`Figure 2 is a block diagram of an electronic system that contains a device
`with a memory interface and an encoder and decoder. Id. at col. 6, ll. 3–5.
`“First device 42 can be a processor, a core logic chipset, a graphics
`accelerator, or any other device that requires access to the memory 50 . . . .”
`Id. at col. 6, ll. 29–32. Both first device 42 and decoder/encoder 80 have
`access to memory 50 through memory interfaces 72 and 76, respectively,
`coupled to fast bus 70. Id. at col. 6, ll. 27–29, col. 7, ll. 26–28, 48–51. Fast
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`bus 70 may have at least the bandwidth required for decoder/encoder 80 to
`operate in real time and, preferably, has a bandwidth of at least
`approximately twice the bandwidth required for decoder/encoder 80 to
`operate in real time. Id. at col. 7, ll. 48–51, col. 8, ll. 28–33.
`During operation, decoder/encoder 80, first device 42, and refresh
`logic 58, if it is present, request access to memory 50 through arbiter 82. Id.
`at col. 12, ll. 53–56. Arbiter 82 determines which of the devices may access
`memory 50. Id. at col. 12, ll. 57–58. Decoder/encoder 80 may get access to
`memory 50 in the first time interval, and first device 42 may get access to
`memory 50 in the second time interval. Id. at col. 12, ll. 58–61. Direct
`Memory Access (DMA) engine 52 of decoder/encoder 80 determines the
`priority of decoder/encoder 80 for access to memory 50 and the burst length
`when decoder/encoder 80 has access to memory 50. Id. at col. 12, ll. 61–67.
`DMA engine 60 of first device 42 determines its priority for access to
`memory 50 and the burst length when first device 42 has access to memory
`50. Id. at col. 12, ll. 65–67.
`When decoder/encoder 80 or one of the other devices generates a
`request to access memory 50, the request is transferred to arbiter 82, and
`access to memory 50 is determined based on the state of arbiter 82 and on a
`priority scheme. Id. at col. 13, ll. 1–30. In particular,
`
`[t]he state of the arbiter 82 is determined. The arbiter typically
`has three states. The first state is idle when there is no device
`accessing the memory and there are no requests to access the
`memory. The second state is busy when there is a device
`accessing the memory and there is no other request to access the
`memory. The third state is queue when there is a device
`accessing the memory and there is another request to access the
`memory.
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`Id. at col. 13, ll. 3–10 (emphases added). The priority scheme can be any
`scheme that ensures decoder/encoder 80 gets access to memory 50 often
`enough to operate properly, but does not starve entirely other devices
`sharing memory 50. Id. at col. 13, ll. 31–37; see id. at col. 8, ll. 9–13
`(describing a “starvation period”).
`
`C. Illustrative Claim
`Of the challenged claims, claims 1 and 7 are independent. Id. at col.
`15, ll. 32–59 (claim 1), col. 16, ll. 15–36 (claim 7). Claims 2 and 4 depend
`directly from claim 1, and claims 8–10 and 12 depend directly from claim 7.
`Id. at col. 15, l. 60–col. 16, l. 9, col. 16, ll. 37–59, 62–63. Claim 1 is
`illustrative and is reproduced below.
`An electronic system comprising:
`1.
`a bus;
`a main memory coupled to the bus having stored therein
`data corresponding to video images;
`a video circuit coupled to the bus, the video circuit
`configured to receive data from the main memory
`corresponding to a current video image to be decoded and to
`output decoded video data corresponding to the current video
`image to be displayed on a display device, the current video
`image to be displayed adapted to be stored in the main memory;
`a processor coupled to the main memory, the processor
`for storing non-image data in the main memory and retrieving
`non-image data from the main memory; and
`an arbiter circuit coupled to the processor and to the
`video circuit, the arbiter circuit configured to receive requests
`for access to the main memory from the video circuit and the
`processor and to control access to the main memory by:
`providing access to the main memory for a request for
`access to the main memory when the arbiter circuit is in an idle
`state;
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`queuing a request for access to the main memory when
`the arbiter circuit is in a busy state; and
`queuing a request for access to the main memory in an
`order based on a priority of the request and a priority of each of
`one or more other requests for access to the main memory that
`are currently queued when the arbiter circuit is in a queue state.
`Id. at col. 15, ll. 32–59.
`D. Applied References and Declaration
`Petitioner relies upon the following references and declaration in
`support of its grounds for challenging the identified claims of the
`’753 patent.
`Exhibit
`1002
`1003
`1004
`1005
`
`References and Declaration
`File History of U.S. Patent No. 7,777,753 B2
`Declaration of Robert Colwell, Ph.D. (“Colwell Decl.”)
`Curriculum Vitae of Robert Colwell, Ph.D.
`U.S. Patent No. 5,546,547, filed Jan. 28, 1994, issued Aug.
`13, 1996 (“Bowes”)
`AT&T DSP3210 Digital Signal Processor, The Multimedia
`Solution, Data Sheet, March 1993 (“Datasheet”)
`EP Patent Application Publication No. 0 626 653 A1, publ’d
`Nov. 30, 1994 (“Artieri”)3
`Patent No. US 6,029,217, filed Oct. 3, 1994, issued Feb. 22,
`2000 (“Arimilli”)
`Robert J. Gove, “The MVP: A Highly-Integrated Video
`Compression Chip,” Proceedings of the IEEE Data
`Compression Conference (DCC ‘94), pp. 215–224 (March
`29–31, 1994) (“Gove”)
`T. Shanley et al., “PCI System Architecture,” Addison-
`Wesley Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”)
`U.S. Patent No. US 5,787,264, filed May 8, 1995, issued
`July 28, 1998 (“Christiansen”)
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`
`3 Exhibit 1007 includes an English translation (pp. 1–57), and affidavit of
`translation (p. 58), and the French language publication (pp. 59–85).
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`Pet. 7–10.
`
`E. Asserted Grounds of Unpatentability
`Petitioner argues that the challenged claims are unpatentable based on
`the following grounds (id.):
`References
`
`Basis
`
`Challenged
`Claim(s)
`1 and 2
`
`Bowes, Datasheet, Artieri, and
`Arimilli
`Bowes, Datasheet, Artieri,
`Arimilli, and Shanley
`Bowes, Datasheet, Artieri, and
`Christiansen
`Bowes, Datasheet, Artieri,
`Arimilli, and Christiansen
`Bowes, Datasheet, Artieri,
`Christiansen, and Shanley
`Bowes, Datasheet, Artieri,
`Christiansen, and Gove
`
`35 U.S.C. § 103(a)
`
`35 U.S.C. § 103(a)
`
`35 U.S.C. § 103(a)
`
`4
`
`7
`
`35 U.S.C. § 103(a)
`
`8 and 10
`
`35 U.S.C. § 103(a)
`
`9
`
`35 U.S.C. § 103(a)
`
`12
`
`II. ANALYSIS
`A. Claim Construction
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent
`that will not expire before a final written decision is issued shall be given its
`broadest reasonable construction in light of the specification of the patent in
`which it appears.” Patent Owner has stated, however, that the ’753 patent
`expired on August 26, 2016. Case IPR2015-01501, Paper 8, 1. Thus, the
`’753 patent expired before we will issue any Final Written Decision as to the
`patentability of the challenged claims in this case or in the related case, Case
`IPR2015-01501. See Pet. 12. Therefore, we apply a district court-type
`claim construction.
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`Petitioner proposes constructions for three claim terms: (1) “decoder,”
`(2) “video circuit,” and (3) “memory interface circuit.” Pet. 12–15.
`Petitioner further argues that its proposed constructions of certain claim
`terms are consistent with the claim construction standard used by the U.S.
`district courts, as set forth in Phillips v. AWH Corp., 415 F.3d 1303, 1314
`(Fed. Cir. 2005) (en banc). Pet. 11–12. Patent Owner proposes
`constructions for two claim terms: (1) “decoder” and (2) “memory interface
`circuit.” Prelim. Resp. 4–5. In order to determine if Petitioner has
`demonstrated a reasonable likelihood that it will prevail in this initial
`proceeding, given the patent’s expiration, we analyze Petitioner’s arguments
`through the lens of the claim construction standard of Phillips that will apply
`to any Final Written Decision. 37 C.F.R. § 42.100(b); see Toyota Motor
`Corp. v. Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8–10 (PTAB
`Aug. 14, 2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
`2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.” (internal citation omitted)).
`“In determining the meaning of the disputed claim limitation, we look
`principally to the intrinsic evidence of record, examining the claim language
`itself, the written description, and the prosecution history, if in evidence.”
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). The words of a
`claim generally are given their ordinary and customary meaning, and that is
`the meaning the term would have to a person of ordinary skill at the time of
`the invention, in the context of the entire patent including the specification.
`See Phillips, 415 F.3d at 1312–13. Claims are not interpreted in a vacuum,
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`but are a part of and read in light of the specification. See Slimfold Mfg. Co.
`v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir. 1987). Although it is
`improper to read a limitation from the specification into the claims, the
`claims still must be read in view of the specification of which they are a part.
`See Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1347 (Fed. Cir.
`2004).
`1. “decoder” (Claims 7, 8, and 12)
`Each of challenged claims 7, 8, and 12 recites a “decoder.” E.g., Ex.
`1001, col. 16, ll. 18–25. Petitioner proposes to construe the term “decoder”
`to mean “video decompression device.” Pet. 12–13 (citing Ex. 1001, col. 1,
`ll. 66–67 (“a video and/or audio decompression device (hereinafter
`‘decoder’)”), col. 15, ll. 27–30 (“Any conventional decoder including a
`decoder complying to the [Moving Picture Experts Group (MPEG)]-1,
`MPEG-2, H.261, or H.261 standards, or any combination of them, or any
`other conventional standard can be used as the decoder/encoder.”)); see
`Phillips, 415 F.3d at 1312–13 ( regarding a term’s ordinary and customary
`meaning to a person of ordinary skill in the art, in the context of the entire
`patent, including the specification).
`Patent Owner disagrees with Petitioner’s proposed construction.
`Prelim. Resp. 4.
`Patent Owner requests that to the extent the Board deems a
`construction [of “decoder”] necessary, it construe this term
`consistent with the term’s construction in parallel proceedings.
`Specifically, Patent Owner requests that the term “decoder” be
`construed to mean “hardware and/or software that translates
`data streams into video or audio information.”
`Id. at 4–5 (emphasis added).
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`As an initial matter, we do not agree with Petitioner that the ’753
`patent sets forth a special definition for the claim term “decoder.” For
`convenience, the disclosures in the Specification relied upon by Petitioner to
`support its argument include: (1) “[t]he resulting bitstream is decoded by a
`video and/or audio decompression device (hereinafter decoder) before the
`video and/or audio sequence is displayed” (Ex. 1001, col. 1, l. 66–col. 2, l. 1
`(emphasis added)); and (2) “[a]ny conventional decoder including a decoder
`complying to the MPEG-1, MPEG-2, H.261, or H.261 [sic] standards, or
`any combination of them, or any other conventional standard can be used as
`the decoder/encoder” (id. at col. 15, ll. 27–30). In our view, these cited
`disclosures do not amount to clear, deliberate, and precise statements as to
`the meaning or significance of the claim term “decoder” in the context of the
`’753 patent, but rather simply indicate that “a decoder” is the shorthand
`description for “a video and/or audio decompression device.”
`To the extent Petitioner asserts that the claim term “decoder” should
`be limited to just a “device,” i.e., hardware, we also are not persuaded. See
`Pet. 11–12. The ’753 patent discloses that “[t]he audio decoding can be
`performed . . . through software.” Ex. 1001, col. 6, ll. 52–54 (emphasis
`added). The Specification further discloses that:
`In the preferred embodiment of the invention, when the
`decoder/encoder 80 is in a system containing a processor and is
`coupled to the processor, the audio decoding is performed in
`software. . . . If the audio decoding is performed in software, the
`processor should preferably operate at a speed to allow the audio
`decoding to be performed in real time without starving other
`components of the system that may need to utilize the processor.
`Id. at col. 6, ll. 54–62 (emphases added). These disclosures in the
`Specification clearly indicate that decoding is not limited to hardware, but
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`also may be performed in software. Petitioner’s proposed construction does
`not take into account this aspect of decoding disclosed in the Specification.
`In view of our analysis set forth in Case IPR2015-01501, Paper 12,
`10–11 (Ex. 2005, 10–11), which analysis is incorporated herein by
`reference,4 and after considering fully the arguments presented by the parties
`here, we are persuaded that Patent Owner’s proposed construction of the
`claim term “decoder” as “hardware and/or software that translates data
`streams into video or audio information” is the ordinary and customary
`meaning of this claim term, as would be understood by one of ordinary skill
`in the art, in the context of the entire disclosure of the ’753 patent. See
`Phillips, 415 F.3d at 1312–13. Patent Owner’s proposed construction is
`consistent with: (1) certain disclosures in the Specification of the
`’753 patent (see, e.g., Ex. 1001, col. 6, ll. 54–62 (disclosing that “audio
`decoding can be performed . . . through software”)); (2) at least one
`dictionary definition of “decoder” (Ex. 2002, 56 (defining a “decoder” as
`“[a]ny hardware or software system that translates data streams into video or
`audio information”)); and (3) our construction of the claim terms “decoder”
`and “video decoder” in Case IPR2015-01501 (Ex. 2005, 10–11 (construing
`the claim phrase “decoder” as “hardware and/or software that translates data
`streams into video or audio information”)).
`2. “video circuit” (Claims 1, 2, and 4)
`Each of challenged claims 1, 2, and 4 recites a “video circuit.” E.g.,
`Ex. 1001, col. 15, ll. 36–42. Petitioner proposes to construe the term “video
`
`
`4 The parties may not incorporate arguments into their filings in this
`proceeding by reference. 37 C.F.R. § 42.6(a)(3).
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`circuit” to mean “hardware of a video decoder.” Pet. 14 (citing Ex. 1003
`¶¶ 43–47). Patent Owner does not contest Petitioner’s proposed
`construction or propose an alternative construction. We agree that the word
`“circuit” here refers to hardware. In view of our construction of “decoder,”
`however, we are not persuaded that that Petitioner’s proposed construction is
`consistent. Therefore, to the extent necessary for this Decision, we construe
`“video circuit” to mean “hardware that translates data streams into video
`information.”
`3. “memory interface circuit” (Claim 7)
`Challenged claim 7 recites a “memory interface circuit.” Ex. 1001,
`col. 16, l. 25. Petitioner proposes to construe the term “memory interface
`circuit” to mean “hardware, including signaling paths to or from a
`competing device or an arbiter, to coordinate communication via a memory
`bus.” Pet. 15 (citing Ex. 1003 ¶¶ 48–53). Patent Owner does not dispute
`Petitioner’s construction, but notes that “in parallel litigation, the Court
`construed the term ‘memory interface’ to include ‘hardware, or hardware
`with software’ and the parties agreed that the term should include
`“hardware’ as well as ‘hardware with software.’” Prelim. Resp. 5 (citing
`Ex. 2001, 18–22).
`Nevertheless, this claim term includes the word “circuit” and, thus,
`differs from the term construed by the U.S. district court. Pet. 14–15; see
`Ex. 2001, 18 (construing “memory interface”). Petitioner’s declarant,
`Dr. Colwell, confirms that a person of ordinary skill in the art “would
`understand the term ‘memory interface circuit’ (as it is used in the
`’753 Patent) to include request/grant lines or signaling paths (e.g., to/from
`other bus requesters or an arbiter) to coordinate interaction of multiple
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`devices contending for bus access to memory.” Id. at 15 (emphasis omitted)
`(citing Ex. 1003 ¶¶ 48-53). Therefore, to the extent necessary for this
`Decision, we adopt Petitioner’s construction of the term “memory interface
`circuit.”
`4. Other Claim Terms
`Petitioner offers no other constructions of any claim term of the
`challenged claims. See Pet. 12–16. Only terms which are in controversy in
`this proceeding need to be construed, and then only to the extent necessary
`to resolve the controversy. Wellman, Inc. v. Eastman Chem. Co., 642 F.3d
`1355, 1361 (Fed. Cir. 2011) (explaining that “claim terms need only be
`construed ‘to the extent necessary to resolve the controversy’” (quoting
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999))). For purposes of this Decision, no other claim terms require express
`construction.
`
`1. Overview
`
`B. Obviousness
`
`Petitioner argues that claims 1, 2, 4, 7–10, and 12 of the ’753 patent
`are rendered obvious by Bowes, Datasheet, and Artieri, alone or in
`combination with one or more of Arimilli, Christiansen, Shanley, and Gove.
`See supra Section I.E.5 A patent claim is unpatentable under 35 U.S.C.
`
`
`5 Petitioner argues that it is neither a privy nor a real party-in-interest to the
`petitioners in Case IPR2015-01501 or Case IPR2016-00670 and that the
`instant Petition is not barred under 35 U.S.C. § 315(b). Pet. 10. Further,
`Petitioner argues that the grounds asserted in the instant Petition rely on
`different prior art combinations, different arguments regarding the asserted
`prior art, and different declarant testimony than those relied upon in the
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`§ 103(a) if the differences between the claimed subject matter and the prior
`art are “such that the subject matter[,] as a whole[,] would have been
`obvious at the time the invention was made to a person having ordinary skill
`in the art to which said subject matter pertains.” KSR Int’l Co. v. Teleflex
`Inc., 550 U.S. 398, 406 (2007). The question of obviousness is resolved on
`the basis of underlying factual determinations, including: (1) the scope and
`content of the prior art; (2) any differences between the claimed subject
`matter and the prior art; (3) the level of skill in the art; 6 and (4) objective
`evidence of nonobviousness, i.e., secondary considerations.7 Graham v.
`John Deere Co., 383 U.S. 1, 17–18 (1966). On this record and for the
`reasons set forth below, we are persuaded that Petitioner demonstrates a
`reasonable likelihood of prevailing in showing that claims 1, 2, 4, 7–10, and
`12 of the ’753 patent are unpatentable.
`
`
`earlier challenges to the claims of the ’753 patent. Id. at 10–11. Therefore,
`Petitioner argues that we should not deny the Petition pursuant to 35 U.S.C.
`§ 325(d). Id. at 11. Because, on this record, we do not find Petitioner to be
`either a privy or a real party-in-interest to the previous petitioners and
`because we find the arguments and the asserted references to be sufficiently
`different from those previously before the Office, we do not deny the
`Petition under 35 U.S.C. § 315(b) or § 325(d).
`6 Petitioner’s declarant proposes an assessment for a person of ordinary skill
`in the art. Ex. 1003 ¶ 20. Patent Owner does not challenge Petitioner’s
`proposed assessment and does not propose an alternative. To the extent
`necessary and for purposes of this Decision, we adopt Petitioner’s
`declarant’s assessment.
`7 Patent Owner does not contend in its Preliminary Response that such
`secondary considerations are present.
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`2. Claims 1 and 2 — Obviousness over Bowes, Datasheet, Artieri,
`and Arimilli
`Petitioner argues that claims 1 and 2 are unpatentable under
`35 U.S.C. § 103(a) as obvious over Bowes, Datasheet, Artieri, and Arimilli.
`Pet. 16–42.
`
`a. Bowes (Ex. 1005)
`Bowes describes a memory bus arbiter for a computer system having
`a DSP co-processor. Ex. 1005, Title. According to Bowes,
`[i]n prior art computer systems, because of the high bandwidth
`required for real-time processing by a DSP, it has not been
`possible for the DSP to run off of the computer system’s
`[dynamic random access memory (DRAM)] in the way the
`[central processor unit (CPU)] 10 utilizes it without adversely
`affecting the rest of the computer system. Thus, there has been
`provided a large block of [static random access memory
`(SRAM)] 24 for use by the DSP 20. . . .
`A significant disadvantage to the prior art computer architecture
`of FIG. 1 is the requirement of a substantial block of static
`random access memory 24. SRAMs are significantly more
`expensive than DRAM which greatly increases the cost of
`computer systems which incorporate SRAM.
`Id. at col. 2, ll. 36–48. Thus, it is an object of Bowes “to provide a
`mechanism and method for arbitrating the memory bus bandwidth to
`efficiently allow the use of a digital signal processor and a CPU over a
`common memory bus sharing the system’s dynamic random access
`memory subsystem without requiring an expensive block static
`random access memory.” Id. at col. 2, ll. 57–63 (emphasis added).
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`Figure 2 of Bowes is reproduced below.
`
`
`Figure 2 illustrates a block diagram of a computer architecture incorporating
`the arbitration scheme described in Bowes. Id. at col. 3, ll. 62–64. “The
`scheme is implemented such that the DSP is provided with sufficient
`bandwidth to perform real-time digital signal processing using the system’s
`[DRAM] and not requiring the incorporation of an expensive block of
`[SRAM].” Id. at col. 4, ll. 55–60.
`As shown in Figure 2, the system includes CPU 10, memory
`controller and arbiter (MCA) 200, main memory subsystem 14, and DSP 20.
`Id. at Fig. 2. “Unlike prior art computer systems, the [system of Bowes]
`provides for the DSP 20 to reside on the system’s memory bus and operate
`from the computer systems’ main memory subsystem 14.” Id. at col. 6,
`ll. 22–26. “[T]his greatly reduces system cost by eliminating the need for an
`expensive block of SRAM.” Id. at col. 6, ll. 26–29. In a preferred
`embodiment, MCA 200 “is an application[] specific integrated circuit
`(ASIC) for arbitrating memory bus 110 between the various bus masters
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`subject to the constraints each imposes to provide optimal bandwidth for
`each, particularly the DSP which is responsible for a significant amount of
`real-time signal processing.” Id. at col. 6, ll. 46–52.
`
`b. Datasheet (Ex. 1006)
`Datasheet describes the AT&T DSP3210 Digital Signal Processor.
`Ex. 1006, 1. The AT&T DSP3210 Digital Signal Processor is intended to be
`used in multimedia environments. Id. at 3. According to Datasheet, “[t]he
`DSP3210 is intended to be used in PC and workstation system architectures
`in which the DSP3210 is a parallel processor to a host processor.” Id. at 4.
`“The primary benefit of this system architecture is the DSP’s ability to
`access program and data from system memory without host intervention.
`Furthermore, expensive local SRAM is replaced by the computer’s existing
`system memory.” Id. (emphasis added).
`
`c. Artieri (Ex. 1007)
`Artieri describes “the main elements of an MPEG decoder.” Ex.
`1007, 2.8
`
`Any MPEG decoder, in particular for standard MPEG 2,
`generally includes a variable length word decoder 10 (VLD), a
`sequence-of-zeros decoder 11 (RLD), an inverse quantization
`circuit 12 (Q-1), an inverse discrete cosine transform circuit 13
`(DCT-1), a half-pixel filter 14, and a memory 15. The encoded
`data are input via a bus CDin, and the decoded data are output
`via a bus VIDout. Between the input and the output, the data
`pass through the processing circuits 10 to 13 in the order
`indicated above, which is illustrated by arrows in dotted lines.
`The output of the decoder is provided by an adder 16 that sums
`the outputs of the filter 14 and of the cosine transform circuit 13.
`
`8 Citations are to the page numbers in the footer added by Petitioner, e.g.,
`“Apple Exhibit 1007 Page 2 of 85.”
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`The filter 14 needs a previously decoded image portion stored in
`memory 15.
`Id. Artieri also teaches that the memory must have three areas. See, e.g., id.
`at 14 (“For this purpose, the memory 15 must include three image areas
`IM1, IM2 and IM3 for storing the image in the process of reconstruction and
`two previously decoded images.”), Fig. 3 (depicting IM1, IM2, and IM3
`within memory 15).
`
`
`
`d. Arimilli (Ex. 1008)
`
`Arimilli is directed “to data processing systems and, in particular, to a
`system and method for intelligent communication of bus requests and bus
`grants within a data processing system.” Ex. 1008, col. 1, ll. 40–43.
`Arimilli’s Figure 1 is reproduced below.
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`In Figure 1, Arimilli depicts multiprocessor data processing system 100,
`which includes a plurality of processing units 102, 104, 106 and system
`memory 112 on shared system bus 108. Id. at col. 3, ll. 46–63, Fig. 1.
`Arimilli’s system controller 130 acts as a system arbiter and “[r]equests and
`grants of bus access are all controlled by system controller 130.” Id. at
`col. 3, ll. 62–63. “When a peripheral device sends a bus request to the
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`system controller, it is ‘queued’ by receiving the request using an input latch
`of the system controller.” Pet. 18 (citing Ex. 1008, col. 4, ll. 16–34; Ex.
`1003 ¶ 82). Alternatively, Arimilli may include, within its arbitration
`scheme, a state in which no device is requesting access to the bus or in
`which system controller 130 has granted access to other system devices. Ex.
`1008, col. 4, l. 19 (table describing the “Null” state), col. 6, ll. 7–25
`(describing “null” and “NG” notations); see Pet. 37; see also Ex. 1003 ¶ 122
`(“this type of arbitration architecture that included behavior within the
`arbiter circuitry to accept requests from peripheral devices and have the
`arbiter maintain the requests in a queue, was also known in the art”).
`
`e. Analysis
`
`In view of the arguments and evidence of record, we are persuaded
`that Petitioner has established a reasonable likelihood of prevailing in
`showing that claims 1 and 2 are unpatentable as obvious over Bowes,
`Datasheet, Artieri, and Arimilli. Pet. 23–42.
`
`i. Claim 1
`
`With respect to independent claim 1, we are persuaded that the
`combination of the teachings of Bowes, Datasheet, Artieri, and Arimilli
`teaches or suggests all of the recited limitations. Pet. 16–42. Petitioner
`provides a detailed mapping of the limitations of challenged claim 1 onto the
`combined teachings of Bowes, Datasheet, Artieri, and Arimilli. Id. at
`23–41; see Ex. 1003 ¶ 131 (pgs. 71–87). Initially, Petitioner argues that a
`person of ordinary skill in the art would have found it obvious to combine
`the teachings of Bowes and Datasheet “based on Bowes’ specific reference
`to, and
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