IPR2016-01114
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753 
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONERS
`
`V.
`
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`Case IPR No: 2016-01114
`Patent No. 7,777,753
`TITLE: ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY
`ALLOWING ACCESS TO A SHARED MEMORY
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
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`IPR2016-01114
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`TABLE OF CONTENTS
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`
`INTRODUCTION ............................................................................................... 1
`I.
`II. THE `753 PATENT .......................................................................................... 2
`III. CLAIM CONSTRUCTION ............................................................................. 3
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD
`THAT ANY CHALLENGED CLAIM IS INVALID ............................................... 6
`1. Ground 1: Bowes, Datasheet, Artieri, and Arimilli (claims 1 and 2) ............... 6
`a. The MPEG Standard Was Considered During the Prosecution of the `753
`Patent ................................................................................................................... 6
`b. Artieri Mirrors the Implementation Identified as Prior Art by the `753
`Patent ................................................................................................................... 7
`c. The combination of Bowes, Datasheet, Artieri and Arimilli does not
`disclose every element of claims 1 and 2 of the `753 Patent ............................ 10
`i. The proposed combination does not disclose “providing access to the main
`memory for a request for access to the main memory when the arbiter circuit is
`in an idle state” [claim 1] ................................................................................... 10
`ii. The proposed combination does not disclose wherein the video
`circuit/decoder is further configured to receive data from the [main] memory
`corresponding to at least one previously decoded [video] image [claim 2] ...... 15
`iii. The proposed combination does not disclose an arbiter that controls
`access to the main memory [claim 1] ................................................................ 30
`d. No motivation to combine Bowes and Artieri ............................................ 36
`2. Ground 2: Bowes, Datasheet, Artieri, Arimilli, and Shanley (claim 4) ......... 50
`3. Ground 3: Bowes, Datasheet, Artieri, and Christiansen (claim 7) ................. 50
`4. Ground 4: Bowes, Datasheet, Artieri, Christiansen and Arimilli (claims 8 and
`10) 52
`5. Ground 5: Bowes, Datasheet, Artieri, Christiansen, and Shanley (claim 9) .. 53
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`IPR2016-01114
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`6. Ground 6: Bowes, Datasheet, Artieri, Christiansen, and Gove (claim 12) .... 54
`V. CONCLUSION .................................................................................................. 54
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`TABLE OF AUTHORITIES
`
`
`
`Cases
`C.R Bard, Inc. v. M3 Sys., Inc.,
` 157 F.3d 1350 (Fed. Cir. 1998) ..................................................................... 36, 38
`
`In re Fine,
` 837 F.2d 1071 (Fed. Cir. 1988) ..................................................................... 48, 51
`
`In re Rambus Inc.,
` 694 F.3d 42 (Fed. Cir. 2012) .................................................................................. 4
`
`In re Wilson,
` 424 F.2d 1382, (CCPA 1970) ............................................................................... 10
`
`Karlin Tech., Inc. v. Surgical Dynamics, Inc.,
` 177 F.3d 968, (Fed. Cir. 1999) ............................................................................. 36
`
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc.,
` IPR2014-00530, 2014 WL 4925282, (Patent Tr. & App. Bd. Sep. 29, 2014) ..... 37
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) ................................. 36, 38
`
`Parthenon Unified Memory Architecture, LLC v. Apple, Inc.,
` Case No. 2:15-cv-00225, Dkt No. 162, .................................................................. 5
`
`Phillips v. AWH Corp.,
` 415 F.3d 1303, (Fed. Cir. 2005) ............................................................................. 4
`
`Teleflex, Inc. v. Ficos N. America Corp.,
` 299 F.3d 1313 (Fed. Cir. 2002) ............................................................................ 37
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`Toyota Motor Corp. v. Cellport Sys., Inc.,
` Case IPR2015-00633, (PTAB Aug. 14, 2015) (Paper 11) ..................................... 4
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`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
` 200 F.3d 795, 803 (Fed. Cir. 1999) ........................................................................ 4
`
`Rules
`35 U.S.C. § 314(a) ..................................................................................................... 1
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`37 C.F.R. § 42.100(b) ................................................................................................ 3
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`37 C.F.R. § 42.5(b) .................................................................................................... 3
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`TABLE OF EXHIBITS
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`Exhibit Description
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`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture, LLC v. Apple, Inc., Case No. 2:15-
`cv-00225 (E.D. Tex.), Dkt No. 162
`Brad Hansen, The Dictionary of Multimedia, 1997
`Excerpts from Stone, H.S., High-Performance Computer
`Architecture, Addison-Wesley Publishing Company, Reading,
`Massachusetts, 1993, ISBN 0-201-52688-3.
`Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`660AV Computers (“Quadra Developer Notes”)
`Institution Decision, IPR2015-01501 (U.S. Pat. No. 7,777,753)
`
`Exhibit
`No.
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`2001
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`2002
`2003
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`2004
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`2005
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`IPR2016-01114
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`I.
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`INTRODUCTION
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
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`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
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`review (“Petition”) filed by Apple, Inc. (“Apple” or “Petitioner”) regarding certain
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`claims of U.S. Patent No. 7,777,753 (“`753 Patent”) because the Petition fails to
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`demonstrate a reasonable likelihood that the Petitioner would prevail as to at least
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`one of the challenged claims, as required under 35 U.S.C. § 314(a).
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`The Petition proposes six grounds challenging claims 1, 2, 4, 7-10, and 12
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`(“challenged claims”) of the `753 Patent. Specifically, the Petitioner contends that:
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`(1) claims 1 and 2 are obvious in view of Bowes, Datasheet, Artieri, and Arimilli
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`(Ground 1); (2) claim 4 is obvious over Bowes in view of Datasheet, Artieri,
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`Arimilli, and Shanley (Ground 2); (3) claim 7 is obvious over Bowes, Datasheet,
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`Artieri, and Christiansen (Ground 3); (4) claims 8 and 10 are obvious over Bowes,
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`Datasheet, Artieri, Christiansen, and Arimilli (Ground 4); (5) claim 9 is obvious over
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`Bowes, Datasheet, Artieri, Christiansen, and Shanley (Ground 5); and (6) claim 12
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`is obvious over Bowes, Datasheet, Artieri, Christiansen, and Gove (Ground 6).
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`Grounds 1 and 3 fail at least because the proposed combinations do not
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`disclose all limitations of independent claims 1 and 7 and dependent claim 2.
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`Specifically, the proposed combinations do not disclose the recited: (i) “idle state;”
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`(ii) decoder receiving data from the main memory corresponding to at least one
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`previously decoded video image; and (iii) an arbiter that controls access to the main
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`memory. By extension, the challenged dependent claims are also not obvious in view
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`of the proposed combinations. Therefore, there is no reasonable likelihood that the
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`Petitioner would prevail with respect to any of the claims challenged in Grounds 1-
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`6. The Petition should be denied because there is no reasonable likelihood that the
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`Petitioner would prevail as to any of the challenged claims.
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`II. THE `753 PATENT
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`The `753 Patent is generally directed to sharing a memory interface between
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`a video decoder and another device contained in an electronic system. `753 Pat. [Ex.
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`1001], Abstract; independent claims 1 and 7. Accordingly, the electronic system
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`includes a bus and a main memory coupled to the bus. Id. at claim 1. The main
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`memory has stored therein data corresponding to video images to be decoded. Id. A
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`video circuit is coupled to the bus and receives data from the main memory
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`corresponding to a video image to be decoded. Id. The video circuit outputs decoded
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`video data corresponding to the current video image to be displayed on a display
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`device. Id. The current video image to be displayed is stored in the main memory.
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`Id. In addition to the video circuit, the electronic system includes another device
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`such as, for example, a processor that is coupled to the main memory. Id. An arbiter
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`circuit is coupled to the processor and the video circuit and is configured to receive
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`requests for access to the main memory from the video circuit and the processor and
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`control access to the main memory. Id.
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`III. CLAIM CONSTRUCTION
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent shall be
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`given its broadest reasonable construction in light of the specification of the patent
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`in which it appears.” However, the `753 Patent expires in August 2016. Accordingly,
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`the `753 Patent will expire before the Board is likely to issue a final written decision
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`as to the patentability of the challenged claims. Therefore, the claim terms are to be
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`construed in accordance with the standard set forth in Phillips.1 37 C.F.R. § 42.5(b);
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`see Toyota Motor Corp. v. Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8-10
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`(PTAB Aug. 14, 2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
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`2012) (“While claims are generally given their broadest possible scope during
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`prosecution, the Board’s review of the claims of an expired patent is similar to that
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`of a district court’s review.”) (internal citation omitted). Under this standard, the
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`                                                            
`1 The construction of the terms and the analysis of the claims set forth herein would
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`have remained the same even if the broadest reasonable interpretation standard was
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`applied.
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`claim terms are given their ordinary and accustomed meaning as understood by one
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`having ordinary skill in the art at the time of the invention in the context of the entire
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`patent, considering intrinsic evidence (the claims, the specification, and the
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`prosecution history), and extrinsic evidence (technical dictionaries, treatises, etc.) to
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`a lesser extent. Phillips v. AWH Corp., 415 F.3d 1303, 1313, 1316-17 (Fed. Cir.
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`2005).
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`Only terms which are in controversy in this proceeding need to be construed,
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`and then only to the extent necessary to resolve the controversy. Vivid Techs., Inc.
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`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Accordingly, no
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`constructions are necessary in this case.2
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`Further, Patent Owner disagrees with Petitioner’s proposed construction for
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`the term “decoder.” Patent Owner requests that to the extent the Board deems a
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`construction necessary, it construe this term consistent with the term’s construction
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`in parallel proceedings. Specifically, Patent Owner requests that the term “decoder”
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`be construed to mean “hardware and/or software that translates data streams into
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`2 The analysis herein would remain unchanged even if the Board were to adopt the
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`Petitioner’s proposed constructions for the terms “decoder,” “video circuit” and
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`“memory interface circuit” or otherwise construe these terms.
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`video or audio information.” See [Ex. 2005 IPR2015-01501, Institution Dec. at 10].
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`This construction is consistent the specification as well as the dictionary definition
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`of the term “decoder”. [`753 Pat., Ex. 1001, 1:66-67 (“a video and/or audio
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`decompression device (hereinafter ‘decoder’)”)]; [Ex. 2002, at 56 (“decoder (n).
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`Any hardware or software system that translates data streams into video or audio
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`information”)].
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`Similarly, with respect to the term “memory interface circuit,” Patent Owner
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`disagrees with Petitioner’s arbitrarily added requirement that the term be limited to
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`“hardware.” In fact, in parallel litigation, the Court construed the term “memory
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`interface” to include “hardware, or hardware with software” and the parties agreed
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`that the term should include “hardware” as well as “hardware with software.” [Ex.
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`2001, Parthenon Unified Memory Architecture, LLC v. Apple, Inc., Case No. 2:15-
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`cv-00225, Dkt No. 162, at 18-22]. Accordingly, Patent Owner requests that to the
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`extent the Board deems a construction necessary, it construe the term consistent with
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`the Court’s construction in parallel litigation.
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`Finally, with respect to the claim terms “bus,” “display device,” “arbiter,” and
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`“arbiter circuit,” unless otherwise noted, the analysis below applies the constructions
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`agreed to by the parties in the parallel litigation. Ex. 1010, pp. 1-2. Those agreed
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`constructions are consistent with the Phillips standard. Moreover, unless explicitly
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`noted below, the validity analysis below remains unchanged even under a broadest
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`reasonable interpretation of these terms.
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`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD THAT ANY CHALLENGED CLAIM IS INVALID
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`1. Ground 1: Bowes, Datasheet, Artieri, and Arimilli (claims 1 and 2)
`The Petition does not establish a reasonable likelihood that any challenged
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`claim is invalid as obvious in view of Bowes, Datasheet, Artieri and Arimilli for at
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`least three reasons: (a) the proposed combination relies on disclosure or teaching that
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`was already before the Office during prosecution of the `753 Patent; (b) Artieri
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`discloses what the `753 Patent identifies as prior art and suffers from the same
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`shortcomings; (c) Bowes, Datasheet, Artieri, and Arimilli, alone or in combination,
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`fail to disclose all limitations of the challenged claims; and (d) one of ordinary skill
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`would not have been motivated to combine Bowes, Artieri and Arimilli as suggested
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`by the Petitioner.
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`a. The MPEG Standard Was Considered During the Prosecution of
`the `753 Patent
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`Artieri is directed to “a system for decoding an image encoded according to
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`an MPEG Standard.” [Ex. 1007, at 2]. The Petitioner relies on Figure 3 of Artieri for
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`the proposition that it would have been obvious to replace the DSP (20) of Bowes
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`with “video decoder circuits specialized for computations dictated by industry-
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`accepted MPEG Standards.” Pet. at 22. The Examiner was well aware of the MPEG
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`Standard during prosecution of the `753 Patent. More than 30 references considered
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`by the Examiner during prosecution of the `753 Patent were directed to the MPEG
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`Standard. `753 Pat. [Ex. 1001], pp. 1-4. In fact, the MPEG Standard was
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`incorporated by reference into the specification of the `753 Patent. Id. at 14:66-15:3.
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`Accordingly, this petition presents substantially the same prior art that was already
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`considered by the Examiner during prosecution of the `753 Patent.
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`b. Artieri Mirrors the Implementation Identified as Prior Art by the
``753 Patent
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`Artieri discloses nothing more than the very same system identified in the
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``753 Patent as prior art. In describing the background of the invention, the `753
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`Patent notes that a typical decoder such as an MPEG decoder (10) contained a
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`video/audio decoding circuit (12/14), a microcontroller (16), and a memory interface
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`(18) coupled to a dedicated memory (22). [`753 Pat., Ex. 1001, 2:21-42]. The `753
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`Patent then highlights the disadvantages of this prior art system:
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`A typical MPEG decoder 10 requires 16 Mbits of memory to operate in
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`the Main Profile at Main Level mode (MP at ML). This typically means
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`that the decoder requires a 2 Mbyte memory. Memory 22 is dedicated
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`to the MPEG decoder 10 and increases the price of adding a decoder 10
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`to the electronic system. In current technology, the cost of this
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`additional dedicated memory 22 can be a significant percentage of the
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`cost of the decoder.
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`Id. at 2:43-51. Figure 1c of the `753 Patent depicts this prior art configuration
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`and is reproduced below side by side with Figure 3 of Artieri.
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`Like the prior art system discussed in the `753 Patent, Figure 3 of Artieri depicts an
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`implementation where the decoder is coupled to and utilizes, a dedicated “image
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`memory 15.” Ex. 1007 at 2 (e.g., “Any MPEG decoder, in particular for standard
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`MPEG 2, generally includes … a memory 15.”); 7 (“According to an embodiment
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`of the present invention, elements that have to exchange data with the image memory
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`are connected to the memory bus by respective write or read buffer memories via
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`the memory bus.”); 12 (“In Figure 3, the elements already included in Figure 1 are
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`designated by the same references;” “A bus, hereafter memory bus MBUS, connects
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`the image memory 15 to the compressed data input bus CDin, to the input of the
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`variable length word decoder (VLD) 10, to the input of the half-pixel filter 14, and
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`to the input of a display controller 18.”).
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`Accordingly, Artieri discloses the very same configuration identified in the
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``753 Patent as prior art and suffers from the same drawbacks. In fact, the `753 Patent
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`is directed to eliminating the “image memory 15” of Artieri – i.e., the decoder’s
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`dedicated memory. See `753 Pat., 5:47-51 (“An advantage of the present invention
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`is the significant cost reduction due to the fact that the video and/or audio
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`decompression and/or compression device does not need its own dedicated memory
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`but can share a memory with another device and still operate in real time”).
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`c. The combination of Bowes, Datasheet, Artieri and Arimilli does not
`disclose every element of claims 1 and 2 of the `753 Patent
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`The proposed combination does not disclose “each and every” claim
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`limitation. See, e.g., In re Wilson, 424 F.2d 1382, 1385 (CCPA 1970) (“All words in
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`a claim must be considered in judging the patentability of that claim against the prior
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`art”).
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`i. The proposed combination does not disclose “providing access
`to the main memory for a request for access to the main memory
`when the arbiter circuit is in an idle state” [claim 1]
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`The Petitioner first relies on Bowes with respect to this limitation. [Pet. at 36].
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`However, Bowes does not disclose this limitation because the arbiter of Bowes does
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`not have an “idle state.” The `753 Patent discloses an arbiter which has three states,
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`one of which is the idle state. [`753 Pat., 13:4-6]. In the idle state, “there is no device
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`accessing the memory and there are no requests to access the memory.” [`753 Pat.,
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`13:4-6]. Bowes does not disclose such an idle state. Instead, in Bowes, “the state of
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`the memory bus assignment defaults to the CPU and remains parked on the CPU
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`until other resources request the memory bus.” [Bowes, 8:30-33]. Accordingly, in
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`Bowes, even if there are no requests to access the memory, the CPU is given access
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`to the memory. Therefore, the arbiter of Bowes does not have an “idle state” in which
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`no device accesses the memory. Id.
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`The use of the recited “idle state” is beneficial compared to the arbitration
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`scheme of Bowes. A POSA would understand that the memory arbiter of the `753
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`Patent being in an “idle state” allows for bus traffic that does not require memory
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`access to occur in an unimpeded fashion. As an example, a video decoder could
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`receive data from a peripheral device such as a DVD drive directly via the bus while
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`the memory arbiter was in the “idle state.” Thus, a POSA would appreciate that the
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`“idle state” of the `753 Patent aids in ensuring that no device monopolizes the bus
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`starving the other devices. [`753 Pat., 5:66-4:5]. In contrast, the Bowes bus arbiter
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`would not allow such bus traffic to occur until such time that the statically fixed
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`priority schedule according to the Bowes arbiter state diagram allows a device to
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`control the bus for a “time slice” period. The Bowes bus arbiter causes the bus to be
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`monopolized during the “time slice” period that the bus is assigned to a particular
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`bus master. [Bowes Pat., 8:23-27; 8:45-56; 9:11-15; FIG. 3]. Moreover, the “default
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`state” of Bowes where “the memory bus assignment defaults to the CPU and remains
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`parked on the CPU” [Bowes, 8:30-33] cannot be conflated with the idle state recited
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`in the `753 Patent because the only permissible bus transactions allowed by the
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`Bowes “default state” are those initiated by the CPU whereas the idle state of the
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``753 Patent would allow for bus transactions to be initiated from either a first device
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`or a decoder.
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`The Petitioner then makes a conclusory statement that this limitation would
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`have been obvious in view of a table in Arimilli. [Pet. at 37]. The Petitioner does not
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`identify where in the table of Arimilli this limitation is disclosed. More specifically,
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`the Petitioner has not identified any disclosure in Arimilli of the “idle state” as
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`disclosed in the `753 Patent – namely, one where “there is no device accessing the
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`memory and there are no requests to access the memory.” [`753 Pat., 13:4-6].
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`Moreover, even if Arimilli did disclose an idle state (which it does not), a
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`POSA would not have been motivated to modify the arbitration scheme of Bowes in
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`light of Arimilli. In Bowes, the MCA (200) is coupled to the memory bus (110) and
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`contains both the memory controller circuitry and the bus arbiter. [Bowes, Ex. 1005;
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`6:44-52; FIG 2]. Furthermore, when one of the four potential bus masters of Bowes
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`requests exclusive use of the memory bus (110), that resource propagates a bus
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`request signal over the memory bus (110) to the MCA (200). [Bowes, Ex. 1005;
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`7:64-8:3] (emphasis added). In contrast in Arimilli, the System Controller (130) is
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`responsible for receiving all bus requests via dedicated point-to-point unidirectional
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`or bidirectional lines. [Arimilli, Ex. 1008, FIG. 1; 3:53-64; 4:3-6; 5:5-9] (emphasis
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`added). Arimilli’s System Controller (130) is thus enabled to receive packets of
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`requests from the potential bus masters via these dedicated lines that are distinct and
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`separate from the bus resource (108) that is being arbitrated and it may receive these
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`packets of requests in a concurrent manner. [Arimilli, Ex. 1008, 2:23-28; 4:3-14].
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`Accordingly, in Arimilli the potential bus masters can support a “private”
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`communication protocol between the various bus devices and system controller
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`(130). [Arimilli, Ex. 1008; 4:10-14]. The Arimilli bus arbitration method requires
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`the potential bus masters to have the capability to encode and formulate packets of
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`bus requests and to furthermore communicate these requests over dedicated point-
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`to-point couplings with the Arimilli System Controller (130) wherein these
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`dedicated point-to-point couplings are separate and distinct from the bus that is being
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`arbitrated. This “topology is capable of supporting totally independent and
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`concurrent address and data bus requests and address and data bus grants;” “provides
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`for system scalability without affecting the request-to-grant speed;” and “is capable
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`of supporting ‘private’ communication protocol between various bus devices and
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`system controller 130.” [Arimilli, 4:6-14]. This design is wholly different from
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`Bowes where the bus requests are propagated over the memory bus (110) itself.
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`[Bowes, Ex. 1005; 7:64-8:3]. In fact, Bowes’ configuration would not offer the
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`benefits enumerated in Arimilli. [Arimilli, 4:6-14]. For at least this reason, a POSA
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`would not have been motivated to combine Arimilli and Bowes because the
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`proposed arbitration scheme in Arimilli is incompatible with Bowes and the
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`proposed combination would render the system inoperable.
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`U.S. Patent No. 7,777,753
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`Moreover, a POSA would understand that Bowes is directed to a single digital
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`computer architecture in which subsystems such as an I/O interface and a NuBus
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`controller share a common memory bus and support real-time applications such as
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`isochronous processing. [Bowes, Ex. 1005; 1:18-22; 2:63-3:2]. In contrast, Arimilli
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`is directed to data processing systems and, in particular to a system and method for
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`intelligent communication of bus requests and bus grants within a data processing
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`system. [Arimilli, Ex. 1008; 1:41-44]. For this reason, incorporation of the Arimilli
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`arbitration method and system into a Bowes digital computer architecture would
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`require undue experimentation that would at least involve complete redesign and
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`implementation of the potential bus masters such as the I/O interfaces and NuBus
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`controllers to enable them to support intelligent communications processing and to
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`further support a private and dedicated point-to-point coupling with the Arimilli
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`System Controller (130). Such redesign is significant and departs from the system
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`architecture contemplated by Bowes. [Bowes, Ex. 1005; FIG. 2]. Moreover a POSA
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`would recognize that even if such undue experimentation were undertaken, the
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`resulting system will be inoperable.
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`ii. The proposed combination does not disclose wherein the
`video circuit is further configured to receive data from the
`main memory corresponding to at least one previously
`decoded video image [claim 2]
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`Figure 1c of the `753 Patent depicts a system having a decoder in accordance
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`with the prior art.
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`The system includes a number of components that are connected to a
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`peripheral bus (170) via interfaces. [`753 Pat., 2:56-63]. A Central Processing Unit
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`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
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`circuit (146) enabling the main memory (168) of the system to be shared between
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`the CPU (152) and other peripherals that may require it. [`753 Pat., 2:64-67].
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`Typically, one of the peripherals connected to the peripheral bus (170) as a master
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`is a decoder (10). [`753 Pat., 3:1-3]. The decoder (10) receives encoded or
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`compressed data from a source peripheral (22) and decodes that data. For instance,
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`if the data to be decoded is video image data, the decoder then directs the decoded
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`video images to a video controller (120) for display. [`753 Pat., 3:3-14].
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`Traditionally, the decoder (10) included its own dedicated memory (22) which
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`was divided into three image area buffers (M1, M2, M3) and a Compressed Data
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`Buffer (CDB) and the compressed image to be decoded was stored in the CDB
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`before it was decoded. [`753 Pat., 3:14-19]. Typically, the decoding of images under
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`the MPEG Standard involves processing of “I”, “P” and “B” frames. “I” frames are
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`so called “intra” image frames whose compressed data directly corresponds to an
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`actual image. [`753 Pat., 3:31-32]. “P” frames are so called “predicted” image frames
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`the construction of which uses pixel blocks of a previously decoded image frame.
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`[`753 Pat., 3:23-25]. Finally, “B” frames are so called “bidirectional” image frames
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`the construction of which uses pixel blocks from two previously decoded images.
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`[`753 Pat., 3:26-28]. Accordingly, the “I” and “P” image frames are used to
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`reconstruct subsequent “P” and “B” frames while “B” frames are not used to
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`reconstruct subsequent image frames. [`753 Pat., 3:28-30].
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`Figure 1c depicts how a prior art decoder (10) uses the buffers M1, M2, and
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`M3 of its dedicated memory (22) during the decoding process. [`753 Pat., 3:20-22;
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`3:31-50]. Accordingly, in prior art systems, although the system included a main
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`memory (168) which the decoder (10) could access via the peripheral bus (170), the
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`decoder (10) utilized its local dedicated memory (22) not the main memory (168)
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`when decoding an image. Specifically, an image to be decoded was stored in the
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`CDB of the dedicated memory (22). The decoder (10) then received the image to be
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`decoded from the CDB in its dedicated memory (22). The decoder (10) also received
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`a previously decoded image (i.e., an “I” image frame or a “P” image frame) from the
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`buffers (M1, M2, M3) in its dedicated memory (22). The decoder (10) then used the
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`previously decoded image (i.e., the “I” or “P” image frame) to decode the image to
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`be decoded using, for example, the MPEG decoding standard. The use of this
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`dedicated memory (22) allowed the decoder (10) to decode a compressed image
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`without having to access the main memory and avoided dropping image frames
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`while preserving the available bandwidth on the peripheral bus (170). [`753 Pat.,
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`3:60-4:48].
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`The `753 Patent discloses an improved system which allows the decoder and
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`a first device (e.g., a CPU) to share the main system memory when decoding an
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`image and eliminates the need for a dedicated memory for the decoder.
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`Figure 4 of the `753 Patent depicts an embodiment of the claimed invention
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`where the decoder/encoder (80) shares the main memory (168) with other peripheral
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`devices (e.g., the CPU (152)). [`753 Pat., 10:14-17]. As shown in Figure 4, the
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`decoder/encoder (80) does not have a dedicated memory and instead uses a region
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`(22’) of the main memory (168) of the system for the decoding process. [`753 Pat.,
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`10:24-26]. The region (22’) of the main memory (168) includes a Compressed Data
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`Buffer (CDB) into which the image source (122) writes a compressed image (i.e., an
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`image to be decoded) and two image buffers M1, and M2 associated with “I” and
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`“P” image frames (i.e., previously decoded images). [`753 Pat., 10:27-30]. The third
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`buffer (M3) used in dedicated memory of prior art decoders has been eliminated and
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`the “B” frames which are not used to decode other images are directly supplied to
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`the display adapter (120) as they are being decoded. [`753 Pat., 10:30-33].
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`Accordingly, in the improved system of the `753 Patent an image to be
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`decoded is directed from the source (122) to the CDB in the main memory (168).
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`[`753 Pat., 10:34-36]. This image to be decoded is transferred from the CDB in the
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`main memory (168) to the decoder/encoder (80) over the peripheral bus (170) and is
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`decoded by the decoder. [`753 Pat., 10:36-37]. If the decoded image is an “I” image
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`frame or a “P” image frame, the decoder/encoder (80) retransmits the decoded image
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`to buffers M1 and M2 in the main memory (168). [`753 Pat., 10:37-39]. These “I”
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`and “P” image frames may then be transmitted from the buffers M1 and M2 in the
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`main memory (168) back to the deco