Paper No.
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________________
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`
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`Apple Inc.,
`Petitioner,
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`v.
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`Parthenon Unified Memory Architecture LLC,
`Patent Owner
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`_____________________
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`
`
`Case IPR2016-01114
`Patent No. 7,777,753
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`_____________________
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`PETITIONER’S REPLY
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`Apple Inc.,
`Petitioner,
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-01114
`Patent No. 7,777,753
`
`_____________________
`
`
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`PETITIONER’S REPLY
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`I.
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`II.
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`
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`TABLE OF CONTENTS
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`Introduction ...................................................................................................... 1
`
`Challenge #3 (Bowes, Datasheet, Artieri, and Christiansen)
`Teaches or Suggests Each and Every Limitation of Claim 7 in
`Combination .................................................................................................... 3
`
`A.
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`B.
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`C.
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`D.
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`E.
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`The Prior Art Teaches an “arbiter included in the
`memory interface circuit of the decoder.” ............................................. 4
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`Patent Owner’s “in the path to memory” Argument is
`Unpersuasive ......................................................................................... 5
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`The Evidence Confirms that Bowes’ Arbiter is included
`in the Memory Interface Circuit of Bowes’ DSP .................................. 7
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`the Adopted Claim
`Though Not Required by
`Construction, Bowes Suggests that Arbiter Logic Can Be
`Included in Other Logic ...................................................................... 10
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`Christiansen Also Suggests Co-Location of Arbitration
`Logic with the DSP. ............................................................................ 15
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`III. The combination of Bowes, Datasheet, Artieri, Christiansen,
`and Arimilli renders claims 8 and 10 obvious. .............................................. 17
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`IV. The combination of Bowes, Datasheet, Artieri, and Christiansen
`renders claim 9 obvious. ................................................................................ 17
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`V.
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`The combination of Bowes, Datasheet, Artieri, Christiansen,
`and Gove renders claim 12 obvious. .............................................................. 17
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`VI. Conclusion ..................................................................................................... 18
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`Petitioner’s Updated Exhibit List
`June 9, 2017
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`Ex. 1007
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`Ex. 1010
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`Exhibit
`Number
`Ex. 1001 U.S. Patent No. 7,777,753
`Ex. 1002
`Prosecution History of U.S. Patent No. 7,777,753
`Ex. 1003 Declaration of Robert Colwell, Ph.D., Under 37 C.F.R. §1.68
`Ex. 1004 Curriculum Vitae of Robert Colwell, Ph.D.
`Ex. 1005 U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”)
`Ex. 1006
`“AT&T DSP3210 Digital Signal Processor The Multimedia
`Solution” Data Sheet March 1993 (“Datasheet”)
`Published European Patent Application EP 0626653 A1 naming
`Artieri, together with English translation and affidavit attesting to the
`accuracy of the translation (“Artieri”)
`Ex. 1008 U.S. Patent No. 6,029,217 to Arimilli et al. (“Arimilli”)
`Ex. 1009 R. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip”, IEEE 1994 (“Gove”)
`T. Shanley et al., “PCI System Architecture”, Addison–Wesley
`Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”)
`Ex. 1011 U.S. Patent No. 5,787,264 to Christiansen et al. (“Christiansen”)
`Ex. 1012 U.S. Patent No. 5,473,380 to Tahara (“Tahara”)
`Ex. 1013 Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd. et al.,
`No. 2:14-CV-00902 (E.D. Tex.)
`File History of U.S. Patent No. 5,752,073
`“ISO/IED 11172-2:1993 Information technology – Coding of
`moving pictures and associated audio for digital storage media at up
`to about 1,5Mbits/s- Part 2: Video;” 1st ed., August 1, 1993 (“MPEG
`Standard”)
`Texas Instruments, Inc., Houston, TX, “TMS320C8x System Level
`Synopsis,” (1995) (Literature Ref. SPRU113B) (“TMS”)
`“Pentium and Pentium Pro Processors and Related Products”, ISBN
`1-55512-265-5
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`Ex. 1014
`Ex. 1015
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`Ex. 1016
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`Ex. 1017
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`Petitioner’s Reply
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`Ex. 1018
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`Joint Claim Construction and Prehearing Statement, Parthenon
`Unified Memory Architecture LLC v. Apple Inc., case no. 2:15-cv-
`632-JRG-RSP (Feb. 16, 2016, E.D. Tex.)
`Ex. 1019 VESA Unified Memory Architecture Hardware Specifications
`Proposal, Version 1.0p
`Institution Decision, IPR2015-01501 (U.S. Patent No. 7,777,753)
`Ex. 1020
`Ex. 1021 Bader Declaration (including Appendix A & B)
`Ex. 1022
`Institution Decision, IPR2015-01502 (U.S. Patent No. 7,542,045)
`Joint Claim Construction Chart, Parthenon Unified Memory
`Ex. 1023
`Architecture LLC v. Apple Inc., case no. 2:15-cv-632-JRG-RSP
`(April 4, 2016, E.D. Tex.)
`Ex. 1024 Microprocessor Report, MPEG Choices for PCs Abound (July 31,
`1995).
`Ex. 1025 Declaration of Yakov Zolotorev in Support of Motion for Pro Hac
`Vice Admission
`Transcript of Teleconference Hearing, IPR2016-01114, IPR2016-
`01118 and IPR2016-01134 (February 27, 2017)
`Ex. 1027 Deposition Testimony of Mitchell A. Thornton, Ph.D., P.E. (May 22,
`2017)
`Ex. 1028 Reply Declaration of Robert Colwell, Ph.D., Under 37 C.F.R. §1.68
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`Ex. 1026
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`iii
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`I.
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`Introduction
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`The Petition and trial record provide detailed reasons why a person of skill
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`in the art (“POSITA”) would have understood Bowes and Christiansen to teach or
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`suggest an arbiter included in the “memory interface circuit” of the decoder, as
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`recited in claims 7-10 and 12 of the ’753 Patent. None of Patent Owner’s
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`arguments overcome the express teachings of Bowes and Christiansen, and Patent
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`Owner’s Response does not provide a persuasive rebuttal of Petitioner’s
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`unpatentability showing. Accordingly, the Board should confirm unpatentability
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`of claims 7-10 and 12 in its Final Written Decision.
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`The record shows that a POSITA would have understood that bus arbitration
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`unit logic 240 in Bowes’ MCA 200 controls whether the DSP 20 or another agent
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`has access to shared memory via the memory bus. See, e.g., Ex. 1003, p. 110.
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`Accordingly, that arbiter logic and its associated request/grant signaling paths are
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`“hardware, including signaling paths to or from … an arbiter, to coordinate
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`communication via a memory bus,” and are in the “memory interface circuit”1 of
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`1 See Institution Decision (Paper 7), pp. 13-14 (adopting construction of
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`“memory interface circuit” to mean “hardware, including signaling paths to or
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`from a competing device or an arbiter, to coordinate communication via a
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`memory bus”).
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`1
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`the decoder as claimed.
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`Petitioner’s Reply
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`Patent Owner’s opposition is to argue that Bowes’ arbitration logic is not
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`included in the “memory interface circuit” of Bowes’ DSP 20. Specifically, Patent
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`Owner builds and argues a “part of [the] path to memory” strawman (see PO
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`Response, p. 4) in an effort to distract from the circuits and signal paths that are
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`actually in Bowes’ “memory interface circuit.” But Patent Owner’s attempt to
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`import limitations into the claim is improper, and is, in any case, inconsistent with
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`a POSITA’s understanding of the circuits and signal paths actually relied upon by
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`Petitioner in its analysis and instituted grounds. Patent Owner’s arguments are
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`unpersuasive.
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`Though Patent Owner has avoided direct advocacy of a claim construction
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`that would require the claimed arbiter to be physically co-located within a decoder,
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`as backup position, Patent Owner now seems to insinuate a physical co-location
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`requirement through its packaging of deposition testimony and through its expert.
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`See PO Response, p. 5 (“POS[IT]A would not co-locate the arbiter with DSP 20”)
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`(citing Ex. 2009, Thornton Dec.). But Petitioner’s instituted grounds include
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`Christiansen, which expressly teaches that an arbiter can be located anywhere
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`within a system, and which suggests colocation of an arbiter and a video device.
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`See Ex. 1027, 58:14-20; Ex. 1011, 5:2-6. Furthermore, the record provides
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`substantial evidence that a POSITA would consider co-locating the arbitration
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`2
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`logic with the DSP and in particular, the memory bus interface circuit of the DSP.
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`Ex. 1003 ¶¶ 141, 146–147; Ex. 1028, ¶¶ 16-24. Accordingly, even if claim 7 were
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`somehow construed to require arbiter logic to physically reside within an arbitrary
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`block or particular packaged integrated circuit (rather than simply in the memory
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`interface circuit of the decoder) such a variation is obvious over the prior art and in
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`view of the record evidence as originally set forth in the Petition. See, e.g.,
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`Petition, p. 57; see also Institution Decision, p. 36 (agreeing in substance).
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`As detailed below, neither Patent Owner’s “part of [the] path to memory”
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`strawman, nor its insinuation of a physical co-location requirement are persuasive,
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`and the Board should confirm the unpatentability of claims 7-10 and 12 in its Final
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`Written Decision.
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`II. Challenge #32 (Bowes, Datasheet, Artieri, and Christiansen) Teaches or
`Suggests Each and Every Limitation of Claim 7 in Combination
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`Patent Owner’s sole opposition to the grounds on which trial was instituted
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`is to allege, relative to a single limitation of claim 7, that Bowes, Datasheet, Artieri,
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`and Christiansen (in combination) fail to disclose “an arbiter included in the
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`2 Challenges #1 and #2 (as applied to claims 1, 2 and 4) were mooted by the
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`intervening finality of unpatentability determinations of the Board in IPR2015-
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`01501. See Partial Termination, Paper 32, IPR2016-01114 (March 17, 2017).
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`IPR2016-01114 (Patent No. 7,777,753)
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`memory interface circuit of the decoder.” No other opposition arguments are
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`advanced (see Ex. 1028, 8:21-9:18) and, accordingly, argument as to other
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`limitations is waived.
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`A. The Prior Art Teaches an “arbiter included in the memory
`interface circuit of the decoder.”
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`Bowes’ DSP has a “memory interface circuit” which includes signal paths
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`used by the DSP to coordinate access to the memory bus, including “control lines
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`for such things as bus requests and bus granting signals.” Petition, pp. 52-53. In
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`addition to the control lines, Bowes’ “arbiter logic is included in the memory
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`interface circuit of DSP 20.” Petition, pp. 55-56.
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`As explained by Dr. Colwell, Bowes’ arbiter, together with the signaling
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`paths to and from the arbiter, are included in the memory interface circuit because
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`those elements are “hardware that coordinates communication between the DSP
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`and memory 14 … ” Petition, p. 56, see also Ex. 1003, ¶ 142. As further
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`explained by Dr. Colwell, to perform a transaction with the main memory, the DSP
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`must “(first) interface with the bus arbitration unit logic by sending a request signal
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`on the control line (DSPREQ) and receiving a bus grant signal on the control line
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`(DSPBGN).” Ex. 1003, ¶ 142. Accordingly, the arbiter is part of the “hardware,
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`including signaling paths to or from a competing device or an arbiter, to coordinate
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`communication via a memory bus,” consistent with the Board’s adopted
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`4
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`Petitioner’s Reply
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`construction of “memory interface circuit.”
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`In addition, as the Board agreed in the Institution Decision, Christiansen
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`“explicitly teaches that an arbiter can be located anywhere in the system” which
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`includes “co-locating the arbitration logic with the DSP.” Institution Decision,
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`p. 36, citing Petition, p. 57, Ex. 1003, ¶¶ 141, 146-147. Even if the claim were
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`construed to require the arbiter logic to “physically reside in some arbitrary …
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`packaged integrated circuit implementation of a DSP” (which it has not been), the
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`Board agreed that such matters were well understood as matters of design choice.
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`Institution Decision, p. 36, citing Petition, pp. 56-57. Those conclusions remain
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`valid, and the Board should confirm in its Final Written Decision that claim 7, and
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`the challenged claims which depend therefrom, are all unpatentable.
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`B.
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`Patent Owner’s “in the path to memory” Argument is
`Unpersuasive
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`Patent Owner argues that Bowes does not teach “an arbiter included in the
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`memory interface circuit of the decoder,” as is recited in claim 7 of the ’753 patent,
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`because Bowes’ MCA 200 “is not part of DSP 20’s path to the memory.” See PO
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`Response, p. 4. Patent Owner’s expert parrots this statement without providing
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`any other analysis. See Ex. 2009, ¶ 36. For the reasons detailed below, Patent
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`Owner’s argument is both unpersuasive and incorrect.
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`First, Patent Owner improperly imports limitations into the claim by
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`suggesting that, unless arbiter logic is in “DSP 20’s path to memory,” it cannot be
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`part of a memory interface circuit. See PO Response, pp. 4-5. The claims do not
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`recite an “in the path to memory” limitation. Rather, claim 7 simply requires that
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`the arbiter be included in the memory interface circuit. Second, leaving aside the
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`impropriety of importing limitations, Patent Owner myopically focuses on I/O
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`driver paths to memory via data/address lines of the memory bus (see id.), while
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`ignoring the very control paths (request/grant lines or signaling paths)
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`encompassed by the Board’s adopted construction of “memory interface circuit.”
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`Specifically, a POSITA would have understood that, in a system such as
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`Bowes (or Bowes in view of Datasheet, Artieri and Christiansen, as in the instituted
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`grounds), having an arbiter which receives requests and grants access to a shared
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`memory bus, the arbiter is unquestionably in the coordination or control “path to
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`memory” of devices which seek to access that shared memory. See Ex. 1028, ¶ 10.
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`This conclusion is reinforced by the construction of “memory interface circuit” as
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`hardware, including [the] signaling paths to or from a competing device or an
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`arbiter, to coordinate communication via the memory bus. Bowes teaches an
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`“arbitration technique … which allows a DSP to … share the memory bus
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`resources with the other potential bus masters on the memory bus.” See Ex. 1005,
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`4:49-55. Thus, before accessing the memory bus (and the memory), DSP 20
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`coordinates its use of the shared memory bus based on request/grant signaling via a
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`circuit path that includes, and indeed goes through, the arbiter. See Ex. 1028, ¶ 11.
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`Bowes’ arbiter is therefore in the path to memory in the sense that matters under
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`the Board’s adopted construction of the term “memory interface circuit.”
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`Accordingly, Dr. Thornton’s statement that “MCA 200 is not part of
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`DSP 20’s path to the memory” is incorrect, and the implication that Patent Owner
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`wishes to Board to draw, namely that MCA 200 is somehow not in the memory
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`interface circuit of Bowes’ DSP 20, is unsound. Simply stated, MCA 200 is within
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`DSP 20’s path to the memory, and the arbitration logic within MCA 200 is in the
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`memory interface circuit of DSP 20, as Dr. Colwell previously testified.
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`C. The Evidence Confirms that Bowes’ Arbiter is included in the
`Memory Interface Circuit of Bowes’ DSP
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`Dr. Colwell explained in his direct testimony that the “control lines and
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`arbitration logic of Bowes are included in the memory interface circuit of the DSP
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`20.” Ex. 1003, ¶ 144. “MCA 200 is coupled to the request/grant signal paths
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`to/from the DSP 20 … and used to coordinate the DSP’s communication via the
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`memory bus.” Id. Indeed, during cross-examination, Dr. Colwell testified that
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`MCA 200’s job is to “control the shared [memory bus] resource among all the
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`agents that need it, so it has to talk to each one accepting requests and sending out
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`grants.” Ex. 2010, 43:15-18. Dr. Thornton agrees:
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`Petitioner’s Reply
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`Ex. 1027, 38:5-10.
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`Thus, in Bowes, the DSP’s “memory interface circuit” can be understood to
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`include: (1) the portion of the DSP which supplies bus request signals and receives
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`bus grant signals; (2) the signaling path from the DSP to the bus arbitration unit
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`logic (which carries the bus request signal); (3) the bus arbitration unit logic itself
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`(which receives the bus request signal and supplies a bus grant signal); and (4) the
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`signaling path from the bus arbitration unit logic back to the DSP (which carries
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`the bus grant signal), all consistent with the Board’s claim construction. Ex. 1028,
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`¶ 12; see also Ex. 1027, 55:8-17.
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`Nonetheless, Patent Owner seeks to distract from this apparent agreement on
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`the actual operation of Bowes arbiter, MCA 200, and on the signaling paths by
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`which DSP 20’s access to shared memory is coordinated or controlled. Instead,
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`Patent Owner seeks to sow confusion as to where MCA 200 resides and how and
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`whether it is part of DSP 20’s path to memory. Patent Owner’s arguments, though,
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`are without merit, as Dr. Colwell re-emphasizes:
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`Petitioner’s Reply
`IPR2016-01114 (Patent No. 7,777,753)
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`“It remains my opinion that the bus arbitration logic 240 of Bowes’
`MCA 200 is coupled into the memory interface circuit of DSP 20 via
`DSPREQ and DSPBGN signal paths by which bus requests are made
`by DSP 20 and corresponding bus grants are received from MCA 200.
`I explained this in my original declaration, and I reemphasize it here.
`The depictions of DSPREQ and DSPBGN signals as inputs to and
`outputs from bus arbitration unit logic 240 of MCA 200 of Bowes,
`together with (i) corresponding logic specifications (dspbr_l and
`dspbg) of VERILOG code reproduced in Appendix A of Bowes for
`an ASIC
`implementation and (ii) the states reflected
`in
`the
`corresponding
`state
`transition diagram
`(Bowes Fig. 3), are
`corroborative.
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`Furthermore, the DSP3210 Datasheet itself lists the Bus Request
`(BRN) and Bus Grant (BGN) pins by which arbitration unit logic 240
`of MCA 200 would be understood by a POSITA to be coupled to
`DSP3210 (an exemplary embodiment of DSP 20 in Bowes) and into
`its 32-bit bus-master interface to system memory.
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`Ex. 1028, ¶¶ 13-14 (internal citations omitted).
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`Accordingly, Bowes’ arbitration logic in MCA 200, which is the component
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`that receives the request signal carried over the DSPREQ signal path from a bus
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`request pin (BRN) of DSP 20, and that (consistent with the VERILOG code and
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`arbitration state transitions described by Bowes) supplies the grant signal carried
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`over the DSPBGN signaling path to a bus grant pin (BGN) of DSP 20, would be
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`Petitioner’s Reply
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`understood by a POSITA to be “included in the memory interface circuit of the
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`decoder” as recited in claim 7. See Ex. 1028, ¶ 15. Bowes teaches this claim
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`feature, and the instituted Bowes, Datasheet, Artieri, and Christiansen grounds
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`render obvious claims 7-10 and 12.
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`D. Though Not Required by the Adopted Claim Construction, Bowes
`Suggests that Arbiter Logic Can Be Included in Other Logic
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`As also taught by Bowes, “[i]n an alternative embodiment, the arbiter logic
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`could be designed in some other form of logic.” Ex. 1005, 6:46-54, Ex. 1003,
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`p. 107. One of the other “other form[s] of logic” taught by Bowes includes the
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`DSP 20. Ex. 1003, p. 107; see also Ex. 1028, ¶ 17. Thus, a POSITA would have
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`understood Bowes to have suggested the inclusion of the arbiter logic in some other
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`logic block, such as DSP 20 (a decoder). See id.
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`None of Patent Owner’s arguments change that teaching. Yet undeterred,
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`Patent Owner attempts misdirection through various citations of Bowes, alleging
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`that the DSP is bandwidth limited and its resources must be “reserved exclusively
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`for data and control traffic dedicated to the video decoding process.” But Patent
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`Owner’s arguments are without merit, because colocating the arbiter with the DSP
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`20 would not have any meaningful effect on the DSP’s available resources,
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`including bus and/or memory interface bandwidth available to the DSP or DSP
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`processing power. Ex. 1028, ¶ 18.
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`Indeed, Patent Owner’s argument is predicated on taking Dr. Colwell’s
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`statements out of context and arguing that locating the arbitration in the DSP 20
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`would “take up some of the chip’s resources.” See PO Response, pp. 5-7; compare
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`Ex. 2010, 58:10-59:18 (Dr. Colwell describing “a few gates … [and] pins”
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`required by the arbiter). From this exaggerated premise, Patent Owner implies that
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`memory bus bandwidth would be consumed by an arbiter relocated to physically
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`reside in an integrated circuit that also implements Bowes’ DSP. But Dr. Colwell
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`never asserted that relocating the arbiter to the DSP would consume bandwidth.
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`The only “resources” Dr. Colwell mentioned were a “few gates” and “pins.” See
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`Ex. 2010, 58:23-59:18. Indeed, Dr. Colwell specifically testified that MCA 200
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`does not use memory bus bandwidth:
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`Ex. 2010, 43:4-5; see also Ex. 1028, ¶ 19. Dr. Thornton agreed that it would be
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`“the most likely circumstance[]” that an arbiter would not “take up memory bus
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`bandwidth itself.” Ex. 1027, 40:14-20.
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`Dr. Thornton also confirmed that a POSITA could put “any number of
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`disparate circuits” like an arbiter and a DSP “on a chip as long as there’s enough
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`transistors and routing real estate.” Ex. 1027, 43:2-8 (speaking in terms of
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`transistors and routing for signal paths, rather than gates and pins). With reference
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`to the pins and gates that might be implicated in a colocation, Dr. Colwell confirms
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`that a POSITA would expect an integrated circuit implementation of Bowes arbiter
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`logic to employ perhaps one 4-bit counter, 100 logic gates and 6 pins (two pins for
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`each bus master (CPU, I/O bus, NuBus)). Ex. 1028, ¶ 20. Relative to an
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`integrated circuit of the class represented by DSP 20, neither an increase of 100
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`gates, nor inclusion of a counter, nor an increase of 6 pins would have been viewed
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`by a POSITA as a significant resource challenge. Id. Thus, were MCA 200’s
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`functions included in the DSP 20 (or more precisely, in the decoder taught by the
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`Bowes, Datasheet, Artieri, and Christiansen combination on which trial was
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`instituted), there would be no effect on the ability of DSP 20 (or more precisely,
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`the decoder) to access the memory bus bandwidth it requires.
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`Furthermore, Dr. Colwell specified that he did not “see a lot of overlap
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`between … the arbitration function” and the “agent … you’re trying to incorporate
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`the arbiter into” (that is, the DSP or decoder). Ex. 2010, 59:1-18. Accordingly,
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`any resources consumed by arbitration logic would not negatively impact the agent
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`(e.g., DSP 20). Ex. 1028, ¶ 21. Thus, there is no basis, whether in Bowes or Dr.
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`Colwell’s testimony, to suggest that colocating the arbiter logic in the DSP or
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`decoder would affect performance of the DSP or decoder. Even if Bowes was
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`“optimized” to support the DSP as Patent Owner alleges, integration of arbitration
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`Petitioner’s Reply
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`logic with “other logic” such as the DSP (as suggested by Bowes), would not have
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`any significant effect on the DSP’s performance, as there would be no significant
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`resource competition between the arbitration logic and the DSP. Ex. 1028, ¶ 21.
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`In short, Patent Owner’s hypothecated resource concern is not a reason for a
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`POSITA to ignore Bowes’ teachings.
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`Indeed, Dr. Colwell’s testimony in cross-examination was that the only
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`resource that MCA 200 uses is “electrical current.” Ex. 2010, 43:19–44:3. But
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`whether MCA 200 was included in DSP 20 or not, a similar amount of electrical
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`current would be used, and neither usage of such electrical current nor any
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`marginal increase in heat dissipation requirements would affect the DSP 20’s
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`processing power or its ability to access the bus interface (as Patent Owner alleges)
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`or dissuade a POSITA from integrating integration of arbitration logic with “other
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`logic” such as DSP 20. Ex. 1028, ¶ 22. Bowes never describes a need for
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`“exclusive” resource allocation of the DSP. Id. Patent Owner’s arguments in this
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`regard are unsupported by anything in Bowes itself.
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`In its quest for some colorable resource contention between DSP 20 and
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`MCA 200, Patent Owner asserts that request and grant signals involved in
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`arbitration for memory access are carried over the memory bus itself, implying that
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`arbitration requests/grants would contend for bandwidth of the memory bus. Ex.
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`2009, ¶¶ 37-38. Patent Owner’s argument is despite Bowes’ clear depiction of
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`separate lines for the DSPREQ and DSPBGN signals. Further, as Dr. Colwell
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`indicates, while “control lines for such things as bus requests and bus granting
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`signals and other system level control signals” can be viewed at one level of
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`abstraction (such as in Bowes’ discussion of a top-level overview, see Ex. 1005,
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`Fig. 2, 5:8-20) as provided by the memory bus, at a more detailed implementation
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`level depicted by Bowes itself in FIG. 4, those control lines are more accurately
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`understood by a POSITA to be “separate bus request and bus granting signal lines
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`between the ... devices (e.g., CPU, DSP) and the arbiter.” See Ex. 1003, ¶ 141;
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`Ex. 1028, ¶ 23. Dr. Thornton confirms that the DSPREQ line and DSPBGN line in
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`Bowes’ FIG. 4 are “separate” “control line[s],” not data or address lines (which
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`contradicts his own prior testimony, see Ex. 2009, ¶ 38).3 Ex. 1027, 54:20-23,
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`55:8-17. Thus, bus request and bus grant signals would not affect memory bus
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`bandwidth.
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`A POSITA would have understood that, at the time of the invention, control
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`signals for an arbiter were commonly carried over control lines separate from a
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`memory bus, just as Bowes describes and depicts. Ex. 1005, 5:14-19, FIG. 4; Ex.
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`1003, ¶ 141. Accordingly, Bowes’ arbiter, whether implemented in ASIC form as
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`3 In any event, Christiansen also teaches control lines separate from a memory bus,
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`as Dr. Thornton testified. Ex. 1027, 56:12-16; see also Ex. 1003, ¶ 141.
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`MCA 200 or integrated as part of an integrated circuit implementing DSP 20 or a
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`decoder, would not contend for or degrade data transfer bandwidth of the memory
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`bus.
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`Finally, Patent Owner makes no mention of Gove, which evidences that it
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`was known to “integrate components such as DSP parallel processors … [and]
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`arbiters … onto a single chip.” See Ex. 1003, ¶¶ 84, 145. It is uncontroverted that
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`Gove supplies a “reason to decrease the number of disparate chips present,” thus
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`supporting the conclusion that a POSITA would have found it obvious to co-locate
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`the arbiter logic of Bowes with the DSP.
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`E.
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`Christiansen Also Suggests Co-Location of Arbitration Logic with
`the DSP.
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`Patent Owner argues that a POSITA “would not take Christiansen’s
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`statement at face value” as “certain locations are unsuitable for the arbiter.” But
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`Patent Owner does not elaborate on what locations are unsuitable, nor does its
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`expert provide any insight. Dr. Colwell confirms that Bowes DSP would be a
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`suitable location. Ex. 1028, ¶ 24.
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`Furthermore, Patent Owner fundamentally fails to consider the role of a
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`POSITA; the POSITA is not an automaton, but a person of ordinary creativity, and
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`a person of skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421
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`(2007). A POSITA, reading Christiansen’s teachings, would have experimented
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`and determined that certain locations are suitable for locating the arbitration
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`functions. A POSITA would have considered factors such as those enumerated by
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`Dr. Colwell in his Petition Declaration (see Ex. 1003, ¶ 143), and based on the
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`suggestion of Christiansen that an arbiter could be placed anywhere in a system, a
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`POSITA would have looked to relocate the arbiter into other suitable locations, one
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`of which would have been the DSP 20 of Bowes. Ex. 1028, ¶ 24.
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`As Dr. Colwell explained in his Petition Declaration, in Christiansen, the
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`“arbiter is located within the dashed line that also includes the video input DMA
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`controller 31,” confirming that “providing the arbiter with a video device is one
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`possible location for the arbiter.” Ex. 1003, p. 108. Dr. Thornton agreed that the
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`dotted line in FIG. 2 indicates that the video input DMA controller is “closely
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`coupled at least with the arbiter” and could mean that the two devices are
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`“collocated.” Ex. 1027, 58:11-20.
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`Inclusion of the arbiter in Bowes’ DSP 20 (or, more generally, in the context
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`of the combination on which trial was instituted, in the decoder), as suggested by
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`Christiansen, constitutes a teaching or suggestion of an “arbiter included in the
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`memory interface circuit of the decoder” as recited in claim 7. Thus, for this
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`reason as well, the Board should confirm unpatentability of claim 7.
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`III. The combination of Bowes, Datasheet, Artieri, Christiansen, and
`Arimilli renders claims 8 and 10 obvious.
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`Patent Owner’s sole argument that claims 8 and 10 are not rendered obvious
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`by the instituted Bowes, Datasheet, Artieri, Christiansen, and Arimilli combination
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`is its contention that claim 7 (from which claims 8 and 10 depend) is not rendered
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`obvious by Bowes, Datasheet, Artieri, and Christiansen. See PO Response, pp. 8-
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`9. As discussed above, however, Bowes, Datasheet, Artieri, and Christiansen do in
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`fact render obvious claim 7. Therefore, as set forth in the Petition, the combination
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`of Bowes, Datasheet, Artieri, Christiansen, and Arimilli renders claims 8 and 10
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`obvious.
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`IV. The combination of Bowes, Datasheet, Artieri, and Christiansen renders
`claim 9 obvious.
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`Patent Owner’s sole argument that claim 9 is not rendered obvious by the
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`instituted Bowes, Datasheet, Artieri, and Christiansen combination is its contention
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`that claim 7 (from which claim 9 depends) is not rendered obvious by Bowes,
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`Datasheet, Artieri, and Christiansen. See PO Response, p. 9. As discussed above,
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`however, Bowes, Datasheet, Artieri, and Christiansen do in fact render obvious
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`claim 7. Therefore, as set forth in the Petition, the combination of Bowes,
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`Datasheet, Artieri, and Christiansen renders claim 9 obvious.
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`V. The combination of Bowes, Datasheet, Artieri, Christiansen, and Gove
`renders claim 12 obvious.
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`Patent Owner’s sole argument that claim 12 is not rendered obvious by the
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`instituted Bowes, Datasheet, Artieri, Christiansen, and Gove combination is its
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`contention that claim 7 (from which claim 12 depends) is not rendered obvious by
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`Bowes, Datasheet, Artieri, and Christiansen. See PO Response, pp. 9-10. As
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`discussed above, however, Bowes, Datasheet, Artieri, and Christiansen do in fact
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`render obvious claim 7. Therefore, as set forth in the Petition, the combination of
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`Bowes, Datasheet, Artieri, Christiansen, and Gove renders claim 12 obvious.
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`VI. Conclusion
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`None of PUMA’s opposition arguments withstand scrutiny. For the reasons
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`stated above, and based on the Petition, evidence and record, the Board should find
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`the challenged claims unpatentable.
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`Dated: June 9, 2017
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`Respectfully submitted,
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`/David W. OBrien/
`David W. O’Brien
`Registration No. 40,107
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`IPR2016-01114 (Patent No. 7,777,753)
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`CERTIFICATE OF WORD COUNT
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`Pursuant to 37 C.F.R. § 42.24, the undersigned attorney for the Petitioner,
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`Apple Inc., declares that the argument section of this Reply (Sections I-VI) has a
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`total of 4,010 words, according to the word count tool in Microsoft Word™.
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`/David W. OBrien/
`David W. O’Brien
`Registration No. 40,107
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`Petitioner’s Reply
`IPR2016-01114 (Patent
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