UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-01114
`Patent No. 7,777,753
`
`_____________________
`
`DECLARATION OF ROBERT COLWELL, Ph.D.,
`UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITIONER REPLY
`
`
`
`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-01114
`Patent No. 7,777,753
`
`_____________________
`
`DECLARATION OF ROBERT COLWELL, Ph.D.,
`UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITIONER REPLY
`
`
`
`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`TABLE OF CONTENTS
`
`Introduction ...................................................................................................... 2
`I.
`Claim Construction .......................................................................................... 3
`II.
`III. Challenges #1 and #2 Mooted – Analysis Reaffirmed .................................... 4
`IV. Challenge #3: Claim 7 is Obvious over Bowes, as informed by the
`DSP3210 Data Sheet, in view of Artieri, and further in view of
`Christiansen ..................................................................................................... 4
`A.
`Bowes Teaches an Arbiter (MCA 200) included in the Memory
`Interface Circuit of DSP 20 .................................................................. 5
`A POSITA Would Have Considered Colocating the Arbiter
`with the DSP ....................................................................................... 10
`Patent Owner Misunderstands My Testimony ................................... 15
`C.
`V. Declaration ..................................................................................................... 16
`
`B.
`
`
`
`
`i
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`I.
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`Introduction
`
`I, Robert Colwell, Ph.D., declare:
`
`1.
`
`I am making this declaration at the request of Apple Inc. in the matter
`
`of the Inter Partes Review of U.S. Patent No. 7,777,753 (“the ’753 Patent”) to
`
`Owen et al. I am the Robert Colwell who has previously submitted a declaration
`
`in this proceeding (Ex. 1003). The terms of my engagement, my qualifications,
`
`professional experience and prior testimony, and the legal standards and claim
`
`constructions I am applying were set forth in my previous declarations. I offer this
`
`declaration in reply to the testimony of Prof. Thornton provided in this proceeding
`
`(Ex. 2009). In forming my opinion, I have considered the materials noted in my
`
`previous declarations in these proceedings, as well as the following additional
`
`materials:
`
`(1) Declaration of Mitchell A. Thornton, Ph. D., P.E. (Exhibit 2009); and
`
`(2) Transcript of Deposition of Mitchell A. Thornton, Ph.D., P.E., May
`
`22, 2017 (Exhibit 1027);
`
`(3)
`
`Institution Decision, Paper 7;
`
`together with any other documents specifically referenced herein.
`
`
`
`
`
`–2–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`II. Claim Construction
`
`2.
`
`It is my understanding that in its Institution Decision, the Board has
`
`adopted Petitioner’s construction of the term “memory interface circuit” to mean
`
`“hardware, including signaling paths to or from a competing device or an arbiter,
`
`to coordinate communication via a memory bus.” Institution Decision, Paper 7, p.
`
`13 (emphasis added). I note that Dr. Thornton likewise states, in his declaration,
`
`that he understands that the Board has so construed the term “memory interface
`
`circuit” and that he has used the Board’s construction in his analysis. Ex. 2009, ¶¶
`
`33-34.
`
`3.
`
`For avoidance of doubt, I reaffirm my prior claim construction
`
`analysis of the term “memory interface circuit” (see Ex. 1003, ¶¶ 49-52) and apply
`
`the Board’s adopted construction that a “memory interface circuit” is hardware,
`
`including signaling paths to or from a competing device or an arbiter, to
`
`coordinate communication via a memory bus.
`
`4.
`
`Furthermore, I have applied the Board’s adopted claim construction of
`
`the term “decoder” as hardware and/or software that translates data streams into
`
`video or audio information. Institution Decision, Paper 7, p. 12. The opinions I
`
`expressed in my earlier declaration (Ex. 1003) have not changed in light of the
`
`Board’s adopted claim construction of “decoder.”
`
`
`
`
`
`–3–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
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`
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`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`III. Challenges #1 and #2 Mooted – Analysis Reaffirmed
`
`5.
`
`It is my understanding that, in a separate proceeding, the Board has
`
`confirmed unpatentability of claims 1, 2 and 4 of the ‘753 Patent. It is also my
`
`understanding that claims 1, 2, and 4 of the ’753 Patent are no longer a part of this
`
`proceeding. However, to the extent my prior analysis of claims 1, 2, and 4 is relied
`
`upon in support of the remaining challenges of claims 7-10 and 12 of the ’753
`
`Patent, I reaffirm my prior analysis of grounds #1 and #2 (see, e.g., Ex. 1003, ¶¶
`
`89-131, 135-139, pp. 71-89, 94-95).
`
`IV. Challenge #3: Claim 7 is Obvious over Bowes, as informed by the
`DSP3210 Data Sheet, in view of Artieri, and further in view of
`Christiansen
`
`6.
`
`It remains my opinion that Bowes, as informed by the DSP3210 Data
`
`Sheet, and in view of Artieri and Christiansen, renders obvious claim 7. Ex. 1003,
`
`¶ 140. It also remains my opinion that (i) one of ordinary skill in the art would
`
`have been motivated to combine the teachings of Bowes, DSP3210 Data Sheet,
`
`and Artieri (Ex. 1003, ¶ 148), and (ii) that one of ordinary skill in the art would
`
`have been motivated to further combine Christiansen for the reasons set forth in
`
`my prior declaration. Ex. 1003, ¶¶ 149-150.
`
`7.
`
`I understand Patent Owner’s argument in opposition focuses solely on
`
`the claim limitation that recites “an arbiter included in the memory interface circuit
`
`of the decoder.” In particular, I understand the Patent Owner and its declarant, Dr.
`
`
`
`–4–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`Thornton, to argue that Bowes’ memory controller and arbiter (MCA) 200 “is not
`
`part of DSP 20’s path to the memory.” PO Response, p. 4; Ex. 2009 (Thornton
`
`Declaration), ¶ 36. I disagree as detailed below.
`
`A. Bowes Teaches an Arbiter (MCA 200) included in the Memory
`Interface Circuit of DSP 20
`
`8.
`
`As a preliminary note, notwithstanding Dr. Thornton’s indication that
`
`he has used the Board’s construction of the term “memory interface circuit” in his
`
`analysis, my interpretation of Dr. Thornton’s analysis is that, in an effort to reach a
`
`conclusion that the “memory interface circuit” of DSP 20 does not include
`
`arbitration logic located in MCA 200, Dr. Thornton ignores the Board’s
`
`construction. Under the Board’s adopted construction of the term, Bowes’
`
`arbitration logic located in MCA 200 is included in the “memory interface circuit”
`
`of DSP 20.
`
`9.
`
`In particular, in a system such as Bowes which includes an arbiter
`
`controlling access to a shared memory via a memory bus, that arbiter receives
`
`memory bus requests and supplies memory bus grants to various agents within the
`
`system (in Bowes, the CPU, DSP, and others). The arbiter must act on those
`
`memory bus requests (by supplying memory bus grants) before any of those agents
`
`can access the shared memory by way of the memory bus.
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`
`
`–5–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`10. Thus, the arbiter coordinates or controls the agents’ access to the
`
`shared memory. Without a grant of access provided by the arbiter, an agent does
`
`not access the shared memory. Arbitration for, and use of, the memory bus is
`
`intrinsic to the act of accessing memory by any agent. Accordingly, a POSITA
`
`would understand that an arbiter is included in a coordination or control “path to
`
`memory” in a system such as Bowes. The arbiter must coordinate the competing
`
`requests to access memory, and it controls which agent in the system accesses
`
`memory based on an arbitration scheme (such as that provided in Bowes’ FIG. 3).
`
`Indeed, the Board’s construction of “memory interface circuit” as “hardware,
`
`including signaling paths to or from a competing device or an arbiter, to coordinate
`
`communication via a memory bus” explicitly includes the arbitration as being a
`
`part of the memory interface circuit.
`
`11.
`
`In the system described by Bowes, that coordination process, with
`
`respect to the DSP (which, in combination with the other references, teaches a
`
`“decoder”), includes the use of signaling lines denoted as DSPREQ and DSPBGN.
`
`Ex. 1005, FIG. 4. Before the DSP can access the memory bus (and in turn, the
`
`memory), the DSP must issue a request signal to the arbiter, which contains bus
`
`arbitration unit logic 240 to coordinate competing requests for the memory bus.
`
`Ex. 1005, 10:9-19. Thus, as Dr. Thornton agreed, there is a signaling path that
`
`
`
`–6–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
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`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`goes from the DSP in Bowes to the bus arbitration unit logic (within MCA 200).
`
`Ex. 1027, 38:5-10. If the DSP is to be granted access to the memory bus,
`
`according to the arbitration scheme, the bus arbitration unit logic 240 then supplies
`
`a grant signal back to the DSP and to no other agent. Thus, as Dr. Thornton also
`
`agreed, there is a signaling path that goes from the bus arbitration unit logic back
`
`to the DSP to propagate the bus grant signal. Id. That circuit path includes, or
`
`goes through, the arbiter MCA 200 in Bowes.
`
`12. Accordingly, the “memory interface circuit” of the DSP in Bowes
`
`includes at least those signaling paths, along with the device which requests
`
`memory access (the DSP), and the device which coordinates that memory access
`
`(the bus arbitration unit logic). That is to say, the DSP’s “memory interface
`
`circuit” includes at least: (1) the portion of the DSP which supplies the bus request
`
`signals and receives bus grant signals; (2) the signaling path from the DSP to the
`
`bus arbitration unit logic (denoted as DSPREQ); (3) the bus arbitration unit logic;
`
`and (4) the signaling path from the bus arbitration unit logic back to the DSP
`
`(denoted as DSPBGN). These elements in Bowes are all “hardware, including
`
`signaling paths to or from a competing device or an arbiter, to coordinate
`
`communication via a memory bus” as provided by the Board’s construction of
`
`“memory interface circuit.”
`
`
`
`–7–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`13.
`
`It remains my opinion that the bus arbitration logic 240 of Bowes’
`
`MCA 200 is coupled into the memory interface circuit of DSP 20 via DSPREQ
`
`and DSPBGN signal paths by which bus requests are made by DSP 20 and
`
`corresponding bus grants are received from MCA 200. I explained this in my
`
`original declaration, and I reemphasize it here. Ex. 1003, ¶¶ 141-144. The
`
`depictions of DSPREQ and DSPBGN signals as inputs to and outputs from bus
`
`arbitration unit logic 240 of MCA 200 of Bowes (Ex. 1005, FIG. 4), together with
`(i) corresponding logic specifications (dspbr_l and dspbg) of VERILOG code
`
`reproduced in Appendix A of Bowes for an ASIC implementation and (ii) the
`
`states reflected in the corresponding state transition diagram (Bowes Fig. 3), are
`
`corroborative. Ex. 1005, 8:3-23, 19:51-21:23, FIG. 3.
`
`14. Furthermore, the DSP3210 Datasheet itself lists the Bus Request
`
`(BRN) and Bus Grant (BGN) pins by which bus arbitration unit logic 240 of
`
`MCA 200 would be understood by a POSITA to be coupled to DSP3210 (an
`
`exemplary embodiment of DSP 20 in Bowes) and into its 32-bit bus-master
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`interface to system memory. Ex. 1006, Table 2 (pp. 17-19), FIG. 2 (p. 4).
`
`
`
`–8–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`
`
`
`
`Ex. 1006, p. 18 (Table 2, excerpt)
`15. As a POSITA would expect, Datasheet indicates that the Bus Request
`
`(BRN) pin is an output pin of the DSP3210, indicating that it sends a signal (as
`
`taught by Bowes, a DSPREQ bus request signal). That signal would be received
`
`by Bowes’ bus arbitration logic 240 in MCA 200. The bus arbitration logic 240,
`
`designed or synthesized, for example, in accordance with the VERILOG code and
`
`arbitration state transitions in FIG. 3 of Bowes, would supply a grant signal to the
`
`DSP in accordance with a current arbitration state and considering any competing
`
`requests. As indicated by the Datasheet, the Bus Grant (BGN) pin is an input pin,
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`indicating that the DSP3210 receives a signal (as taught by Bowes, a DSPBGN bus
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`grant signal). Thus, the bus arbitration logic 240 would be understood by a
`
`POSITA to be “included in the memory interface circuit of the decoder” as recited
`
`in claim 7. Accordingly, the opinions in my original declaration, that Bowes
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`
`
`–9–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
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`
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`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`teaches an arbiter “included in the memory interface circuit of the decoder,”
`
`remain the same.
`
`B. A POSITA Would Have Considered Colocating the Arbiter with
`the DSP
`
`16.
`
`I further understand the Patent Owner and its declarant, Dr. Thornton,
`
`to argue that a person of ordinary skill in the art would not have colocated the
`
`arbiter of Bowes with the DSP 20. Ex. 2009, ¶ 37. Again, I disagree as detailed
`
`below.
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`17. As I stated in my Petition declaration, Bowes states that arbiter logic
`
`“could be designed in some other form of logic.” Ex. 1005, 6:46-54; Ex. 1003, p.
`
`107. As I further stated, “one of ordinary skill in the art would have [] recognized
`
`that one of these other forms of logic would be in the DSP 20 (a decoder).” Ex.
`
`1003, p. 107.
`
`18. Dr. Thornton appears to argue that colocating the arbiter with the DSP
`
`would impact the DSP’s resources. But a POSITA would have understood that
`
`colocating the arbiter with the DSP 20 would not have any meaningful effect on
`
`the DSP’s available resources, including the bus and/or memory interface
`
`bandwidth available to the DSP, or the DSP’s processing power.
`
`19. For example, with respect to the DSP’s bus bandwidth, as I stated
`
`during my deposition, I do not believe the MCA 200 uses memory bus bandwidth.
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`
`
`–10–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
`
`Ex. 2010, 43:4-5. Accordingly, colocating the MCA 200 with the DSP would not
`
`impact the DSP’s memory bus bandwidth. A POSITA would have understood the
`
`same, as the MCA 200 merely controls access to the memory bus, but does not
`
`itself access or utilize the memory bus, and therefore does not use memory bus
`
`bandwidth. Dr. Thornton appears to agree:
`
`
`
`Ex. 1027, 40:12-20.
`
`20.
`
`Instead of addressing my testimony, Dr. Thornton appears to
`
`selectively mischaracterize my testimony to support his conclusions. In particular,
`
`Dr. Thornton cites my statement that “the logic required to implement the
`
`arbitration function would take up some of the chip’s resources.” Ex. 2009, ¶ 37.
`
`In context, the “resources” I mentioned were “gates” and “pins” available in a chip.
`
`Ex. 2010, 58:23-59:18. In terms of gates and pins, an integrated circuit
`
`implementation of the bus arbitration logic 240 in MCA 200 within a DSP would
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`
`
`–11–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
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`
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`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`likely employ a 4-bit counter, on the order of 100 logic gates, and about six pins
`
`(two for each bus master: the CPU, the I/O bus, and the NuBus, see Ex. 1005,
`
`5:20-6:43). Providing a counter, 100 logic gates, and six pins to an integrated
`
`circuit such as the DSP 20 would not have been a significant resource challenge to
`
`a POSITA at the time of the ’753 Patent. For example, Datasheet indicates that the
`
`DSP3210 was included on a 132 pin package, but packages well in excess of that
`
`number were available in 1995 and would have been available to a POSITA to use
`
`to co-locate an arbiter with a DSP, such as the DSP3210.
`
`21. Additionally, as I stated during my deposition, there is no overlap
`
`between the arbitration function and the functionality of an agent into which a
`
`POSITA would incorporate the arbiter (e.g., in this example, the DSP 20 in
`
`Bowes). Ex. 2010, 59:1-18. Since there is no overlap, resources consumed by the
`
`arbitration function would not have a negative impact on the DSP 20. That would
`
`be true even in Bowes’ system, which Dr. Thornton alleges is “optimized” to
`
`support the DSP. There would still be no significant resource competition between
`
`the arbitration function or logic and the DSP; both could operate with the same
`
`level of performance as if the components were separate.
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`22. As I also stated during my deposition, the only resource consumed by
`
`the arbiter (MCA 200) in Bowes is electrical current. Ex. 2010, 43:19–44:3. But
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`
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`–12–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`whether MCA 200 and DSP 20 were separate or colocated, a similar amount of
`
`electrical current would be used. The usage of that electrical current by the MCA
`
`200 would not affect the DSP 20’s processing power, or its ability to access the
`
`memory bus interface. Further, any heat dissipation requirements of the MCA 200
`
`would likewise not affect the DSP 20’s processing power or ability to access the
`
`memory bus interface. As a result, the arbiter’s electrical current and any heat
`
`dissipation requirements would certainly not dissuade a person from integrating the
`
`arbiter logic with other logic as suggested by Bowes. While Dr. Thornton alleges
`
`that the DSP requires that its resources “be reserved exclusively for data and
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`control traffic” (Ex. 2009, ¶ 37), I have again reviewed Bowes, and do not find
`
`support for Bowes describing any “exclusive” resource allocation, and in
`
`particular, for any “exclusive” resource allocation requirement that would dissuade
`
`a POSITA from colocating arbiter logic with a DSP (or decoder).
`
`23. Based on Dr. Thornton’s discussion in paragraphs 37 and 38 of his
`
`declaration, it appears that Dr. Thornton is of the opinion that the bus request
`
`signals and bus grant signals in Bowes would compete with data and address traffic
`
`on the memory bus, and thereby occupy some of the resources needed by Bowes’
`
`DSP. But as I stated during my deposition, and in my original declaration, Bowes
`
`provides separate bus request and bus granting signal lines between devices like
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`
`
`–13–
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
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`
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`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`the DSP and the arbiter, and Christiansen provides an example of a diagram which
`
`specifically calls out those separate control lines. Ex. 1003, ¶ 141. In Dr.
`
`Thornton’s deposition, he agreed that the DSPREQ and DSPBGN line in Bowes
`
`are separate control lines, and not data or address lines:
`
`
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`Ex. 1027, 55:8-17; see also Ex. 1027, 54:20-23. Thus, because the bus request
`
`signals and bus grant signals in Bowes are sent over control lines separate from
`
`data or address lines, those signals would not affect memory bus bandwidth. As I
`
`also stated in my deposition, Bowes indicates that bus bandwidth is not used in the
`
`arbitration. Ex. 2010, 50:2-5. Thus, contrary to Dr. Thornton’s allegations, a
`
`POSITA would not have considered colocation of the arbiter with the DSP to have
`
`impacted the DSP’s access to memory bus bandwidth.
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`
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`–14–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`
`
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`Declaration of Robert Colwell, Ph.D. in support of
`Petitioner Reply in IPR2016-01114
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`24. Finally, and despite Christiansen’s clear teaching that an arbiter “can
`
`be located anywhere throughout the computer system,” Dr. Thornton alleges that a
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`“POSA understands that, depending on the system, certain locations are unsuitable
`
`for the arbiter.” Ex. 1011, 5:16-19; Ex. 2009, ¶ 39. Dr. Thornton does not
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`elaborate on what locations are unsuitable. However, due to the proximity of
`
`respective memory bus interface circuits that are controlled by arbitration
`
`decisions, I would consider each of the handful of bus agents in Bowes (including
`
`the DSP) to be a suitable location for the arbitration logic. For at least the reasons
`
`set forth above, a POSITA would have understood that the DSP of Bowes is a
`
`suitable location for the arbiter.
`
`C.
`
`Patent Owner Misunderstands My Testimony
`
`25. As a final note, I understand that Dr. Thornton and Patent Owner
`
`utilize an isolated quotation from my deposition testimony to allege that the
`
`memory interface circuit of DSP 20 does not include anything in MCA 200.
`
`However, the quoted deposition testimony reflects my confusion about what was
`
`being asked of me during the deposition, and (even now) I remain unclear as to the
`
`question’s meaning. The question asked was: “Does the memory interface circuit
`
`of DSP 20 include anything in MCA 200?” The answer to the question could be
`
`yes or no. For example, if the questioner was asking if the memory interface
`
`circuit included anything like logic, then the answer would be yes, as arbiter logic
`
`
`
`–15–
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`
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`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
`
`Declaration of Robert Colwell, PhD. in support of
`Petitioner Reply in IPR2016—Ol l 14
`
`is certainly included in the circuit path that connects to the DSP 20 Via the request
`
`(DSPREQ) and grant (DSPBGN) signal paths that control the DSP’s bus interface
`
`to memory, as I discussed extensively in my Petition Declaration, and which are
`
`not shared by other bus agents. That arbiter logic in MCA 200 allocates bus
`bandwidth to DSl’ 20 per Bowes Fig. 3. But at the same time, the question could
`
`also mean “is there logic in MCA 200 corresponding to the data paths of DSP 20?”
`
`or “is MCA 200 inside DSP 20?” to which the answers are no. With respect to
`
`data paths, Bowes does not indicate that data flows through MCA 200, but rather,
`
`that the MCA 200 simply provides bus grants to competing devices in Bowes’s
`
`system. Additionally, strictly speaking, the MCA 200 is not “inside DSP 20,” as
`
`they are separate components in Bowes, but as I mentioned previously, a POSITA
`
`would have found it obvious, for many reasons, to colocate an arbiter with a DSP.
`
`V.
`
`Declaration
`
`I declare that all statements made herein on my own knowledge are true and
`
`that all statements made on information and belief are believed to be true, and
`
`further, that these statements were made with the knowledge that willful false
`
`statements and the like so made are punishable by fine or imprisonment, or both,
`
`under Section 1001 of Title 18 of the United States Code.
`
`Date: é’8’
`
`Executed:W
`
`Robert Colwell, Ph.D.
`
`—16—
`
`Apple v. PUMA
`IPR2016-01114
`
`Ex. 1028
`
`Apple v. PUMA
`IPR2016-01114
`Ex. 1028
`
`
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