IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Petition for Inter Partes Review
`
`Attorney Docket No.: 52959.21
`Customer No.:
`27683
`
`Real Party in Interest:
`Apple Inc.
`
`
`
`
`
`In re patent of Owen et al.
`
`U.S. Patent No. 7,777,753
`
`Issued: Aug. 17, 2010
`
`Title: Electronic System and Method
`For Selectively Allowing Access To
`A Shared Memory
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
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`
`
`Declaration of Robert Colwell, Ph.D.
`Under 37 C.F.R. § 1.68
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`
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`–1–
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`Apple Exhibit 1003
`Page 1 of 123
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`Table of Contents
`
`Introduction .......................................................................................................... 5 
`I. 
`II.  Qualifications and Professional Experience ........................................................ 7 
`III.  Level of Ordinary Skill in the Art ..................................................................... 10 
`IV. Relevant Legal Standards .................................................................................. 11 
`V.  The ’753 Patent .................................................................................................. 12 
`A.  Overview ..................................................................................................... 12 
`
`B.  History of the ’753 Patent ........................................................................... 19 
`
`VI. Claim Construction ............................................................................................ 20 
`VII.  Overview of References .............................................................................. 30 
`A.  Overview of Bowes (U.S. Patent No. 5,546,547) ...................................... 30 
`
`B.  Overview of DSP3210 Data Sheet ............................................................. 33 
`
`C.  Overview of Artieri (translation of EP 0626653) ....................................... 36 
`
`D.  Overview of Arimilli (U.S. Patent No. 6,029,217) .................................... 39 
`
`E.  Overview of Gove ...................................................................................... 40 
`
`F.  Overview of Shanley .................................................................................. 42 
`
`G.  Overview of Christiansen (U.S. Patent No. 5,787,264) ............................. 42 
`
`H.  Overview of Tahara .................................................................................... 43 
`
`VIII.  Challenge #1: Claims 1 and 2 are invalid under 35 U.S.C § 103 over
`Bowes as informed by the DSP3210 Data Sheet and in view of Artieri
`and Arimilli. ................................................................................................ 44 
`A.  Bowes’ DSP as a “video circuit” [or “decoder”] ....................................... 48 
`
`B.  Use of a shared “main memory” was known: ............................................ 59 
`
`C.  An arbiter circuit configured for “queuing,” as recited in claims 1 (see
`also claim 8) was known ............................................................................ 64 
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`D.  Reasons to Combine Bowes, DSP3210 Data Sheet, and Artieri ................ 67 
`
`E.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Arimilli . 69 
`
`F.  Detailed Analysis: Claims 1-2 .................................................................... 71 
`
`IX. Claim 3 is invalid under 35 U.S.C § 103 over Bowes as informed by the
`DSP3210 Data Sheet and in view of Artieri and Arimilli in further
`view of Tahara ............................................................................................. 89 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Arimilli
`in further view of Tahara ............................................................................ 90 
`
`B.  Detailed Analysis of Claim 3 ..................................................................... 91 
`
`X.  Challenge #2: Claim 4 is invalid under 35 U.S.C § 103 over Bowes, as
`informed by the DSP3210 Data Sheet and in view of Artieri and
`Arimilli in further view of Shanley. ............................................................ 92 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Arimilli
`in further view of Shanley .......................................................................... 92 
`
`B.  Detailed Analysis of Claim 4 ..................................................................... 94 
`
`XI. Challenge #3: Claim 7 is invalid under 35 U.S.C § 103 over Bowes, as
`informed by the DSP3210 Data Sheet, and in view of Artieri, in further
`view of Christiansen .................................................................................... 95 
`A.  An Arbiter included in the Memory Interface Circuit of the Decoder ....... 95 
`
`B.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri and
`Christiansen ................................................................................................ 99 
`
`C.  Detailed Analysis Claim 7 ........................................................................ 100 
`
`XII.  Challenge #4 – Claims 8 and 10 are invalid under 35 U.S.C. § 103 over
`Bowes as informed by the DSP3210 Data Sheet, in view of Artieri and
`Christiansen, and in further view of Arimilli ............................................110 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri,
`Christiansen, and Arimilli......................................................................... 111 
`
`B.  Detailed Analysis of Claim 8 ................................................................... 111 
`
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`C.  Detailed Analysis of Claim 10 ................................................................. 114 
`
`1.  Further Reasons to Combine Christiansen .......................................... 114 
`
`2.  Claim 10 Detailed Analysis ................................................................. 116 
`
`XIII.  Challenge #5 – Claim 9 is invalid under 35 U.S.C. § 103 over Bowes as
`informed by the DSP3210 Data Sheet and in view of Artieri and
`Christiansen, in further view of Shanley ...................................................117 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and
`Christiansen in further view of Shanley ................................................... 117 
`
`B.  Detailed Analysis of Claim 9 ................................................................... 118 
`
`XIV.  Challenge #6: Claim 12 is invalid under 35 U.S.C § 103 over Bowes as
`informed by the DSP3210 Data Sheet and in view of Artieri and
`Christiansen, in further view of Gove .......................................................118 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and
`Christiansen in further view of Gove ....................................................... 119 
`
`B.  Detailed Analysis of Claim 12 ................................................................. 120 
`
`XV.  Declaration .................................................................................................123 
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`I.
`
`Introduction
`
`I, Robert Colwell, Ph.D., declare:
`
`1.
`
`I am making this declaration at the request of Apple Inc. in the matter
`
`of the Inter Partes Review of U.S. Patent No. 7,777,753 (“the ’753 Patent”) to
`
`Owen et al.
`
`2.
`
`I am being compensated for my work in this matter. I am also being
`
`reimbursed for reasonable and customary expenses associated with my work and
`
`testimony in this investigation. My compensation is not contingent on the outcome
`
`of this matter or the specifics of my testimony.
`
`3.
`
`In the preparation of this declaration, I have studied:
`
`(1) The ’753 Patent, Exhibit 1001;
`
`(2) The prosecution history of the ’753 Patent, Exhibit 1002;
`
`(3) U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”), Exhibit 1005;
`
`(4)
`
`“AT&T DSP3210 Digital Signal Processor The Multimedia Solution”
`
`Data Sheet March 1993 (“DSP3210 Data Sheet”), Exhibit 1006
`
`(5) EP 0626653 to Artieri, English translation, Exhibit 1007
`
`(6) U.S. Patent No. 6,029,217 to Arimilli et al. (“Arimilli”), Exhibit 1008
`
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`(7) R. Gove, “The MVP: A Highly-Integrated Video Compression Chip”,
`
`IEEE 1994 (“Gove”), Exhibit 1009;
`
`(8)
`
` T. Shanley et al., “PCI System Architecture”, Addison –Wesley
`
`Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”), Exhibit 1010;
`
`(9) U.S. Patent No. 5,787,264 to Christiansen et al. (“Christiansen”),
`
`Exhibit 1011;
`
`(10) U.S. Patent No. 5,473,380 to Tahara (“Tahara”), Exhibit 1012; and
`
`(11) other documentation as designated in the analysis below.
`
`
`
`4.
`
`In forming the opinions expressed below, I have considered:
`
`(1) The documents listed above,
`
`(2) The relevant legal standards, including the standard for obviousness
`
`provided in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007), and
`
`(3) My own knowledge and experience, including my work experience in
`
`the fields of electrical engineering, computer engineering, computer
`
`architectures, memory interfacing, and multimedia technologies, and my
`
`experience in working with others involved in those fields, as described
`
`below.
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`II. Qualifications and Professional Experience
`
`5. My complete qualifications and professional experience are described
`
`in my curriculum vitae, a copy of which can be found in Exhibit 1004. The
`
`following is a brief summary of my relevant qualifications and professional
`
`experience.
`
`6.
`
`I have nearly 40 years of professional experience in the field of
`
`processor and system architecture design. I consider myself an expert in, among
`
`other things, CPU architecture and computer systems.
`
`7.
`
`I received an undergraduate Bachelor of Science degree in Electrical
`
`Engineering from the University of Pittsburgh in 1977. I received a Master’s of
`
`Science degree in Computer Engineering from Carnegie Mellon University in 1978
`
`as well as a Ph.D. in Computer Engineering in 1985.
`
`8.
`
`From 1977 to 1980, I held an engineering position at Bell Telephone
`
`Laboratories where I worked on, among other things, microprocessor hardware
`
`design.
`
`9.
`
`From 1980 to 1984, I held an engineering position at Perq Systems,
`
`where I worked on hardware design in computer environments. From 1985 to
`
`1990, I held an engineering position at Multiflow Computer, where I served as a
`
`hardware architect. While at Multiflow Computer, I assisted in creating the first
`
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`very long instruction word (VLIW) scientific supercomputer.
`
`10. From 1990 to 2001, I held various positions at Intel including Senior
`
`CPU Architect and later Chief Architect (for Intel’s IA-32, also known as x86). As
`
`part of my responsibilities at Intel, I co-invented Intel’s P6 microarchitecture that
`
`formed the core of the Pentium II manufactured by Intel (as well as the Pentium
`
`III, Celeron, Xeon, and Centrino families). The P6 core is still very influential
`
`today, in Intel’s top-of-the-line Core i3, i5, and i7 processors. In addition, I led
`
`Intel’s x86 Pentium CPU architecture endeavors. I was honored to be named an
`
`Intel fellow in 1997 in recognition of my contributions to the P6 microarchitecture
`
`development.
`
`11.
`
`I became a self-employed industry consultant in 2001, working with
`
`computer industry clients such as Safeware, the University of Pittsburgh, Intel,
`
`many venture capital companies, and the U.S. Department of Defense (DoD).
`
`12. From 2011 to 2014, I worked at the Defense Advanced Research
`
`Projects Agency (DARPA) first as Deputy Director, then Director, of the
`
`Microsystems Technology Office (MTO). MTO had an annual budget of
`
`approximately $600M, and my job as office leader was to invest that money in
`
`promising new technologies for the DoD, including new energy-efficient
`
`computing systems, modular and adaptable radars, position/navigation/timing
`
`systems for GPS-denied environments, computer-mediated prosthetics for military
`
`
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`(and civilian) amputees, traumatic brain injury detection devices for soldiers, fused
`
`multiple-band night vision sensors, extremely high power lasers, and much more.
`
`13.
`
`I have been recognized by the industry for my contributions to
`
`processor design. I received the Eckert-Mauchly Award in 2005 for “outstanding
`
`achievements
`
`in
`
`the design and
`
`implementation of
`
`industry-changing
`
`microarchitectures, and for significant contributions to the RISC/CISC architecture
`
`debate.” The Eckert-Mauchly Award is generally viewed as the highest possible
`
`recognition in the field of computer architecture.
`
`14.
`
`I was inducted into the National Academy of Engineering in 2006, the
`
`nation’s highest honorary society for engineering achievement. In 2012 I was
`
`inducted into the American Academy of Arts and Sciences; other inductees in my
`
`“class” that year included Sir Paul McCartney, Hillary Rodham Clinton, and Mel
`
`Brooks.
`
`15.
`
`In 2015 I received the Bob Rau Award from the Institute of Electrical
`
`and Electronics Engineers (IEEE), for “contributions to critical analysis of
`
`microarchitecture and the development of the Pentium Pro processor.”
`
`16.
`
`I have published many conference papers, sections of textbooks, and
`
`articles for magazines. I have also been named an inventor on 40 patents related to
`
`computer hardware and processor design. I have also been an editor for several
`
`
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`IEEE publications.
`
`17. My curriculum vitae (Ex. 1004) includes a list of all publications I
`
`have authored in the last 10 years.
`
`18.
`
`In summary, I have extensive familiarity with multimedia systems,
`
`computer architectures, unified memory architectures, and methods related to
`
`controlling memory access, and am familiar with what the states of these
`
`technologies were at the relevant time of the ’753 Patent invention and before.
`
`III. Level of Ordinary Skill in the Art
`
`19.
`
`I am familiar with the knowledge and capabilities of persons of
`
`ordinary skill in the computer system architecture and multimedia processing arts
`
`in the period around 1996. In addition to my own experiences, I worked with and
`
`spent 11 years leading an industrial microprocessor design team at Intel, which by
`
`the mid 1990’s included more than 450 engineers. The majority of those engineers
`
`I personally interviewed as part of the recruiting and hiring process. My experience
`
`working in the industry and interactions with colleagues and supervision of
`
`practicing engineers has allowed me to become directly and personally familiar
`
`with the level of skill of individuals and the general state of the art as of 1996.
`
`20.
`
`I have been informed by Apple’s counsel that the earliest alleged
`
`priority date for the ’753 Patent is August 26, 1996. Unless otherwise stated, my
`
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`testimony below refers to the knowledge of one of ordinary skill in the computer
`
`system architecture and multimedia processing arts in the period around and prior
`
`to August 26, 1996. In my opinion, the level of ordinary skill in the art appropriate
`
`to understanding the scientific and engineering principles applicable to the ’753
`
`Patent is (i) a Bachelor of Science degree (or higher degree) in an academic area
`
`emphasizing electrical or computer engineering and (ii) three years of relevant
`
`industry experience.
`
`IV. Relevant Legal Standards
`
`21.
`
`I have been asked to provide my opinions regarding whether claims 1-
`
`4, 7-10, and 12 of the ’753 Patent would have been obvious to a person having
`
`ordinary skill in the art at the time of the alleged invention, in light of the prior art.
`
`I have been informed by Apple’s counsel that a claimed invention is unpatentable
`
`under 35 U.S.C. § 103 if the differences between the invention and the prior art are
`
`such that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which the subject
`
`matter pertains. I have also been informed by counsel that the obviousness analysis
`
`takes into account factual inquiries including the level of ordinary skill in the art,
`
`the scope and content of the prior art, and the differences between the prior art and
`
`the claimed subject matter.
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`
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`22.
`
`I have been informed by counsel that the Supreme Court has
`
`recognized several rationales for combining references or modifying a reference to
`
`show obviousness of claimed subject matter. Some of these rationales include the
`
`following: (a) combining prior art elements according to known methods to yield
`
`predictable results; (b) simple substitution of one known element for another to
`
`obtain predictable results; (c) use of a known technique to improve a similar device
`
`(method, or product) in the same way; (d) applying a known technique to a known
`
`device (method, or product) ready for improvement to yield predictable results; (e)
`
`choosing from a finite number of identified, predictable solutions, with a
`
`reasonable expectation of success; and (f) some teaching, suggestion, or motivation
`
`in the prior art that would have led one of ordinary skill to modify the prior art
`
`reference or to combine prior art reference teachings to arrive at the claimed
`
`invention.
`
`V. The ’753 Patent
`
`A. Overview
`
`23. The ’753 Patent generally describes an electronic system with a first
`
`device and a “video/audio compression/decompression device such as a
`
`decoder/encoder” to share a memory. (Ex. 1001, Abstract). “An arbiter selectively
`
`provides access for the first device and/or the decoder/encoder to the memory
`
`based on priority.” (Ex. 1001, Abstract).
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`24.
`
`In order to fit digital media, such as movies, onto a “conventional
`
`recording medium, such as a CD,” the ’753 Patent recognizes it was already known
`
`to “compress video and audio sequences before they are transmitted or stored.”
`
`(Ex. 1001, 1:44-51). For compression/decompression, “[t]he MPEG standards are
`
`currently well accepted standards for one way communication. H.261, and H.263
`
`are currently well accepted standards for video telephony.” (Ex. 1001, 2:6-7). The
`
`’753 Patent further states that electronic systems added decoders to systems (such
`
`as a computer) in order to “allow them to display compressed sequences.” (Ex.
`
`1001, 2:14-17).
`
`25. The ’753 Patent continues and explains that a decoder for MPEG
`
`sequences “typically … requires a 2 Mbyte memory,” and that such memory was
`
`“dedicated to the MPEG decoder 10 and increases the price of adding a decoder 10
`
`to the electronic system.” (Ex. 1001, 2:44-51). The ’753 Patent views this
`
`dedicated memory as a problem that increased the cost of the decoder. (Ex. 1001,
`
`2:49-51). The ’753 Patent allegedly addresses this problem by having the “video
`
`and/or audio decompression and/or compression device share[] a memory interface
`
`and the memory with the first device.” (Ex. 1001, 5:2-3). Figure 2 of the ’753
`
`Patent illustrates an electronic system containing a device (“first device”) having a
`
`shared memory with a decoder:
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`’753 Patent (Ex. 1001), FIG. 2
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`
`
`The ’753 Patent explains that its proposed solution results in cost reduction “due to
`
`the fact that the video and/or audio decompression and/or compression device does
`
`not need its own dedicated memory but can share a memory with another device
`
`and still operate in real time.” (Ex. 1001, 5:48-51).
`
`26. The ’753 Patent further explains that the system, such as the system of
`
`FIG. 2, includes an arbiter, where requests for access to the memory are granted
`
`based on a priority scheme, which “can be any priority scheme that ensures that the
`
`decoder/encoder 80 gets access to the memory 50 often enough and for enough of
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`a burst length to operate properly, yet not starve the other devices sharing the
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`memory.” (Ex. 1001, 13:30-35). I note that below, in claim 1, the arbiter performs
`
`the function of “controlling access to said main memory.” (See also, claim 7
`
`“control access to the memory”) As set forth in the ’753 Patent specification, I
`
`understand that the arbiter performs this function by allowing only one of the
`
`devices to access the main memory at a given time. (Ex. 1001, 13:11-29). The
`
`’753 Patent states that its system includes a “bus 70 [FIG. 2 above], that have a
`
`bandwidth greater than the bandwidth required for the decoder/encoder 80 to
`
`operate in real time. … A fast bus 70 is any bus whose bandwidth is equal to or
`
`greater than the required bandwidth.” (Ex. 1001, 7:48-8:10). Exemplary buses
`
`that, according to the ’753 Patent, provide bandwidth to be considered “fast”
`
`include “a PCI bus,…VESA Local Bus (VLB), an Accelerated Graphics Port
`
`(AGP) bus, or any bus having the required bandwidth.” (Ex. 1001, 10:17-24, see
`
`also Ex. 1001, 5:26-33). PCI bus, VESA Local Bus (VLB), and Accelerated
`
`Graphics Port (AGP) bus were known, available bus architectures.
`
`27. As an initial matter, the alleged solution presented in the ’753
`
`Patent—sharing a memory between multiple devices and arbitrating access thereto
`
`between the devices—was well known to persons of ordinary skill in the art before
`
`the earliest alleged priority date of the ’753 Patent. For example, others had
`
`previously identified the problem of dedicated “substantial block of static random
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`access memory … SRAMs are significantly more expensive than DRAM which
`
`greatly increases the cost of computer systems which incorporate SRAM.” (Ex.
`
`1005, 2:36-41). Further, others had identified the same solution to the problem,
`
`namely providing “a mechanism and method for arbitrating the memory bus
`
`bandwidth to efficiently allow the use of a digital signal processor and a CPU over
`
`a common memory bus sharing the system's dynamic random access memory
`
`subsystem without requiring an expensive block static random access memory.”
`
`(Ex. 1005, 2:57-63).
`
`28. Additionally, digital signal processors were known to provide
`
`compression and decompression (e.g., MPEG) processing before the ’753 Patent.
`
`(See, e.g., Ex. 1016, “TMS” (TMS teaches that the single-chip multiprocessor DSP
`
`(“TMS320C8x” p. iii) may be used to accelerate applications “such as video
`
`compression and decompression, image processing, and graphics manipulation.”
`
`(Ex. 1016, p. A-6; Ex. 1009, 216).
`
`29.
`
`In claim 1 of the ’753 Patent, which is exemplary, a “processor” and a
`
`“video circuit” both require access to a main memory. The “video circuit” is
`
`configured to receive encoded data to be decoded and output decoded data. (Ex.
`
`1001, 15:36-40). Claim 1 of the ’753 Patent recites:
`
`1. An electronic system comprising:
`a bus;
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`a main memory coupled to the bus having stored therein data
`corresponding to video images;
`a video circuit coupled to the bus, the video circuit configured to
`receive data from the main memory corresponding to a current video
`image to be decoded and to output decoded video data corresponding to
`the current video image to be displayed on a display device, the current
`video image to be displayed adapted to be stored in the main memory;
`a processor coupled to the main memory, the processor for
`storing non-image data in the main memory and retrieving non-image
`data from the main memory; and
`an arbiter circuit coupled to the processor and to the video circuit,
`the arbiter circuit configured to receive requests for access to the main
`memory from the video circuit and the processor and to control access
`to the main memory by:
`providing access to the main memory for a request for
`access to the main memory when the arbiter circuit is in an idle
`state;
`
`queuing a request for access to the main memory when the
`arbiter circuit is in a busy state; and
`queuing a request for access to the main memory in an
`order based on a priority of the request and a priority of each of
`one or more other requests for access to the main memory that
`are currently queued when the arbiter circuit is in a queue state.
`
`30. Based on my experience, the electronic system described in the ’753
`
`Patent and claimed in claim 1, as well as those systems of claims 2-4, 7-10 and 12,
`
`were already well known to persons of ordinary skill in the art before the earliest
`
`
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`alleged priority date. For instance, others had already taught the usefulness of
`
`unified memory architectures with arbitration to the shared memory. (See Ex.
`
`1005, Bowes). One of ordinary skill in the art would recognize that arbitration
`
`must be present in any system that shares access to a resource (e.g., memory) in
`
`order to prevent conflicts. Arbitration schemes that were based on a priority were
`
`well known. (See, e.g., Ex. 1005, 4:51-55; Ex. 1008,1:47-51; Ex. 1011, 1:16-19)
`
`31. Prior to the earliest alleged priority date of the ’753 Patent, others had
`
`also taught the usefulness of video circuitry or a decoder interacting with a
`
`memory in order to receive encoded data and output decoded data. (See Ex. 1007).
`
`In fact, the International Organization for Standardization document the “ISO/IEC
`
`11172-2:1993:Information technology – Coding of moving pictures and associated
`
`audio for digital storage media at up to about 1,5 Mbit/s-Part 2:Video,” 1st ed.,
`
`August 1, 1993 (“MPEG Standard”), was publically available as of August 1993,
`
`years before the earliest alleged priority date of the ’753 Patent. The MPEG
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`Standard was a well-accepted industry standard. Ex. 1001, 2:6-7. The
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`compression disclosed in the MPEG Standard allows videos to be encoded to
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`reduce the bandwidth or memory requirements during storage or transmission; the
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`compressed images are subsequently decoded for display. (Ex. 1015, p. 52 (Figure
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`D.1)). The MPEG Standard provides for a decoder interacting with a “Picture
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`store” or a memory. (Ex. 1015, p. viii).
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`Ex. 1015, MPEG Standard, Figure 4
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`
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`32. Accordingly, as I show below, it is my opinion that the elements and
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`functionality recited in claims 1-4, 7-10, and 12 of the ’753 Patent were already
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`well known before the earliest claimed priority date of the ’753 Patent.
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`B. History of the ’753 Patent
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`33. The ’753 Patent issued on Aug 17, 2010 from U.S. Patent Application
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`No. 12/424,389 by Jefferson Eugene Owen, Raul Zegers Diaz, and Osvaldo
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`Colavin. I have been informed by counsel that the earliest alleged priority date for
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`the ’753 Patent is August 26, 1996.
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`34.
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`I have reviewed the prosecution history of the ’753 Patent and it is my
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`understanding that none of the references cited in this declaration were discussed
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`by the United States Patent Office during prosecution that led to the ’753 Patent.
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`VI. Claim Construction
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`35.
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`It is my understanding that in order to properly evaluate the ’753
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`Patent, the terms of the claims must first be interpreted. It is my understanding that
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`for the purposes of this inter partes review the claims are to be given their broadest
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`reasonable interpretation in light of the specification. It is my further understanding
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`that claim terms are given their ordinary and customary meaning as would be
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`understood by one of ordinary skill in the art, unless the inventor has set forth a
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`special meaning for a term. As such, any claim term not construed below should be
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`given its ordinary and customary meaning.
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`36.
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`In addition to the broadest reasonable interpretation set forth herein, I
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`have been informed that the ’753 Patent appears set to expire in August 2016. In
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`such cases, I have been told that the Board may construe patent claims, once
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`expired, according to the standard applied in the district courts by applying the
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`principles set forth in Philips v. AWH Corp., 415 F.3d 1030, 1312 (Fed. Cir. 2005)
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`(en banc). I am told under Philips principles, the words of the claims are generally
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`given their ordinary and customary meaning as understood by a person of ordinary
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`skill in the art in question at the time of the alleged invention. It is my opinion that
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`this change of standards would not affect any of the invalidity grounds discussed
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`herein should construction of the claims remain as provided herein.
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`37.
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`
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`In order to construe the following claim terms, I have reviewed the
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`–20–
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`entirety of the ’753 Patent as well as its prosecution history.
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`38.
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`“decoder”
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`39. This claim term is found in claims 7-10 and 12 as well as in the
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`detailed description. In context, the recited decoder is a video decoder in that the
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`claim recites that the decoder is coupled to a bus “for receiving encoded video
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`images and for outputting data for displaying decoded video images ….” (Ex.
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`1001, 16:17-19).
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`40. The ’753 Patent sets forth a special meaning for “decoder” as follows:
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`“[t]he resulting bitstream is decoded by a video and/or audio decompression device
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`(hereinafter decoder) before the video and/or audio sequence is displayed.” (Ex.
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`1001, 1:65-2:1) (Emphasis added). The ’753 Patent continues in the detailed
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`description: “[a]ny conventional decoder including a decoder complying to the
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`MPEG-1, MPEG-2, H.261, or H.261 standards, or any combination of them, of any
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`conventional standard can be used as the decoder/encoder.” (Ex. 1001, 15:27-30).
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`A person of skill in the art would recognize that such a decoder would ordinarily
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`be implemented using a combination of hardware, such as a digital signal
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`processor (DSP) with or without specialized computational pipelines, and software.
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`41.
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`In context provided by claim 7 itself, the recited decoder is necessarily
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`a video decoder in that, the claim recites that the decoder is coupled to a bus “for
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`receiving encoded video images and for outputting data for displaying decoded
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`video images ….” (Ex. 1001, 16:17-19).
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`42.
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`It is therefore my opinion based on my review of the ’753 Patent that
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`one of ordinary skill in the art would understand that “decoder” means video
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`decompression device.
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`43.
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`“video circuit”
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`44. The term “video circuit” is used in claim 1 of the ’753 Patent and,
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`based on the context provided by the claim language itself, a video circuit is
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`“configured to receive…a current video image to be decoded and to output
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`decoded video data corresponding to the current video image to be displayed ….”
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`(Ex. 1001, ’753 Patent, 15:36-40). As such, the term is closely related to the
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`“decoder” term construed above.
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`45. While there is no clear description of circuitry per se in the ’753
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`Patent, the specification does identify a “video decoding circuit 12” block that is
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`apparently part of a more general “decoder.” (Ex. 1001, 6:47; see also FIGs. 1a,
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`1b and 2). Based on my review of the ’753 Patent, it appears that the closest
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`approximation of a video circuit actually described in the patent would be in
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`connection with the block diagram of FIG. 6 (duplicated below) which the ’753
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`Patent identifies as an “electrical diagram, in block form” of “an MPEG decoder.”
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`(Ex. 1001, 6:17-19, FIG. 6).
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`
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`Ex. 1001, ’753 Patent, Fig. 6
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`46. The ’753 Patent describes this video circuit (or electrical diagram in
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`block form) aspect of its MPEG decoder as “[l]ike any conventional MPEG
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`decoder” in that it includes a variable length decoder (VLD) receiving compressed
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`data from First-In, First-Out (FIFO) memories. (Ex. 1001, 11:51-53). The ’753
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`Patent goes on to describe the pipelined flow through a Run-Level Decoder1
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`(RLD), an inverse quantization circuit Q-1, an inverse discrete cosine transform
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`circuit DCT-1, an adder 32, and a filter 34. (Ex. 1001, 6:17-19, 11:50-62). The
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`’753 Patent notes that the illustrated decoder differs from a “conventional decoder”
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`in that FIFOs are connected to a bus and a memory controller calculates and
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`supplies addresses for various required exchanges vi