5 g /W /. 3 _3
`
`«ii mi 1
`
`Ii
`
`A"
`
`4
`
`ziilzi/90
`
`.
`
`First lnventor
`
`Title
`
`PTO/SBl05 (05-03)
`Approved for use through 04/30/2003. OMB O651»0032
`U.S. Patent and Trademark Office. US. DEPARTMENT OF COMMERCE
`Under the Paewvork Reduction Act of 1995 no ersons are reuired to resend to a collection oi Inlormation unless it disla s a valid OMB control numbe
`00100.02.0053
`UTILITY
`PATENT APPLICATION
`TRANSMITTAL
`
`/lllllllllllllll
`
`59 lllll
`
`M“ M‘ “°"""‘e’
`Dividing Work Among Multiple Graphics Pipelines
`Using a Super—Tiling Technique
`EV 063310627 US
`
`(Only for new noriprovisional applications under 37 CFR 1. 53(b))
`
`Express Mail Label No.
`
`APPLICATION ELEM ENTSA
`See MPEP chapter 600 concemlng utility patent application contents.
`
`ADDRESS TO:
`
`commissioner for Patents
`Mail Stop Patent Application
`P.0. Box 1450
`Alexandria VA 22313-1450
`
`Fee Transmittal Form (e.g.. PTOISB/17)
`(Submit an original and a duplicate for fee processing)
`Applicant Claims Small Blllltt’ 5l3lU5-
`See 37 CFR 1.27.
`
`[Total Pages
`Specification
`(preferred arrangement set forth below)
`- Descriptive title of the invention
`- Cross Reference to Related Applications
`- Statement Regarding Fed sponsored R & D
`- Reference to sequence listing. a table,
`or a computer program listing appendix
`- Background of the Invention
`- Brief Summary of the Invention
`- Brief Description of the Drawings (if filed)
`- Detailed Description
`- C|aim(s)
`- Abstract ot the Disclosure
`
`Drawing(s) (35 u.s.c. 113) [Totalsheetsl
`4.
`5. Oath or Declaration
`[Total Sheets
`]
`a. El Newly executed (original or copy)
`
`b. I:] Copy from a prior application (37 CFR 1.63(d))
`(for continuation/divisional with Box 18 completed)
`
`i. [:1 DELETION or lNVENTOR(S)
`Signed statement attached deleting invcntor(s)
`name in the prior application, see 37 CFR
`1.63(d)(2) and 1.33(b).
`
`6.l:]
`
`Application Data Sheet. See 37 CFR 176
`
`7. El CD—ROM or CD-R in duplicate, large table or
`Computer Program (Appendix)
`8. Nucleotide and/or Amino Acid Sequence Submission
`(if ap licable, all necessary)
`a.
`Computer Reader Fon'n (CRF)
`b.
`Specification Sequence Listing on:
`
`]
`
`i. E]
`
`CD-ROM or CD-R (2 copies); or
`
`ii. [:I
`
`Paper
`
`c. I:l Statements verifying identity of above copies
`ACCOMPANYING APPLICATION PARTS
`
`Assignment Papers (cover sheet & document(s))
`37 CFR 3.73(b) Statement
`Power of
`(when there is an assignee)
`Attorney
`English Translation Document {if a
`llcable)
`lnforrnation Disclosure
`Copies of IDS
`Statement (lDS)lPTO«1499
`Citations
`Preliminary Amendment
`Return Receipt Postcard (MPEP 503)
`(Should be specifically itemized)
`Certified Copy of Priority Document(s)
`(if foreign priority is claimed)
`Nonpublication Request under 35 U.S.C. 122
`(b)(2)(B)(i). Applicant must attach forrn PTOlSBl35
`or its equivalent.
`Other: ...... ..
`
`18. if a CONTINUING APPLICATION. check appropriate box, and supply the requisite infonnation below and in the first sentence of the
`specification following the title, or in an Application Data Sheet under 37 CFR 1. 76:
`
`of prior application No.: ............................... ..
`I:I Divisional
`El Continuation
`Art Unit:
`Examiner
`Prior application information:
`For CONTINUATTON OF DIVISIONAL APPS only; The entire disclosure of the prior application, from which an oath or declaration is supplied under Box
`5b, is considered a pan of the disclosure ol the accompanying continuation or divisional application and is hereby incorporated by reference.
`The Incorporation can only be relied upon when a portion has been inadvertently omitted from the submitted application parts.
`19. CORRESPONDENCE ADDRESS
`3-‘
`
`I:I Continuation-in—part (CIP)
`
`OR
`
`IE Correspondence address below
`
`E Customer Number or Bar Code Label
`
`. as . rtc
`Name
`Christopher J. Reckamp
`Vedder Price Kaufman & Kammholz
`I I I
`-
`-
`'
`' ‘
`Chicao
`°°~"W
`U.S.A.
`
`l Slatel ”_
`Telephone
`
`zip Code 60601
`312-609-500
`
`2- I -7 - -
`Registration No. (Altomey/Agent) 341414
`
`_ ' “ .
`=
`. . ' _
`'
`CT"/0’7—‘P-
`This collection of information is required by 37 I R 1.53(b). The lnton-nation is quired to obtain or retain a benefit by the public which is to tile (and by the USPTO to process)
`an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14, This collection is estimated to take 12 minutes to complete, Including gathering, preparing, and
`submitting the completed application lorm to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to cuiriplele this
`lorm and/or suggestions for reducing this burden. should be sent to the Chiet lnfomiation Officer, US. Patent and Trademark Office, US. Department of Commerce, P.O. Box
`1450, AIexaiirIn'a_ VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Mail Stop Patent Application, Commissioner [or
`Patents, PO. Box 1450, Alexandria, VA 22313-1450.
`Ifyou need assistance in completing the form, call 1-800-PTO—9199 and select option 2.
`
`1083973
`
`TEXAS INSTRUMENTS EX. 1002 - 1/615
`
`

`
`£0/Zi/90
`
`PTOISB/17 (01-03)
`Approved for use through 04/30/2003. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`nder the Paerwork Reduction Act of 1995 no ersons are re uired to resend to a collection of information unless it disla s a valid OMB control number.
`
`FEE TRANSMITTAL
`
`Effective 01/01/2003. Patent fees are subject to annual revision.
`
`D Applicant claims small entity status. See 37 CFR 1.27
`TOTAL AMOUNT OF PAYMENT
`862.00
`
`6/12/03
`Mark M. Leather
`
`Attome Docket No.
`
`00100020053
`
`Other
`
`I
`A-H Technologes Inc.
`
`r er
`Check I] Creditcard ‘j '64°d"9Y
`I Deposit Account:
`Deposu
`Account
`50-0441
`Number
`Deposit
`Account
`Name
`- Commissioner is authorized to: (check all that apply)
`harge feem indicated below
`Cred” any ovcrpaymems
`Dcharge any additional fee(s) during the pendency of this application
`Dcharge fee(s) indicated below, except for the filing fee
`to the above-identified deposit account.
`FEE CALCULATION
`1. BASIC FILING FEE
`-
`-
`
`2051
`
`2052
`1053
`
`Fee Description
`_
`65 Surcharge — late filing fee or oath
`f
`5
`ii
`—lt
`"
`lt"|‘
`25 cxgrirhgleit ae provisiona iing ea or
`130 Non-English specification
`t_
`_
`,1
`F
`fl‘
`t f
`1812 2,520
`or iing a reques or ex pa (-2 reexamina ion
`1804
`920' Requesting publication of SIR prior to
`Examine, action
`1305 1‘34g- Requesgng pubficatjon of SR after
`E"ami""-"' a°”°“
`first m:nth th
`55 Extension for reply
`in secon mon
`205
`x ension or rep y WI
`465 Extension for reply within third month
`
`2251
`2252
`2253
`
`£e
`
`Fee Paid
`
`2254
`
`725 Extension for reply within fourth month
`935 Extension for reply within fifth month
`
`2001 375
`2002 165
`2003 250
`2004 375
`2005
`so
`
`2255
`flu‘.
`Utility filing fee
`Design filing fee — 2401
`p|an1 fifing fee
`2402
`Reissue filing fee - 2403
`p.-01,1510,-.31 fi|ing fee
`1451
`
`160 Notice of Appeal
`160 Filing a brief in support of an appeal
`140 Request for oral hearing
`1,510 Petition to institute a public use proceeding
`
`SUBTOTAL (1)
`
`75000
`
`2452
`2453
`
`55 Petition to revive - unavoidable
`650 Petition to revive - unintentional
`
`2. EXTRA CLAIM FEES FOR uTiLiryeflri3nREissuE
`Extra Claims
`~
`F
`'
`-90"= El
`,, _
`'3 ' E
`
`-
`
`ee escr 9 on
`D
`I H
`
`F
`
`T°‘a'C"""”‘
`Independent
`Claims
`Mum” Dependem
`ee
`ee
`ee
`ee
`"Far 9 Em“
`s":""a" EFM“
`code (3)
`code (5)
`9 Claims in excess of 20
`1202
`18
`2202
`1
`1
`42
`Independent claims in excess of 3
`1201
`B4
`2201
`1203 280
`2203 140 Multipledependentclaim,ifnotpaid
`1204
`34
`2204
`42 " Reissue independent claims
`over original patent
`"‘ Reissue claims in excess of 20
`and over original patent
`
`1205
`
`18
`
`2205
`
`9
`
`$ 72.00
`SUBTOTAL (2)
`“or number reviousl aid, if reater; For Reissues, see above
`suamineo By
`
`2501
`2502
`2503
`1460
`1807
`1806
`8021
`2809
`
`2310
`
`650 ljfiliiyissue fee (meissue)
`235 Design issue fee
`315 Plant issue fee
`130 Petitions to the Commissioner
`I'0C3SSlI'|g 99 Un er
`.
`so P
`'
`f
`d
`37 CFR1 17(q)
`,
`.
`180 Submission of Information Disclosure Stmt
`40 Recording each patentassignment per
`property (times number of properties)
`375 Filing a submission after final rejection
`(37 CFR 1.129(a))
`375 Fgreach addmonaiinvenfigntg be
`examined (37 CFR 1‘129(b))
`375 Request for Continued Examination (RCE)
`900 Request for B><D8dii9d exflminafifl"
`of a design application
`
`SUBTOTAL (3)
`(Complete (irappiicabie)
`
`2801
`1302
`\
`"f
`f
`Oth
`'Re:ruce<:1(:pelEi:I:i)(: Filin Fee Pad
`y
`9
`'
`
`Telephone 312~609»7598
`Christopher J. Reckamp
`6/12/03
`J’?
`public. Credit card information should not
`WARNING: lnforma ' on this form may beco
`be Included on this form. Provide credit card information and authorization on PTO-2038.
`This collection of information is required by 37 CFR 1.17 and 1.27. The information is required to obtain or retain a benefit by the public which is to file (and by the
`USPTO to process) an application. Confidentiality is governed by 35 use. 122 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete,
`including gathering, preparing, and submitting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on
`the amount of time you require to complete this form andlor suggestions for reducing this burden, should be sent to the Chief information Officer, U.S. Patent and
`Trademark Office, US. Department of commerce, Washington. DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO:
`Commissioner for Patents. Washington, DC 20231.
`
`34414
`
`1034014
`
`If you need assistance in completing the form, call 1-800-PTO-9199 (1—800-786-9199) and select option 2.
`
`TEXAS INSTRUMENTS EX. 1002 - 2/615
`
`

`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants: Lcather et al.
`
`Serial No.:
`
`Examiner:
`
`Art Group:
`
`Filing Date:
`
`June 12, 2003
`
`Docket No.: O0100.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING A
`SUPER-TILING TECHNIQUE
`
`Mail Stop Patent Application
`Commissioner for Patents
`P O BOX 1450
`.
`Alexandria, VA 223134450
`
`Certificate ofExpress Mail
`I hereby certify that this paper is being deposited with the
`United States Postal Service "Express Mail Post Office to
`Addressee " service under 37 CFR 1.10, on the date
`indicated and is addressed to Mail Stop Patent
`A
`l"
`'
`,C "
`P
`,l’.0.B.I450,
`A1;;;;;z,77;;V;;’;',';;::*;e;,;‘°'
`0*
`Express Mail N0. E V 0633 1 062 7 US.
`ii.
`Winona K. Jackson .
`
`PRELIMINARY AMENDMENT
`
`Dear Sir:
`
`Prior to examination, Applicants respectfully request that the above-identified application
`
`be amended as follows:
`
`In The Specification:
`
`Please add the following new paragraph directly below the invention title on page 1 of
`
`the specification as follows:
`
`This application claims the benefit of U. S. Provisional Application Ser. No. 60/429,641
`
`filed November 27, 2002, entitled “Dividing Work Among Multiple Graphics Pipelines Using a
`
`Super—Ti1ing Technique”, having as inventors Mark M. Leather and Eric Dcmcrs, and owned by
`
`instant assignee.
`
`CHICAGO/#1083968. l
`
`TEXAS INSTRUMENTS EX. 1002 - 3/615
`
`

`
`REMARKS
`
`Applicants submit that the specification is fully supported by the original provisional
`
`application, and the claims are fully supported by the originally filed provisional application.
`
`Respectfully submitted,
`
`By: 4'4
`Chris opher J. Rcckamp
`Reg. No. 34,414
`
`Dated: June 12, 2003
`
`Vedder, Price, Kaufman & Kammholz
`222 North LaSalle Street
`Chicago, Illinois 60601
`Telephone: (312) 609-7500
`Facsimile: (312) 609-5005
`
`CHICAGO/#1083968. I
`
`TEXAS INSTRUMENTS EX. 1002 - 4/615
`
`

`
`020053
`
`PATENT APPLICATION
`ATTY. DOCKET NO. 00100.02.0053
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`FILING OF A UNITED STATES PATENT APPLICATION
`
`DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES
`USING A SUPER-TILING TECHNIQUE
`
`INVENTORS:
`
`Mark M. Leather
`
`12187 Woodside Drive
`Saratoga, California 95070
`
`Eric Demers
`
`901 Sycamore Drive
`Palo Alto, California 94303
`
`ATTORNEY OF‘ RECORD:
`CHRISTOPHER J. RECKAMP
`
`REGISTRATION NO. 34,414
`VEDDER PRICE KAUFMAN & KAMMHOLZ
`222 NORTH LASALLE STREET, SUITE 2600
`CHICAGO, ILLINOIS 60601
`PHONE (312) 609-7500
`FAX (312) 609-5005
`
`Express Mail Label No.: EV 063310627 US
`
`Date of Deposit: June 12, 2003
`
`I hereby certify that this paper is being deposited with the
`U.S. Postal Service “Express Mail Post Office to
`Addressee” service under 37 C.F.R. Section 1.10 on the
`‘Date of Deposit’, indicated above, and is addressed
`to: Mail Stop Patent Application, Commissioner of Patents,
`P. O. Box 1450, Alexandria, VA, 22313-1450.
`
`Name of Depositor: Winona K. Jackson
`
`TEXAS INSTRUMENTS EX. 1002 - 5/615
`
`

`
`020053
`
`DIVIDTNG WORK AMONG MULTIPLE GRAPHICS PIPELINES USING A
`SUPER-TILING TECHNIQUE
`
`RELATED CO—PENDING APPLICATION
`
`[0001]
`
`This is a related application to a co-pending application entitled “Parallel
`
`Pipeline Graphics System” having docket number 010025, having serial number
`
`, having Leather et al. as the inventors, filed on even date,
`
`owned by the same assignee and hereby incorporated by reference in its entirety.
`
`FIELD OF THE INVENTION
`
`[0001]
`
`The present invention generally relates to graphics processing circuitry
`
`and, more particularly, to dividing graphics processing operations among multiple
`
`pipelines.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`Computer graphics systems, set top box systems or other graphics
`
`processing systems typically include a host processor, graphics (including video)
`
`processing circuitry, memory (e.g. frame buffer), and one or more display devices. The
`
`host processor may have a graphics application running thereon, which provides vertex
`
`data for a primitive (e.g. triangle) to be rendered on the one or more display devices to
`
`the graphics processing circuitry. The display device, for example, a CRT display
`
`includes a plurality of scan lines comprised of a series of pixels. When appearance
`
`attributes (e. g. color, brightness, texture) are applied to the pixels, an object or scene is
`
`presented on the display device. The graphics processing circuitry receives the vertex
`
`data and generates pixel data including the appearance attributes which may be presented
`
`on the display device according to a particular protocol. The pixel data is typically
`stored in the frame buffer in a manner that corresponds to the pixels location on the
`
`display device.
`
`[0003]
`
`FIG. 1 illustrates a conventional display device 10, having a screen 12
`
`partitioned into a series of Vertical strips 13-18. The strips 13-18 are typically l-4 pixels
`
`in width. In like manner, the frame buffer ofconventional graphics processing systems is
`
`partitioned into a series of vertical strips having the same screen space width.
`
`1
`
`TEXAS INSTRUMENTS EX. 1002 - 6/615
`
`

`
`020053
`
`Alternatively, the frame buffer and the display device may be partitioned into a series of
`
`horizontal strips. Graphics calculations, for example, lighting, color, texture and user
`
`viewing information are performed by the graphics processing circuitry on each of the
`
`primitives provided by the host. Once all calculations have been performed on the
`
`primitives, the pixel data representing the object to be displayed is written into the frame
`
`buffer. Once the graphics calculations have been repeated for all primitives associated
`
`with a specific frame, the data stored in the frame buffer is rendered to create a video
`
`signal that is provided to the display device.
`
`[0004]
`
`The amount of time taken for an entire frame of information to be
`
`calculated and provided to the frame buffer becomes a bottleneck in graphics systems as
`
`the calculations associated with the graphics become more complicated. Contributing to
`
`the increased complexity of the graphics calculation is the increased need for higher
`
`resolution video, as well as the need for more complicated video, such as 3-D video. The
`
`video image observed by the human eye becomes distorted or choppy when the amount
`
`of time taken to render an entire frame of video exceeds the amount of time in which the
`
`display device must be refreshed with a new graphic or frame in order to avoid
`
`perception by the human eye. To decrease processing time, graphics processing systems
`
`typically divide primitive processing among several graphics processing circuits where,
`
`for example, one graphics processing circuit is responsible for one vertical strip (e.g. 13)
`
`of the frame while another graphics processing circuit is responsible for another vertical
`
`strip (e.g. 14) of the frame. In this manner, the pixel data is provided to the frame buffer
`
`within the required refresh time.
`
`[0005]
`
`Load balancing is a significant drawback associated with the partitioning
`
`systems as described above. Load balancing problems occur, for example, when all of
`
`the primitives 20-23 of a particular object or scene are located in one strip (e.g. strip 13)
`
`as illustrated in FIG. 1. When this occurs, only the graphics processing circuit
`
`responsible strip 13 is actively processing primitives; the remaining graphics processing
`
`circuits are idle. This results in a significant waste of computing resources as at most
`
`only half of the graphics processing circuits are operating. Consequently, graphics
`
`processing system performance is decreased as the system is only operating at a
`
`maximum of fifty percent capacity.
`
`TEXAS INSTRUMENTS EX. 1002 - 7/615
`
`

`
`020053
`
`[0006]
`
`Changing the width of the strips has been employed to counter the system
`
`performance problems. However, when the width of a strip is increased, the load
`
`balancing problem is enhanced as more primitives are located within a single strip;
`
`thereby, increasing the processing required of the graphics processing circuit responsible
`
`for that strip, while the remaining graphics processing circuits remain idle. When the
`
`width of the strip is decreased (e.g. four bits to two bits), cache (e. g. texture cache)
`
`efficiency is decreased as the number of cache lines employed in transferring data is
`
`reduced in proportion to the decreased width of the strip. In either case, graphics
`
`processing system performance is still decreased due to the idle graphics processing
`circuits.
`
`[0007]
`
`Frame based subdivision has been used to overcome the performance
`
`problems associated with conventional partitioning systems. In frame based subdivision,
`
`each graphics processor is responsible for processing an entire frame, not strips within the
`
`same frame. The graphics processors then alternate frames. However, frame subdivision
`
`introduces one or more frames of latency between the user and the screen, which is
`
`unacceptable in real—time interactive environments, for example, providing graphics for a
`
`flight simulator application.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0008]
`
`The present invention and the related advantages and benefits provided
`
`thereby, will be best appreciated and understood upon review of the following detailed
`
`description of a preferred embodiment, taken in conjunction with the following drawings,
`
`where like numerals represent like elements, in which:
`
`[0009]
`
`FIG. 1 is a schematic block diagram of a conventional display partitioned
`
`into several vertical strips:
`
`[0010]
`
`‘ FIG. 2 is a schematic block diagram of a graphics processing system
`
`employing an exemplary multi-pipeline graphics processing circuit according to one
`
`embodiment of the present invention;
`
`[0011]
`
`FIG. 3 is a schematic block diagram of a memory partitioned into an
`
`exemplary super-tile pattern according to the present invention;
`
`TEXAS INSTRUMENTS EX. 1002 - 8/615
`
`

`
`020053
`
`[0012]
`
`FIG. 4 is a schematic block diagram of a memory partitioned into a super-
`
`tilc pattern according to an alternate embodiment of the present invention;
`
`[0013]
`
`FIG. 5 is a schematic block diagram of an exemplary multi-pipeline
`
`graphics processing circuit used in a multi processor configuration according to an
`
`alternate embodiment of the present invention;
`
`[0014]
`
`FIG. 6 is a flow chart of the operations performed by the graphics
`
`processing circuit according to the present invention;
`
`[0015]
`
`FIG. 7 is a diagram illustrating a polygon bounding box to determine
`
`which, if a polygon fits in a tile or super tile; and
`
`[0016]
`
`FIG. 8 is a schematic block diagram of an exemplary multi-pipeline
`
`graphics processing circuit used in a multi processor configuration according to an
`
`alternate embodiment of the present invention.
`
`TEXAS INSTRUMENTS EX. 1002 - 9/615
`
`

`
`020053
`
`DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
`
`[0017]
`
`A multi—pipcline graphics processing circuit includes at least two pipelines
`
`operative to process data in a corresponding tile of a repeating tile pattern, a respective
`
`one of the at least two pipelines is operative to process data in a dedicated tile, wherein
`
`the repeating tile pattern includes a horizontally and vertically repeating pattern of square
`
`regions. The multi-pipeline graphics processing circuit may be coupled to a frame buffer
`
`that is subdivided into a replicating pattern of square regions (e.g. tiles), where each
`
`region is processed by a corresponding one of the at least two pipelines such that load
`
`balancing and texture cache utilization is enhanced.
`
`[0018]
`
`A multi-pipeline graphics processing method includes receiving vertex
`
`data for a primitive to be rendered, generating pixel data in response to the vertex data,
`
`determining the pixels within a set of tiles of a repeating tile pattern to be processed by a
`
`corresponding one of at least two graphics pipelines in response to the pixel data, the
`
`repeating tile pattern including a horizontally and vertically repeating pattern of square
`
`regions, and performing pixel operations on the pixels within the determined set of tiles
`
`by the corresponding one of the at least two graphics pipelines. An exemplary
`
`embodiment of the present invention will now be described with reference to Figures 2-6.
`
`[0019]
`
`FIG. 2 is a schematic block diagram of an exemplary graphics processing
`
`system 30 employing an example of a multi—pipcline graphics processing circuit 34
`
`according to one embodiment of the present invention. The graphics processing system
`
`30 can be implemented with a single graphics processing circuit 34 or with two or more
`
`graphics processing circuits 34, 54. The components and corresponding functionality of
`
`the graphics processing circuits 34, 54 are substantially the same. Therefore, only the
`
`structure and operation of graphics processing circuit 34 will be described in detail. An
`
`alternate embodiment, employing both graphics processing circuits 34 and 54 will be
`
`discussed in greater detail below with reference to FIGS. 4-5.
`
`[0020]
`
`Graphics data 31, for example, vertex data of a primitive (e.g. triangle) 80
`
`(FIG. 3) is transmitted as a series of strips to the graphics processing circuit 34. As used
`
`herein, graphics data 31 can also include video data or a combination of video data and
`
`graphics data. The graphics processing circuit 34 is preferably a portion of a stand-alone
`
`graphics processor chip or may also be integrated with a host processor or other circuit, if
`
`TEXAS INSTRUMENTS EX. 1002 - 10/615
`
`

`
`020053
`
`desired, or part of a larger system. The graphics data 31 is provided by a host (not
`
`shown). The host may be a system processor (not shown) or a graphics application
`
`running on the system processor. In an alternate embodiment, an Accelerated Graphics
`
`Port (AGP) 32 or other suitable port receives the graphics data 31 from theihost and
`provides the graphics data 31 to the graphics processing circuit 34 for further processing.
`
`[0021]
`
`The graphics processing circuit 34 includes a first graphics pipeline 101
`
`operative to process graphics data in a first set of tiles as discussed in greater detail
`
`below. The first pipeline 101 includes front end circuitry 35, a scan converter 37, and
`
`back end circuitry 39. The graphics processing circuit 34 also includes a second graphics
`
`pipeline 102, operative to process graphics data in a second set of tiles as discussed in
`
`greater detail below. The first graphics pipeline 101 and the second graphics pipeline
`
`102 operate independently of one another. The second graphics pipeline 102 includes the
`
`front end circuitry 35, a scan converter 40, and back end circuitry 42. Thus, the graphics
`
`processing circuit 34 of the present invention is configured as a multi—pipeline circuit,
`
`where the back end circuitry 39 of the first graphics pipeline 101 and the back end
`
`circuitry 42 of the second graphics pipeline 102 share the front end circuitry 35, in that
`
`the first and second graphics pipelines 101 and 102 receive the same pixel data 36
`
`provided by the front end circuitry 35. Alternatively, the back end circuitry 39 of the first
`
`graphics pipeline 101 and the back end circuitry 42 of the second pipeline 102 may be
`
`coupled to separate front end circuits. Additionally, it will be appreciated that a single
`
`graphics processing circuit can be configured in similar fashion to include more than two
`
`graphics pipelines. The illustrated graphics processing circuit 34 has the first andisecond
`
`pipelines 101-102 present on the same chip. However, in alternate embodiments, the first
`
`and second graphics pipelines 101-102 may be present on multiple chips interconnected
`
`by suitable communication circuitry or a communication path, for example, a
`
`synchronization signal or data bus interconnecting the respective memory controllers.
`
`[0022]
`
`The front end circuitry 35 may include, for example, a vertex shader, set
`
`up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31
`
`and generate pixel data 36 to be further processed by the back end circuitry 39 and 42,
`
`respectively. The front end circuitry 35 generates the pixel data 36 by performing, for
`
`example, clipping, lighting, spatial transformations, matrix operations and rasterizing
`
`TEXAS INSTRUMENTS EX. 1002 - 11/615
`
`

`
`\
`
`020053
`
`operations on the primitive data 31. The pixel data 36 is then transmitted to the
`
`respective scan converters 37 and 40 of the two graphics pipelines 101-102.
`
`[0023]
`
`The scan converter 37 of the first graphics pipeline 101 receives the pixel
`
`data 36 and sequentially provides the position (e.g. x, y) coordinates 60 in screen space of
`
`the pixels to be processed by the back end circuitry 39 by determining or identifying
`
`those pixels of the primitive, for example, the pixels within portions 81-82 of the triangle
`
`80 (FIG. 3) that intersect the tile or set of tiles that the back end circuitry 39 is
`
`responsible for processing. The particular tile(s) that the back end circuitry 39 is
`
`responsible for is determined based on the tile identification data present on the pixel
`
`identification line 38 of the scan converter 37. The pixel identification line 38 is
`
`illustrated as being hard wired to ground. Thus, the tile identification data corresponds to
`
`a logical zero. This corresponds to the back end circuitry 39 being responsible for
`
`processing the tiles labeled “A” (e.g. 72 and 75) in FIG. 3. Although the pixel
`
`identification line 38 is illustrated as being hard wired to a fixed value, it is to be
`
`understood and appreciated that the tile identification data can be programmable data, for
`
`example, from a suitable driver and such a configuration is contemplated by the present
`
`invention and is within the spirit and scope of the instant disclosure.
`
`[0024]
`
`Back end circuitry 39 may include, for example, pixel shaders, blending
`
`circuits, z-buffers or any other circuitry for performing pixel appearance attribute
`
`operations (e. g. color, texture blending, z-buffering) on those pixels located, for example,
`
`in tiles 72, 75 (FIG. 3) corresponding to the position coordinates 60 provided by the scan
`
`converter 37. The processed pixel data 43 is then transmitted to graphics memory 48 via
`memory controller 46 for storage therein at locations corresponding to the position
`coordinates 60.
`
`[0025]
`
`The scan converter 40 of the second graphics pipeline lO2, receives the
`
`pixel data 36 and sequentially provides position (e.g. x, y) coordinates 61 in screen space
`
`of the pixels to be processed by the back end circuitry 42 by determining those pixels of
`
`the primitive, for example, the pixels within portions 83-84 of the triangle 80 (FIG. 3)
`
`that intersect the tiles that the back end circuitry 42 is responsible for processing. Back
`
`end circuitry 42 tile responsibility is determined based on the tile identification data
`
`present on the pixel identification line 41 of the scan converter 41. The pixel
`
`TEXAS INSTRUMENTS EX. 1002 - 12/615
`
`

`
`_.
`
`.13;
`
`020053
`
`identification line 41 is illustrated as being hard wired to Vcc; thus, the tile identification
`
`data corresponds to a logical one. This corresponds to the back end circuitry 42 being
`
`responsible for processing the tiles labeled “B” (e.g. 73-74) in FIG. 3. Although the pixel
`
`identification line 41 is illustrated as being hard wired to a fixed value, it is to be
`understood and appreciated that the tile identification data can be programmable data, for
`
`example, from a suitable driver and such configuration is contemplated by the present
`
`invention and is within the spirit and scope of the instant disclosure.
`
`[0026]
`
`Back end circuitry 42 may include, for example, pixel shaders, blending
`
`circuits, z-buffers or any suitable circuitry for performing pixel appearance attribute
`
`operations on those pixels located, for example, in tiles 73 and 74 (FIG. 3) corresponding
`
`to the position coordinates 61 provided by the scan converter 40. The processed pixel
`
`data 44 is then transmitted to the graphics memory 48, via memory controller 46, for
`
`storage therein at locations corresponding to the position coordinates 61.
`
`[0027]
`
`The memory controller 46 is operative to transmit and receive the
`
`processed pixel data 43-44 from the back end circuitry 39 and 42; transmit and retrieve
`
`pixel data 49 from the graphics memory 48; and in a single circuit implementation,
`
`transmit pixel data 50 for presentation on a suitable display 51. The display 51 may be a
`
`monitor, a CRT, a high definition television (HDTV) or any other device or combination
`
`thereof.
`
`[0028]
`
`Graphics memory 48 may include, for example, a frame buffer that also
`
`stores one or more texture maps. Referring to FIG. 3, the frame buffer portion of the
`
`graphics memory 48 is partitioned in a repeating tile pattern of horizontal and vertical
`
`square regions or tiles 72-75, where the regions 72-75 provide a two dimensional
`
`partitioning of the frame buffer portion of the memory 48. Each tile is implemented as a
`
`16 x 16 pixel array. The repeating tile pattern of the frame buffer 48 corresponds to the
`
`partitioning of the corresponding display 51 (FIG. 2). When rendering a primitive (e.g.
`
`triangle) 80, the first graphics pipeline 101 processes only those pixels in portions 81, 82
`
`of the primitive 80 that intersects tiles labeled “A”, for example, 72 and 75, as the back
`
`end circuitry 39 is responsible for the processing of tiles corresponding to tile
`
`identification () present on pixel identification line 38 (FIG. 2). In corresponding fashion,
`
`the second graphics pipeline 102 processes only those pixels in portions 83, 84 of the
`
`TEXAS INSTRUMENTS EX. 1002 - 13/615
`
`

`
`020053
`
`primitive 80 that intersects tiles labeled “B”, for example 73-74, as the back end circuitry
`
`42 (FIG. 2) is responsible for the processing of tiles corresponding to tile identification 1
`
`present on pixel identification line 41 (FIG. 2).
`
`[0029]
`
`By configuring the frame buffer 48 according to the present invention, as
`
`the primitive data 31 is typically written in strips, the tiles (e.g. 72 and 75) being
`
`processed by the first graphics pipeline 101 and the tiles (e.g. 73 and 74) being processed
`
`by the second graphics pipeline 102 will be substantially equal in size, notwithstanding
`
`the primitive 80 orientation. Thus, the amount of processing performed by the first
`
`graphics pipeline 101 and the second graphics pipeline 102, respectively, are
`
`substantially equal; thereby, effectively eliminating the load balance problems exhibited
`
`by conventional techniques.
`
`I [0030]
`
`FIG. 4 is a schematic block diagram of a frame buffer 68 partitioned into a
`
`super-tile pattern according to an alternate embodiment of the present invention. Such a
`
`partitioning would be used, for example, in conj unetion with a multi-processor
`
`implementation to be discussed below with reference to FIG. 5. As illustrated, the frame
`
`buffer 68 is partitioned into a repeating tile pattern where the tiles, for example, 92-99
`
`that form the repeating tile pattern are the responsibility of and processed by a
`
`corresponding one of the graphics pipelines provided by the multi-processor
`
`implementation.
`
`[0031]
`
`FIG. 5 is a schematic block diagram of a graphics processing circuit 54
`
`which may be coupled with the graphics processing circuit 34 (FIG. 2), for example, by
`
`the AGP 32 or other suitable port, to form one embodiment of a multi-proces