`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313- 1450
`www.uspto.gov
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`APPLICATION NO.
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`F ING DATE
`
`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`CONF {MATION NO.
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`10/459,797
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`06/12/2003
`
`Mark M. Leather
`
`00100.02.0053
`
`4148
`
`29153
`7590
`06/26/2014
`ADVANCED MICRO DEVICES,INC.
`C/O Faegre Baker Daniels LLP
`311 S. WACKER DRIVE
`CHICAGO, IL 60606
`
`RICHER, JONI
`
`2611
`
`06/26/2014
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`Notice of the Office communication was sent electronically on aboVe—indicated "Notification Date" to the
`following e—mail address(es):
`
`inteas @ faegrebdcom
`michelle.daVis @ faegrebd. com
`cynthia.pays0n @ faegrebdcom
`
`PTOL—90A (Rev. 04/07)
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`UNIFIED 1015
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`UNIFIED 1015
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`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Ex parte MARC M. LEATHER and ERIC DEMERS
`
`Appeal 2011—O10197
`Application 10/459,797
`Technology Center 2600
`
`Before ROBERT E. NAPPI, JASON V. MORGAN, and J. JOHN LEE,
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`Administrative Patent Judges.
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`NAPPI, Administrative Patent Judge.
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`DECISION ON APPEAL
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`This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
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`of claims 1 through 7, 10 through 22, 24, and 25.
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`We affir1n—in—part.
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`INVENTION
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`The invention is directed to a graphics processing circuit that includes
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`at least two pipelines operative to process data in a corresponding set of tiles
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`of a repeating tile pattern, a respective one of the at least two pipelines
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`operative to process data in a dedicated tile. See Abstract of Appellants’
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`Specification. Claim 1 is illustrative of the invention and reproduced below:
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`
`
`Appeal 2011-010197
`Application 10/459,797
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`1. A graphics processing circuit, comprising:
`at least two graphics pipelines on a same chip operative to
`process data in a corresponding set of tiles of a repeating tile
`pattern corresponding to screen locations, a respective one of
`the at least two graphics pipelines operative to process data in a
`dedicated tile; and
`
`a memory controller on the chip in communication with the
`at least two graphics pipelines, operative to transfer pixel data
`between each of a first pipeline and a second pipeline and a
`memory shared among the at least two graphics pipelines;
`wherein the repeating tile pattern includes a horizontally and
`vertically repeating pattern of square regions.
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`REJECTIONS AT ISSUE
`
`The Examiner has rejected claims 1 through 4, 7, 10, 12, 14, and 25
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`under 35 U.S.C. § 103 (a) as unpatentable over Maclnnis (U.S. 6,570,579
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`B1; May 27, 2003) and Perego (U.S. 6,864,896 B2; Mar. 8, 2005). Answer
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`4-8.1
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`The Examiner has rejected claims 5, 18, and 24 under 35 U.S.C.
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`§ 103(a) as unpatentable over Maclnnis, Perego, and Kelleher (U.S.
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`5,794,016; Aug. 11, 1998). Answer 8-12.
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`The Examiner has rejected claims 6 and 17 under 35 U.S.C. § 103 (a)
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`as unpatentable over Maclnnis, Perego, and Furtner (U.S. 6,778,177 B1;
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`Aug. 17, 2004). Answer 12-13.
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`The Examiner has rejected claims 11, 13, 15, and 16 under 35 U.S.C.
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`§ 103(a) as unpatentable over Maclnnis, Perego, Kelleher, and Hamburg
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`(U.S. 5,905,506; May 18, 1999). Answer 13-14.
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`1 Throughout this opinion we refer to the Appeal Brief dated February 22,
`2011, Reply Brief dated June 6, 2011, and the Examiner’s Answer mailed on
`April 5, 2011.
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`
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`Appeal 2011—O10197
`Application 10/459,797
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`The Examiner has rejected claim 19 under 35 U.S.C. § 103(a) as
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`unpatentable over Maclnnis, Perego, Furtner and Kent (US 2003/0164830
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`A1; Sept. 4, 2003). Answer 14-16.
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`The Examiner has rejected claims 20 through 22 under 35 U.S.C.
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`§ 103(a) as unpatentable over Perego. Answer 16-18.
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`Rejection independent claims 1 and 25.
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`ISSUES
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`Appellants argue on pages 16 through 22 of the Appeal Brief and
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`pages 1 and 2 of the Reply Brief, the Examiner’s rejection of independent
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`claims 1 and 25 is in error. The dispositive issue presented by this argument
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`is: Did the Examiner err in finding that the combination of Maclnnis and
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`Perego teach a memory shared among the graphics pipelines?
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`Rejection independent claim 20.
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`Appellants argue on pages 27 and 28 of the Appeal Brief that the
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`Examiner’s rejection of claim 20 is in error. Appellants’ argument with
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`respect to this claim presents us with the issue: did the Examiner err in
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`finding that Perego teaches passing the same pixel data to both of the
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`graphics pipelines on the same chip?
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`Rejection independent claim 24.
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`Appellants argue on pages 22 and 23 of the Appeal Brief that the
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`Examiner’s rejection of claim 24 is in error. Appellants’ argument with
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`respect to this claim present us with the issue: did the Examiner err in
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`
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`Appeal 2011—O10197
`Application 10/459,797
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`finding that the combination of Maclnnis, Perego, and Kelleher teaches both
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`the front end and the back end circuitry on the same chip as claimed?
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`ANALYSIS
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`We have reviewed Appellants’ arguments in the Briefs, the
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`Examiner’s rejection and the Examiner’s response to the Appellants’
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`arguments. We agree with Appellants’ conclusion that the Examiner erred
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`rejecting claims 1 through 7, 10 through 22, and 25 under 35 U.S.C. § lO3(a)
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`but disagree with Appellants’ conclusion the Examiner erred in rejecting
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`claim 24 under 35 U.S.C. § 103(a).
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`Rejection independent claims 1 and 25.
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`The Examiner’s response, to Appellants’ arguments directed to the
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`rejection of these claims, cites to Perego’s teaching of memory (item 314 of
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`Figure 3) which the Examiner finds is shared between the pipelines (items
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`312 of Figure 3). Answer 4, 5, 19, and 20. We disagree with the
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`Examiner’s finding. As argued by Appellants on page 17 of the Appeal
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`Brief, Perego teaches item 314 is a shared memory, but it is shared between
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`the CPU and the individual rendering engines and not shared among the
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`rendering engines (which the Examiner equates to graphics pipelines) as
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`claimed. The Examiner has not found that Maclnnis teaches this feature.
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`Thus, we do not find the Examiner has shown that combination of Maclnnis
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`and Perego teaches all of the limitations of independent claims 1 and 25.
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`Accordingly, we will not sustain the Examiner’s rejection of claims 1
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`
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`Appeal 2011—010197
`Application 10/459,797
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`through 4, 7, 10, 12, 14, and 25 under 35 U.S.C. § 103(a) as unpatentable
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`over Maclnnis and Perego.
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`The Examiner has not found that Kelleher, Furtner, Kent, or Hamburg
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`teaches the shared memory as recited in independent claims 1. Accordingly,
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`we similarly will not sustain the Examiner’s rejection of claims 5, 6, 11, 13,
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`and 15 through 19 under 35 U.S.C. § 103(a)
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`Rejection independent claim 20.
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`The Examiner’s response to Appellants’ arguments directed to the
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`rejection of claim 20 cites to Perego’s teaching of the CPU (item 308 Figure
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`3) generating the pixel data through the graphic controller (item 310) to the
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`rendering engines (item 312). Answer 23-24. We disagree with the
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`Examiner’s finding. As argued by Appellants, on page 28 of the Appeal
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`Brief, Perego teaches each rendering engine receives different portions of
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`the processing task. Thus, we do not find the Examiner has shown that
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`Perego teaches or makes obvious all of the limitations of independent claim
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`20. Accordingly we will not sustain the Examiner’s rejection of claims 20
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`through 22 under 35 U.S.C. § 103 (a) as unpatentable over Perego, Furtner
`
`and Kent.
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`Rejection independent claim 24.
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`The Examiner’s response, to Appellants’ arguments directed to the
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`rejection of claim 24, cites to Perego’s teaching in Figure 8 that two
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`different rendering engines, which the Examiner equates with the claimed
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`back end circuitry, are within the same memory module or chip. Answer 22.
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`Further, the Examiner finds that Maclnnis teaches that a common front end
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`Appeal 201 l—Ol0l97
`Application l0/459,797
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`circuitry, a back end circuitry, and a memory controller are on the same
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`chip. Answer 9, 10, and 22. Appellants’ arguments, directed to the rejection
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`of claim 24, do not address the teachings of Maclnnis or the combined
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`teachings. Rather Appellants only assert that Perego does not teach the front
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`end and back end circuitry on the same chip as claimed. Thus, Appellants’
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`arguments directed to the rejection of independent claim 24 have not
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`persuaded us of error in the Examiner’s rejection as it has not addressed the
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`combined teachings of the references. Accordingly, we sustain the
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`Examiner’s rejection of claim 24 under 35 U.S.C. § 103 (a) as unpatentable
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`over Maclnnis, Perego, and Kelleher.
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`DECISION
`
`The decision of the Examiner to reject claims 1 through 7, 10 through
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`22, 24, and 25 is affinned—in—part.
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`No time period for taking any subsequent action in connection with
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`this appeal may be extended under 37 C.F.R. § l.l36(a)(l)(iV).
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`AFFIRMED-IN-PART
`
`ELD