`
`BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES
`
`In re application of:
`Mark M. Leather et al.
`
`Examiner: Joni Hsu
`
`Application No.: 10/459,797
`
`Group Art Unit: 2628
`
`Filed:
`
`June 12, 2003
`
`Docket No.: 00100.02.0053
`
`For: DIVIDING WORK AMONG
`
`MULTIPLE GRAPHICS
`
`PIPELINES USING A SUPER-
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`TILING TECHNIQUE
`
`APPELLANTS’ REPLY BRIEF IN RESPONSE TO EXAMINER’S ANSWER
`
`Dear Sir:
`
`Appellants wish to thank the Examiner for the “Response to Argument” set forth in the
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`Examiner’s Answer. Appellants respectfully reiterate their prior remarks as it appears that the
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`claim construction and teachings of Perego are incorrect. Appellants again respectfully submit
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`that the claims must be reasonably interpreted in View of the Specification and that the claims
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`themselves contradict the Examiner’s construction as do the actual teachings of the Perego
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`reference which were not addressed in the Examiner’s “Response to Arguments” section. Claim
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`1, for example, recites the memory controller on the chip in communication with at least two
`
`graphics pipelines, operative to transfer pixel data between each of the first pipeline and a second
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`pipeline in a memory shared among the at least two graphics pipelines... As such, the same
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`memory controller that is on the chip is in communication with two graphics pipelines and the
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`memory is shared among the at least two graphics pipelines. The Examiner’s position appears to
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`overlook what the Perego reference actually teaches as being shared. What is shared in Perego is
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`memory between a CPU and a single rendering engine which is specifically described and shown
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`in Perego as a memory module 304 or 804 including a rendering engine 312 and dedicated
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`CHICAGO/#2207470.1
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`U N I 1 4
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`UNIFIED 1014
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`
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`memory that the CPU can access but no other rendering engine can access. Only a single
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`rendering engine can access the memory on a memory module.
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`FIG. 8 clearly shows this structure since each rendering engine only has access to its own
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`memory devices. Appellants claim a different configuration wherein the same memory
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`controller on a chip is in communication with shared memory that is shared between two
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`graphics processors. The graphics rendering engines in Perego cannot share memory amongst
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`graphics engines and do not incorporate a common memory controller to do so. Perego uses the
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`term “shared memory” because a portion of the memory on each separate memory module is
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`used by the CPU, the claims do not claim such an operation but instead claim that the memory
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`controller on the chip is in communication with multiple graphics pipelines and transfers pixel
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`data between each of the pipelines and the memory controller that is in communication with a
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`memory shared among the at least two graphics pipelines. Multiple rendering engines in Perego
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`do not share the same graphics memory through a common memory controller on a chip as
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`alleged in the office action. Accordingly, Appellants respectfully reversal of the rejections.
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`Appellants also respectfully reas sert their other remarks from their Brief.
`
`Respectfully submitted,
`
`By:
`
`/Christopher J. Reckamp/
`Christopher J. Reckamp
`Registration No. 34,414
`
`Date:
`
`
`June 6 2011
`
`Vedder Price P.C.
`
`222 N. LaSalle Street
`
`Chicago, Illinois 60601
`PHONE:
`(312) 609-7599
`
`FAX:
`
`(312) 609-5005
`
`CHICAGO/#2207470.1
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