throbber
United States Patent [19]
`
`Riseman
`
`'
`
`[11]
`[45]
`
`4,106,050
`Aug. 8, 1978
`
`[54] INTEGRATED CIRCUIT STRUCTURE WITH
`FULLY ENCLOSED AIR ISOLATION
`[75] Inventor:
`Jacob Risernan, Poughkeepsie, NY.
`[73] Assignee:
`International Business Machines
`Corporation, Armonk, NY.
`[21] Appl. No.: 719,888
`[22] Filed:
`Sep. 2, 1976
`
`[51] Int. Cl.2 ........................................... .. H01L 27/04
`[52] US. Cl. .................. ..
`[58] Field of Search ...................... .. 357/49, 47, 50, 55
`[56]
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,332,137
`3,489,961
`3,513,022
`3,647,585
`
`7/1967 Kenney ............................ .. 357/49 X
`l/ 1970 Frescura et al. ............. .. 357/49 X
`5/1970 Casterline et al. ..
`357/49 X
`3/1972 Fritzinger et al. ................... .. 156/17
`
`3,689,992
`9/1972 Schutze et al. ...................... .. 29/577
`3,787,710
`l/1974 Cunningham
`357/49 X
`3,905,037
`9/1975 Bean et al. ........................... .. 357/60
`Primary Examiner-Stanley D. Miller, Jr.
`Assistant Examiner-James W. Davie
`Attorney, Agent, or Firm—-Julius B. Kraft; Theodore E.
`Galanthay
`ABSTRACT
`[57]
`An integrated circuit member structure comprising a
`semiconductor substrate having formed therein a pat
`tern of cavities extending from one surface of the sub
`strate into the substrate and fully enclosed within said
`member, a plurality of pockets of semiconductor mate
`rial extending from said substrate laterally surrounded
`and electrically insulated by said cavities and a planar
`layer of electrically insulative material on said surface.
`
`5 Claims, 8 Drawing Figures
`
`001
`
`Petitioner Samsung - SAM1009
`
`

`
`U. S. Patent
`
`Aug. s, 1978
`
`Sheetl 0f2
`
`4,106,050
`
`002
`
`

`
`U. S. Patent
`
`Aug. s, 1978 I Sl-1eet2 of2
`
`4,106,050
`
`,
`
`,
`
`,
`
`,
`._
`
`,1
`
`/ M20
`22
`
`FIG. 4A
`
`
`
`NAN N :LN-bo [\D
`
`003
`
`

`
`INTEGRATED CIRCUIT STRUCTURE WITH
`FULLY ENCLOSED AIR ISOLATION
`
`15
`
`25
`
`35
`
`BACKGROUND OF THE INVENTION
`The present invention relates to integrated circuit
`structures and more particularly to dielectric isolation
`in such integrated circuit structures, particularly by
`air-isolation.
`The form of most existing integrated circuits is the
`so-called monolithic form. Such a structure contains
`great numbers of active and passive devices in a block
`or monolith of semiconductor material. Electrical con
`nections between these active and passive devices are
`generally made on a surface of the semiconductor block
`of material. Until recently, junction isolation has been
`by far the most widely practiced manner of isolating
`devices or circuits in the integrated circuit from each
`other. For example, active P-type diffusions are custom
`arily used to isolate conventional FET and bipolar de
`vices from one another and from other devices such as
`the resistors and capacitors. Such junction isolation is
`also used in integrated circuits utilizing ?eld effect tran
`sistor devices. More detailed descriptions of junction
`isolation may be found in U.S. Pat. Nos. 3,319,311;
`3,451,866; 3,508,209 and 3,539,876.
`Although junction isolation has provided excellent
`electrical isolation in integrated circuits which have
`functioned very effectively over the years, at the pres
`ent stage of the development of the integrated circuit
`art, there is an increasing demand in the ?eld of digital
`integrated circuits for faster switching circuits. It has
`long been recognized that the capacitive effect of the
`isolating P-N junctions has a slowing effect on the
`switching speed of the integrated circuits. Until re
`cently, the switching demands of the integrated circuits
`have been of a suf?ciently low frequency that the ca
`pacitive effect in junction isolation has presented no‘
`major problems. However, with the higher frequency
`switching demand which can be expected in the ?eld in
`the future, the capacitive effect produced by junction
`isolation may be an increasing problem. In addition,
`junction isolation requires relatively large spacing be
`tween devices, and, thus, relatively low device densities
`which is contrary to higher device densities required in
`large scale integration. Junction isolation also tends to
`give rise to parasitic transistor effects between the isola
`tion region and its two abutting regions. Consequently,
`in recent years there has been a revival of interest in
`integrated circuits having dielectric isolation instead of 50
`junction isolation. In such dielectrically isolated cir
`cuits, the semiconductor devices are isolated from each
`other by insulative dielectric materials or by air.
`conventionally, such dielectric isolation in integrated
`circuits has been formed by etching channels in a semi
`conductor member corresponding to the isolation re
`gions from the back side of the member, i.e., the side
`opposite to the planar surface at which the devices and
`wiring of the integrated circuit are to be formed. This
`leaves an irregular or channeled surface over which a
`substrate back side, usually a composite of a thin dielec
`tric layer forming the interface with the semiconductor
`member covered by a thicker layer of polycrystalline
`silicon is deposited. Alternatively, the polycrystalline
`silicon need not be deposited in which case, the chan
`nels would provide air-isolation. Next, the other or
`planar surface of the semiconductor member may be
`either mechanically ground down or chemically etched
`
`45
`
`55
`
`60
`
`65
`
`1
`
`. 4,106,050
`
`2
`until the bottom portions of the previously etched chan
`nels are reached. This leaves the structure wherein a
`plurality of pockets of semiconductor material sur
`rounded by a thin dielectric layer are either supported
`on a polycrystalline silicon substrate and separated from
`each other by the extensions of the polycrystalline sub
`strate or in the absence of the polysilicon, a structure in
`which the pockets of semiconductor material are, in
`effect, “air-isolated” from each other. While such struc
`tures provide an essentially ?at and thus wirable planar
`surface of coplanar pockets of semiconductor material,
`such integrated circuit structures have limited utility
`with integrated circuits of high device densities. This is
`due to the fact that the etched channels which corre
`spond to the isolation regions must be formed from the
`back side of the integrated circuit substrate and etched
`until the level of the active planar‘ surface of the sub
`strate is reached.
`It is recognized in the art that when etching from the
`back side of an integrated circuit member the etching
`must be made to greater depth than when etching di
`rectly from the planar front surface in order to insure
`uniform lateral isolation. It is- also recognized that when
`etching through a member, the extent of lateral etching
`will be substantially the same as the depth of etching.
`Accordingly, when etching channels from the back side
`of the substrate, so much lateral “real estate” is con
`sumed on the wafer that such an approach has very
`limited practicality in high density integrated circuits.
`On the other hand, if the etching to form the channels
`in the above dielectric isolation or air-isolation structure
`is carried out from the active or front surface of the
`integrated circuit, only limited lateral vetching is neces
`sary to reach practical isolation depths. However, the
`result is an essentially corrugated active surface rather
`than a planar one. Such a corrugated active surface is,
`of course, difficult to wire, i.e., form integrated circuit
`metallurgy interconnections by conventional photo
`lithographic integrated circuit fabrication techniques.
`Another approach which has been utilized for form
`ing lateral dielectric isolation in the art involves the
`formation of recessed silicon dioxide lateral isolation
`regions, usually in the eptitaxial layer where the semi
`conductor devices are to be formed, through the expe
`dient of ?rst selectively etching a pattern of recesses in
`the layer of silicon, and then thermally oxidizing the
`silicon in the recesses with appropriate oxidation block
`ing masks, e.g., silicon nitride masks, to form recessed
`or inset regions of silicon dioxide which provide the
`lateral electrical isolation. Representative of the prior
`art teaching in this area are U.S. Pat. No. 3,648,125 and
`an article entitled, “Locos Devices,” E. Kooi et al.,
`Philips Research Report 26, pp. 166 - 180 (1971).
`While this approach has provided both planarity at
`the active device integrated circuit surface as well as
`good lateral dielectric isolation, it has encountered
`some problems. Originally, the art applied the silicon
`nitride masks directly onto the silicon substrates. This
`gave rise to problems associated-with high stresses cre
`ated on the underlying silicon substrate by the silicon
`nitride-silicon interface. Such stresses were found in
`many cases to produce dislocations in the silicon sub
`strate which appear to result in undesirable leakage
`current pipes and otherwise adversely affect the electri
`cal characteristics of the interface. In order to minimize
`such interface stresses with silicon nitride layers, it has
`become the practice in the art to form a thin layer of
`silicon dioxide. between the silicon substrate and the
`
`004
`
`

`
`4,106,050
`3
`4
`silicon nitride layer. During such thermal oxidation,
`position including those described in Volume 10, pp.
`there is a substantial additional lateral penetration of
`533 - 546, of the Encyclopedia of Chemical Technol
`silicon oxide from the thermal oxidation beneath the
`ogy, Kirk and Othmer, Second Edition, published in
`silicon nitride. This lateral penetration is greatest at the
`1966 by Interscience Publishers. However, the silicate
`mask-substrate interface to provide a laterally sloping
`glasses, such as those described on pp. 540 - 545 in the
`structure known and recognized in the prior art as the
`above encyclopedia, have been found‘ to be particularly _
`undesirable, “bird’s beak.”
`desirable. The term “siliceous glass” as used in this
`The publications, “Local Oxidation of Silicon; New
`application, is meant to include all silica-containing
`Technological Aspects,” by J. A. Appels et al., Philips
`glasses including glasses which are substantially unmod
`Research Report 26, pp. 157 - 165, June 1971, and “Se
`i?ed silica (SiOZ). In addition, among the silicate glasses
`lective Oxidation of Silicon and Its Device Applica
`which may be used are alkali silicate glasses which are
`tion,” E. Kooi et al., Semiconductor Silicon 1973, pub
`modi?ed by NazO, soda-lime glasses, borosilicate
`lished by the Electrochemical Society, Edited by H. R.
`glasses, alumino-silicate glasses, and lead glasses. Then, '
`Huff and R. R. Burgess, pp. 860 — 879, are representa
`the two substrates are bonded together by fusing the
`tive of the recognition in the prior art of the “bird’s
`planar layer over the second substrate to the silicon
`beak” problems associated with silicon dioxide-silicon
`dioxide layer over the ?rst substrate to thereby fully
`nitride composite masks, particularly when used in the
`enclose the cavities. Finally, the second silicon substrate
`formation of recessed silicon dioxide by thermal oxida
`is removed from the fused structure.
`tion. Because of such “bird’s beak” problems, the art has
`The resulting structure is one having a planar surface,
`experienced some dif?culty in achieving well-de?ned
`at which the active devices of the integrated circuit may
`lateral isolation boundaries.
`be subsequently formed, i.e., the surface of the ?rst
`In addition, while, as previously mentioned, air isola
`silicon substrate covered by the planar layer of silicon
`tion has been used in the prior art in integrated circuits,
`dioxide. Further, since the cavities have been formed by
`no practical approach has been developed for the appli
`etching down from this surface rather than the back side
`cation of air isolation to high density, large scale inte
`surface of the structure, only minimal lateral integrated
`grated circuits.
`circuit “real estate” has been consumed in forming such
`cavities. In addition, the back side surface of the struc
`ture remains unetched and thus planar. Finally, because
`of the fully enclosed air-isolation, the structure has
`cavities capable of absorbing changes in volume of the
`silicon material resulting from the application of heat
`during the processing steps. Thus, heat-induced stresses
`are minimized.
`>
`The foregoing and other objects, features and advan
`tages of the invention will be apparent from the follow
`ing more particular description of the preferred embodi
`ments of the invention, as illustrated in the accompany
`ing drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`20
`
`25
`
`35
`
`SUMMARY OF THE INVENTION
`Accordingly, it is an object of the present invention
`to provide an air-isolated integrated circuit structure
`with a planar wirable surface.
`It is another object of the present invention to pro
`vide an air-isolated integrated circuit structure in which
`the air isolation regions are of minimal dimensions so
`that the integrated circuit structure is adaptable to high
`device density integrated circuits.
`It is a further object of the present invention to pro
`vide an air-isolated integrated circuit structure in which
`both the upper and lower surfaces of the structure are
`planar.
`'
`It is yet a further object of the present invention to
`provide a dielectrically isolated integrated circuit struc
`ture in which both upper and lower surfaces are planar
`and which is substantially free from stresses created by
`changes in volume in the semiconductor material dur
`45
`ing integrated circuit fabrication heating steps.
`It is an even further object of the present invention to
`provide a method for fabricating an integrated circuit
`structure having the above described advantages.
`In accordance with the present invention, there is
`provided an integrated circuit member comprising a
`semiconductor substrate having formed therein a pat
`tern of cavities extending from one surface of the sub
`strate into the substrate and fully enclosed within the
`member, a plurality of pockets of semiconductor mate
`rial extending from said surface laterally surrounded
`and electrically insulated by said cavities and a planar
`layer of electrically insulative material on the surface.
`The integrated circuit member is formed by a fabrica
`tion method comprising ?rst etching a pattern of cavi
`ties extending from one surface of a ?rst silicon sub
`strate into the substrate; the cavities laterally surround
`and electrically isolate the plurality of silicon substrate
`pockets. Next, a ?rst layer of silicon dioxide is formed
`on this ?rst substrate surface. There is also formed over
`a second silicon substrate a planar second layer com
`prising a glass, and preferably a siliceous glass. The
`glass composition may be any conventional glass com
`
`FIGS. 1 — 7 are diagrammatic sectional views of a
`portion of an integrated circuit in order to illustrate the
`method of forming the preferred embodiment of the
`present invention.
`PREFERRED EMBODIMENTS OF THE
`PRESENT INVENTION
`FIGS. 1 — 7 illustrate the preferred embodiment of
`the present invention. On a suitable P- wafer 10 having
`a resistivity of 10 ohm/cm, an N+ region 11 which will
`subsequently serve as a subcollector is formed by con
`ventional thermal diffusion of impurities as set forth for
`example in U.S. Pat. No. 3,539,876. When introduced
`into substrate 10, N+ region 11 has a surface concentra
`tion of 1021 atoms/cm3. Region 11 may also be formed
`by conventional ion implantation techniques.
`Then, FIG. 2, a pattern of recesses or cavities 12 are
`etched in the substrate. This pattern of recesses corre
`sponds to the desired air-isolation pattern for the inte
`grated circuit structure. Recesses 12 are formed by
`etching utilizing a conventional mask such as a silicon
`dioxide mask formed by standard photolithographic
`integrated circuit fabrication techniques which mask
`has apertures corresponding to the recessed pattern to
`be formed. Then, the substrate may be etched in the
`conventional manner through the apertures de?ned in
`the silicon dioxide mask.
`
`55
`
`60
`
`65
`
`005
`
`

`
`10
`
`15
`
`20
`
`25
`
`5
`It should be noted that these recesses may be formed
`utilizing a conventional etchant for silicon such as a
`composition of nitric acid and diluted hydro?uoric acid
`in which case they will have the conventional sloped or
`tapered shape of recesses etched in silicon. Alterna
`tively, they may be formed by a technique of vertical
`walled etching as described in the aforementioned
`R.C.A. Review article, June 1970, particularly at pages
`272 — 275, wherein the substrate 10 should have a (110)
`surface orientation and the etchant utilized would be a
`boiling mixture of 100 grams KOH in 100 cc of water in
`which case recesses 12 will have the substantially verti
`cal-walled structure. For purposes of the present illus
`tration, recesses 12 are in the order of 2 microns in
`depth.
`Next, FIG. 3, utilizing conventional integrated circuit
`fabrication techniques, N-type epitaxial‘layer 13 is de
`posited over the substrate. Epitaxial layer 13 has a maxi
`mum impurity concentration or doping level of 1018
`atoms/cm3 and is deposited by conventional techniques
`at a temperature in the order of from 950° — 1150° C.
`During the deposition of epitaxiallayer 13, portions of
`the layer 13’ are deposited in cavities 12. Layer 13 has a
`thickness of about 2 microns. It should be noted that if
`it is considered desirable in the integrated circuit struc
`ture to avoid deposition of epitaxial layer portions 13’ in
`the'cavities 12, epitaxial layer 13 may be deposited im
`mediately after Step 1 and prior to the formation of the
`cavities in Step 2. In such a case, cavities 12 should be
`etched to a depth beyond the P—/N+ junction. Since
`substrate 10 is P-—, it may be subject to conventional
`surface inversion problems well-known in the art in
`certain integrated circuit applications. A higher concen
`tration of P dopant may be introduced in those portions
`of cavity 12 abutting substrate 10 by standard impurity
`introduction techniques such as diffusion or ion implan
`tation subsequent to the formation of the trench but
`prior to the formation of silicon dioxide layer 14.
`Next, FIG. 4, a layer of silicon dioxide 14 referably
`having a thickness in the order of from 3000 R — 10,000
`A is formed over the surface as shown using any con
`ventional silicon dioxide formation technique such as
`chemical vapor deposition or RF sputter deposition, or
`preferably, by standard thermal oxidation.
`Next, as shown in FIG. 4A, a layer of silicon dioxide
`20 which is to provide the planar surface of the inte
`grated circuit structure is deposited on a separate wafer
`21 of silicon. Wafer 21 should be as thin as possible but
`still be handleable without breakage. Wafer 21 may be
`either monocrystalline or polycrystalline silicon. Such a
`thickness may be conveniently between 3 and 5 mils.
`Silicon dioxide layer 20 which has a thickness in the
`order from % to 3 microns may be formed by any of the
`conventional techniques for forming silicon dioxide on
`a semiconductor substrate, e.g., chemical vapor deposi
`tion, sputter deposition or thermal oxidation of the sili
`con substrate. However, in accordance with one aspect
`of the present invention which will be described in the
`present embodiment, it .may be desirable to have an
`intermediate layer of an etch barrier material such as
`silicon nitride between silicon substrate 21 and silicon
`dioxide layer 20. As will be hereinafter described, when
`silicon substrate 21 is removed by chemical etching,
`silicon nitride is somewhat more resistant to conven~
`tional silicon etchants than is silicon dioxide, although
`65
`silicon dioxide is also resistant to such etchants and may
`be used alone without the nitride. In any event, if, as in
`FIG. 4A, silicon nitride is to be used, a layer 22 having
`
`4, 106,050
`a thickness in the order of from 1000 A — 2000 A may be
`formed by any conventional technique such as the
`chemical vapor deposition reaction of silane and ammo
`nia. Alternatively, silicon nitride layer 22; may be depos
`ited by conventional RF sputter deposition techniques.
`At this point, the structure of FIG. 4A is abutted
`against the structure of FIG. 4 and silicon dioxide layer
`20 is fused to'silicon dioxide layer 14. to fully enclose
`cavity patter-n12.
`‘
`_
`The fusion of layers 14 and 20 may be achieved 'by
`heating the abutting structure in the steam atmosphere '
`at temperatures in the order of 1200° C for about one;
`half hour. Alternatively, fusion temperature may‘ be
`reduced by forming a thin layer of phosphosilicate glass- '7
`or borosilicate glass on the surfaces of either silicon
`dioxide layers 14 and 20. This may be accomplished by
`the simple expedient of slightly etching the surfaces of
`layers 14 and 20 prior to the fusion step to make these
`layers hydrophilic and then depositing a small amount
`of either boric acid solution (saturated aqueous boric
`acid solution) or dilute phosphoric acid solution on
`either or both of the layers 14 and 20. This results in a
`thin layer of either borosilicate or phosphosilicate glass
`being formed on the surface of the silicon dioxide layers
`thus treated. These glasses may also be formed by dop
`ing with boron or silicon in the conventional manner.
`When such a thin borosilicate or- phosphosilicate glass
`layer is formed on the surface, the fusion step maybe
`then carried out at a lower temperature in theorder of
`1 100° C by heating in an oxidizing ambient, e. g., heating
`in steam for about 15 minutes followed by heating in dry ,
`oxygen for about 15 minutes to complete the fusion.
`Alternatively, the slight etch to make one of the layers
`hydrophilic may be used alone to similarly reduce the
`required fusion temperatures.
`In a variation of the illustrated embodiment, any
`standard borosilicate or phosphosilicate glass having a
`high melting point of at least 1100° C may be used in
`place of silicon dioxide to provide the siliceous material
`of layer 20. This high temperature glass may be depos—
`ited by any conventional technique such as sedimenta
`tion, RF sputtering or vapor phase deposition.
`Silicon substrate 21 is then removed and silicon ni
`tride layer 22 optionally removed to provide the struc
`ture shown in FIG. 6 wherein silicon dioxide layer 20
`provides a planar surface over the entire structure fully
`enclosing air-isolation cavity pattern 12. Silicon wafer
`21 may be removed by any combination of conventional
`wafer polishing, grinding or etching techniques. Most
`conveniently, most of the upper portion of substrate 21, '
`FIG. 5, may be ?rst removed by any conventional pol
`ishing or grinding technique followed by any conven
`tional etching technique including chemical etching or
`sputter etching with either nonreactive or reactive ions.
`As set forth previously, the etching may be carried out
`using selected etchants or etching techniques to which
`either the silicon nitride layer 22 if used or the silicon
`dioxide layer 20 is more resistant than is silicon wafer
`21. If present, the silicon nitride layer 22 may be option
`ally removed using a conventional etchant for silicon
`nitride to which the silicon dioxide is resistant. Such a
`conventional etchant for silicon nitride is hot phos
`phoric acid or hot phosphoric salt.
`The resulting structure shown in FIG. 6 has a planar
`silicon dioxide layer over a plurality of silicon pockets
`23 which are laterally air-isolated by cavity pattern 12.
`Then, utilizing the structure of FIG. 6, the active
`devices of the integrated circuit may be formed utilizing
`
`40
`
`45
`
`50
`
`55
`
`006
`
`

`
`4,106,050
`8
`7
`1. An integrated circuit member structure compris
`conventional integrated circuit fabrication techniques
`ing:
`to introduce regions of selected conductivity-types such
`a semiconductor substrate having formed therein a
`as P region 24 into isolated silicon pockets 23 (FIG. 7)
`pattern of cavities extending from one surface of
`through openings 25 formed in silicon dioxide layer 20
`said substrate into the substrate,
`by conventional integrated circuit photolithographic
`' a plurality of pockets of semiconductor material ex
`fabrication techniques. Then, after such regions are
`tending from said surface laterally surrounded and
`formed, the regions may be readily interconnected by
`electrically insulated by said cavities,
`conventional integrated circuit metallization or wiring
`a planar layer of electrically insulative material over
`techniques subsequently formed on the planar surface of
`said surface,
`silicon dioxide layer 20, e.g., metallization layer 26 con
`_ said cavities being fully enclosed by the combination
`nected to P region 24 through metal contact 27.
`of said substrate and said planar layer, and
`It should be noted that for any of the foregoing pro
`a metallization pattern formed on said layervof insula
`cessing steps involving etching either to form recesses
`tive material and selectively connected to a plural
`in layers or substrates or to remove layers, any conven
`ity of said pockets.
`tional etching technique may be employed such as those
`2. The structure of claim 1 wherein the lateral sur
`described in U.S. Pat. No. 3,539,876. Alternatively, any
`faces of said pockets abutting said cavities have formed
`of the above etching steps may be carried out by sputter
`thereon a layer of electrically insulative material.
`etching, utilizing conventional sputter etching appara
`3. The integrated circuit member of claim 2 wherein
`tus and methods such as those described in U.S. Pat. No.
`said substrate is a silicon substrate and said planar layer
`3,598,710, particularly sputter etching carried out utiliz
`is a layer of silicon dioxide.
`ing reactive gases such as oxygen or hydrogen or chlo
`4. The integrated circuit member of claim 3 wherein
`rine. U.S. Pat. No. 3,471,396 sets forth a listing of inert
`said layer formed on said cavities is a layer of silicon
`or reactive gases or combinations thereof which may be
`dioxide.
`used in sputter etching.
`5. The integrated circuit member of claim 2 wherein
`While the invention has been particularly shown and
`each of a plurality of said pockets is formed of a semi
`conductor material of one ‘conductivity-type having
`described with reference to the preferred embodiments
`formed therein at least one region of opposite conduc
`thereof, it will be understood by those skilled in the art
`tivity-type extending from the substrate surface of the
`that various changes in form and details may be made
`pocket into the pocket to provide an integrated circuit
`therein without departing from the spirit and scope of
`30
`device.
`the invention.
`What is claimed is:
`
`20
`
`25
`
`l i i t i
`
`35
`
`45
`
`'50
`
`55
`
`65
`
`007

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket