IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC CORPORATION, HTC AMERICA, INC.,
`and APPLE, INC.
`PETITIONERS
`
`v.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR2016-009231
`Patent 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
`
`
`
`
`
`
`
`1 Case IPR2016-00847 has been joined with this proceeding.
`
`
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC CORPORATION, HTC AMERICA, INC.,
`and APPLE, INC.
`PETITIONERS
`
`v.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR2016-009231
`Patent 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
`
`
`
`
`
`
`
`1 Case IPR2016-00847 has been joined with this proceeding.
`
`
`
`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`TABLE OF CONTENTS
`
`INTRODUCTION ..................................................................................................... 1
`I.
`STATE OF THE PRIOR ART & THE `789 PATENT ................................................. 2
`II.
`III. THE CHALLENGED CLAIMS ARE PATENTABLE ................................................... 5
`A. Anticipation by Lambrecht [claims 1, 3, 5, 11, and 13] ................................... 5
`1. No disclosure of “a shared bus … having a sufficient bandwidth to enable the
`decoder to access the memory and operate in real time” [Independent claim 1
`and claims depending thereon] ............................................................................... 6
`2. No disclosure of “a decoder that requires access to the memory sufficient to
`maintain real time operation” [Independent claim 1 and claims depending
`thereon] ................................................................................................................. 13
`3. No disclosure of “a shared bus … having a sufficient bandwidth to enable the
`decoder to access the memory and operate in real time” [Independent claim 1
`and claims depending thereon] ............................................................................. 15
`4. No disclosure of “the bus having a sufficient bandwidth to enable the
`decoder to access the memory and operate in real time when the first device
`simultaneously accesses the bus” [Independent claim 1 and claims depending
`thereon] ................................................................................................................. 21
`B. Obviousness in view of Lambrecht and Artieri [claim 4] .............................. 24
`C. Obviousness in view of Lambrecht and Moore [claim 6] .............................. 25
`IV. CONCLUSION ................................................................................................... 25
`
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`ii
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`
`TABLE OF AUTHORITIES
`
`
`Cases
`
`C.R Bard, Inc. v. M3 Sys., Inc.,
`157 F.3d 1350 (Fed. Cir. 1998) ............................................................................ 31
`
`
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) ..................................................................... 40, 41
`
`
`In re Wilson,
`424 F.2d 1382 (CCPA 1970) .................................................................................. 3
`
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .............................................................................................. 31
`
`
`
`Rules
`
`35 U.S.C. § 314(a) ..................................................................................................... 1
`
`
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`iii
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`TABLE OF EXHIBITS
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`Exhibit Description
`
`U.S. Patent No. 5,812,789 (“`789 Patent”)2
`File History of `789 Patent
`Shanley, et al., “PCI System Architecture,” Addison-Wesley
`Publishing Company, 1995 (3rd ed.) (“Shanley”)
`Expert Declaration of Dr. Harold Stone (“Stone Decl.”)
`U.S. Patent No. 5,682,484 (“Lambrecht”)
`G. Moore, “Cramming more components onto integrated circuits,”
`Electronics, Vol. 38, No. 8, Apr. 19, 1965 (“Moore”)
`U.S. Patent No. 5,579,052 (“Artieri”)
`Declaration of Mitchell A. Thornton (“Thornton Decl.”)
`Deposition testimony of Harold S. Stone, Phd. dated November 16,
`2016 (“Stone Depo”)
`
`
`
`
`
`Exhibit
`No.
`
`1001
`1002
`1019
`
`1030
`1032
`1035
`
`1036
`2003
`2004
`
`
`2 Ex. 1001, 1002, 1019, 1030, 1032, 1035, and 1036 are already of record and not
`
`attached to this Response.
`
`
`
`iv
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`
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`I.
`
`INTRODUCTION
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
`
`
`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) hereby submits the following response to the Petition for Inter Partes
`
`review (“Petition”) filed by HTC Corp., HTC America, Inc., and Apple, Inc.
`
`(collectively, “Petitioner”) regarding certain claims of U.S. Patent No. 5,812,789
`
`(“`789 Patent”) filed on April 20, 2016 and Decision Granting Institution of Inter
`
`Partes Review 37 C.F.R. 42.108 issued on August 23, 2016 (“Institution Decision”).
`
`The Board instituted an Inter Partes review with respect to the following three
`
`proposed grounds:
`
`1. Alleged Ground A: Anticipation of claims 1, 3, 5, 11, and 13 under §
`
`102(e) by Lambrecht;
`
`2. Alleged Ground B: Obviousness of claim 4 under 35 U.S.C. § 103(a) over
`
`Lambrecht and Artieri; and
`
`3. Alleged Ground C: Obviousness of claim 6 under 35 U.S.C. § 103(a) over
`
`Lambrecht and Moore.
`
`For the reasons discussed below, Lambrecht does not anticipate independent
`
`claim 1. Dependent claims 3-6, 11, and 13 are allowable for at least the same reasons.
`
`The discussion below first discusses the `789 Patent and claims. It then rebuts the
`
`adopted grounds of unpatentability on the merits.
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`
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`1
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`
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`II. STATE OF THE PRIOR ART & THE `789 PATENT
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`The computer memory storage requirements of a digital representation of an
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`uncompressed image is dependent on its resolution, color depth, and size in pixels.
`
`Video files are comprised of sequences of images that are further enhanced with a
`
`corresponding audio track to accompany them. [Ex. 2003, Thornton Decl. ¶29]. As
`
`a result, a video file quickly becomes large in size. The transmission of
`
`uncompressed video files is prohibitively expensive. Id.
`
`Accordingly, video files are typically compressed at a transmitting device.
`
`[Ex. 2003, Thornton Decl. ¶30]. The compressed file is then transmitted to a
`
`receiving device where it is decompressed. Id. To that end, an encoder at the
`
`transmitter compresses the video file and a decoder decompresses the file received
`
`at the receiver in order to retrieve a facsimile of the original video and audio data.
`
`Id. In order to ensure compatibility between devices, a number of standards for
`
`encoding and decoding video files were developed. Id. One of those standards was
`
`developed by the Motion Picture Experts Group (“MPEG”) and has been adopted as
`
`a standard for the communication of video. Id.
`
`If a decoder does not operate in real time, the decoded video being displayed
`
`would stop periodically between images until the decoder can access the memory
`
`and process the subsequent image frame. [Ex. 2003, Thornton Decl. ¶31]. Moreover,
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`U.S. Patent No. 5,812,789
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`when using a temporal (intercompression) technique such as the MPEG Standard,
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`some of the images are decoded based on previous images and some based on
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`previous and subsequent images. Id. Accordingly, dropping an image on which the
`
`decoding of other images depends is unacceptable as it can result in poor or
`
`unrecognizable decoded images. Id. Therefore, it is typically the case that a decoder
`
`requires its own dedicated memory. Id. For instance, traditional MPEG decoders
`
`require a 2 Mbyte dedicated memory that is utilized during the decoding process. Id.
`
`This dedicated memory is necessary to allow the decoder to decode images in real-
`
`time without dropping frames that would result in a deterioration of the video quality
`
`at the receiver. Id.
`
`It is generally desirable to reduce the die area of an integrated circuit device
`
`for a given functionality. [Ex. 2003, Thornton Decl. ¶32]. Such a reduction allows
`
`for an increase in the number of the die that can be manufactured on a silicon wafer
`
`having a given size. Id. For example, a video decoder die would be reduced in size
`
`if it did not include a dedicated memory circuit. Id. Moreover, such a dedicated
`
`memory of a decoder may remain unused when an image is not being decoded which
`
`is inefficient. Id. Accordingly, it is desirable to permit the decoder to share the main
`
`memory of the system with other system components. Id.
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`3
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`To that end, the `789 Patent is generally directed to sharing both a memory
`
`interface and a memory between a video and/or audio decoder and another device
`
`contained in an electronic system. [`789 Pat. [Ex. 1001], Abstract; 4:12-22; 4:30-
`
`34; 4:40-48; independent claim 1]. Accordingly, the electronic system includes a
`
`first device that requires access to the memory and a decoder that requires access
`
`to the memory sufficient to maintain real time operation. Id. at claim 1. A memory
`
`interface is coupled to the memory, the first device and the decoder. Id. The
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`memory interface includes an arbiter for selectively providing access for the first
`
`device and the decoder to the memory. Id. A shared bus is coupled to the memory,
`
`the first device and the decoder. Id. The shared bus has sufficient bandwidth to
`
`enable the decoder to access the memory and operate in real time when the first
`
`device simultaneously accesses the shared bus. Id.
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`A video decoder only requires access to memory during its operation. [Ex.
`
`2003, Thornton Decl. ¶34]. In accordance with the implementation of the `789
`
`Patent, other devices such as a first device may have exclusive access to a shared
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`memory when the decoder is not operating. Id. In such instances, the first device can
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`use the entire bandwidth of the fast bus to support memory accesses. Id.
`
`The fast bus (70) of the `789 Patent has a bandwidth that is at least twice the
`
`required bandwidth to support the memory accesses needed to support real time
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`4
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`video decoding. [`789 Pat., 6:67-7:2]. Accordingly, the video decoder will typically
`
`be using less than 40% of the bandwidth of the fast bus (70) during decoding. [`789
`
`Pat., 7:18-20]. This frees up the remaining bandwidth to be used by other devices
`
`such as a first device during the decoder operation. [`789 Pat., 7:20-22]. Because
`
`the decoder does not use the entire available bandwidth of the fast bus (70) during
`
`real time decoding, the remaining bus bandwidth may be used by other devices such
`
`as a first device simultaneously while real time decoding is occurring. [`789 Pat.,
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`7:5-15].
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`III. THE CHALLENGED CLAIMS ARE PATENTABLE
`
`
`A. Anticipation by Lambrecht [claims 1, 3, 5, 11, and 13]
`
`Independent claim 1 and dependent claims 3, 5, 11, and 13 are not anticipated
`
`by Lambrecht because Lambrecht does not disclose: (1) “a shared bus … having a
`
`sufficient bandwidth to enable the decoder to access the memory and operate in real
`
`time” (Independent claim 1 and claims depending thereon); (2) “a decoder that
`
`requires access to the memory sufficient to maintain real time operation”
`
`(Independent claim 1 and claims depending thereon); (3) “a shared bus … having a
`
`sufficient bandwidth to enable the decoder to access the memory and operate in real
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`time” (Independent claim 1 and claims depending thereon); (4) “the bus having a
`
`sufficient bandwidth to enable the decoder to access the memory and operate in real
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`5
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`IPR2016-00923
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`U.S. Patent No. 5,812,789
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`time when the first device simultaneously accesses the bus” (Independent claim 1
`
`and claims depending thereon).
`
`1. No disclosure of “a shared bus … having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real
`time” [Independent claim 1 and claims depending thereon]
`
`The Petition identifies multimedia device (142D) as the first device; the
`
`main memory (110) as the memory; the multimedia device (144D) as the decoder;
`
`and the PCI expansion bus (120) as the shared bus. [Pet. at 16]. The Petitioner
`
`then contends that the PCI expansion bus (120) provides real time access by the
`
`multimedia device (144D) (alleged decoder) to the main memory (110) (alleged
`
`memory) when operating in the multimedia mode which is a special mode
`
`optimized for real-time data transfers. [Pet. at 17-19]. That is not the case. [Ex.
`
`2003, Thornton Decl. ¶39]. Specifically, when operating in the multimedia mode,
`
`the PCI expansion bus (120) does not enable the multimedia device (144D)
`
`(alleged decoder) to access the main memory (110) (alleged memory). Id.
`
`Accordingly, the PCI expansion bus (120) does not permit communication between
`
`multimedia device (144D) and the main memory (110) when it is placed in the
`
`multimedia mode. Id.
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`The petitioner relies on the embodiment of Figure 21 of Lambrecht for its
`
`contention that independent claim 1 is anticipated. [Pet. at 10-19]. With respect to
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`IPR2016-00923
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`U.S. Patent No. 5,812,789
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`the embodiment of Figure 21, Lambrecht states that “[t]he computer system of FIG.
`
`21 is similar to the computer system of FIG. 1” except that “the mode logic in the
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`computer system of FIG. 21 is operable to place the PCI bus 120 in either a normal
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`PCI mode or in a real-time/multimedia mode optimized for multimedia transfers
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`of periodic data.” [Ex. 2003, Thornton Decl. ¶40 (citing Lambrecht, Ex. 1032,
`
`26:48-56)]. Accordingly, the embodiment of Figure 21 replaces the PCI
`
`expansion bus (120) and the real time bus (130) of Figure 1 with a single PCI
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`expansion bus (120) which has two different modes of operation: (1) a first mode
`
`of operation where the PCI Expansion Bus (120) operates like the PCI Expansion
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`Bus (120) of Figure 1; and (2) a second mode of operation where the PCI
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`Expansion Bus (120) operates like the real time bus (130) of Figure 1. [Ex. 2003,
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`Thornton Decl. ¶40]. The mode logic (960) selects which of the two modes is
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`enabled. [Lambrecht, 27:18-22]. Figure 1 and Figure 21 of Lambrecht are
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`reproduced below, highlighting the difference between the two systems.
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`Because Lambrecht states that “[t]he computer system of FIG. 21 is similar
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`to the computer system of FIG. 1,” one of ordinary skill in the art would
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`understand that when the PCI Expansion Bus (120) of Figure 21 is in the “normal
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`PCI mode” it operates like the PCI Expansion Bus of the embodiment of Figure
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`1. [Ex. 2003, Thornton Decl. ¶41]. Conversely, when the PCI Expansion Bus (120)
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`of Figure 21 is in the multimedia mode, it operates like the multimedia bus (130)
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`of the embodiment of Figure 1. Id. Therefore, for at least three reasons, the PCI
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`Expansion Bus (120) of the embodiment of Figure 21 does not enable the
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`multimedia device (144D) (alleged decoder) to access the main memory (110)
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`(alleged memory) when operating in the multimedia mode. Id.
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`First, as shown in Figure 1, the multimedia bus (130) (which operates
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`“similar” to the PCI Expansion Bus (120) of Figure 21 operating in the
`
`multimedia mode) is not in communication with the PCI Bridge Chipset (106)
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`U.S. Patent No. 5,812,789
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`and the main memory (110) and cannot transfer data from the multimedia device
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`(144) (alleged decoder) to the main memory (110) (alleged memory). [Ex. 2003,
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`Thornton Decl. ¶42].
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`Second, with respect to the operation of the multimedia bus (130) of Figure
`
`1, Lambrecht explicitly states that the multimedia bus (130) facilitates
`
`communication between the multimedia devices (142-146) – not between the
`
`multimedia device (144D) (alleged decoder) and the main memory (110) (alleged
`
`memory). [Ex. 2003, Thornton Decl. ¶42]. Specifically, Lambrecht states:
`
`The multimedia devices 142-146 use the multimedia bus 130 to
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`communicate data, preferably only periodic data, between the
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`respective devices. … Thus, the multimedia devices 142-146
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`communicate with each other via the PCI bus 120 and also
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`communicate with the CPU and main memory 110 via the PCI bus
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`120, as is well known in the art. The multimedia devices 142-146
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`also communicate data between each other using the real-time bus
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`or multimedia bus 130. When the multimedia devices 142-146
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`communicate using the real-time bus 130, the devices are not
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`required to obtain PCI bus mastership and they consume little or no
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`PCI bus cycles.”
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`IPR2016-00923
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`U.S. Patent No. 5,812,789
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`[Lambrecht, Ex. 1032, 8:8-28] (emphasis added). Accordingly, the multimedia
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`bus (130) of Figure 1 does not enable the multimedia device (144D) (alleged
`
`decoder) to access the main memory (110) (alleged memory). [Ex. 2003, Thornton
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`Decl. ¶42]. Because the multimedia mode of the PCI Expansion Bus (120) of the
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`embodiment of Figure 21 operates similar to the multimedia bus (130) of the
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`embodiment of Figure 1 [Lambrecht, 26:51-52], the PCI Expansion Bus (120) of
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`Figure 21 operating in the multimedia mode also does not enable the multimedia
`
`device (144D) (alleged decoder) to access the main memory (110) (alleged
`
`memory). [Ex. 2003, Thornton Decl. ¶42].
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`Third, that the multimedia mode of the PCI Expansion Bus (120) does not
`
`enable the multimedia device (144D) (alleged decoder) to access the main
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`memory (110) (alleged memory) is evident from a closer analysis of the
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`embodiment of Figure 21. [Ex. 2003, Thornton Decl. ¶43]. As is well known to
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`those of ordinary skill in the art, bus standards such as the PCI standard are not
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`defined solely based on their physical hardware assets. Id. Instead, a bus is
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`typically defined as a collection of assets including the hardware and the protocol
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`for data transfer. Id.
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`For example, the Peripheral Component Interconnect (or PCI) specification
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`is one that defines the PCI bus. [Ex. 2003, Thornton Decl. ¶43]. The PCI bus is
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`U.S. Patent No. 5,812,789
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`intended to define the interconnect and bus transfer protocol between highly-
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`integrated peripheral adapters that reside on a common local bus on a system
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`board or add-in expansion cards that are on the PCI bus. [Ex. 2003, Thornton Decl.
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`¶43 (citing Shanley, Ex. 1019, p. 545)]. Accordingly, Lambrecht introduces the
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`use of a new, non-standard bus referred to as the “real-time/multimedia mode” or
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`“multimedia mode” of the PCI Expansion Bus (120). [Ex. 2003, Thornton Decl.
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`¶43]. The purpose of this new “multimedia mode” of the PCI Expansion Bus
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`(120) is to allow periodic data transfers. Id. (citing Lambrecht, 26:53-60). In order
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`to support the use of this new “multimedia mode” of the PCI Expansion Bus
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`(120), specialized hardware (and/or software) must be included with all devices
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`that enable them to use this new and non-standard protocol for data transmission.
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`[Ex. 2003, Thornton Decl. ¶43]. Accordingly, Lambrecht discloses interface logic
`
`(966) “for interfacing to the PCI bus 120 when the PCI bus 120 is in the
`
`multimedia mode.” Id. (citing Lambrecht, 27:38-40) (“The bus interface circuitry
`
`962 also includes interface logic 966 for interfacing to the PCI bus 120 when the
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`PCI bus 120 is in the multimedia mode. The bus interface circuitry 962 also includes
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`interface logic 968 for interfacing to the optional multimedia bus 130”).
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`As a result, all devices disclosed in Figure 21 that benefit from the new and
`
`non-standard “multimedia mode” of the PCI Expansion Bus (120) which enables
`
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`real-time data transmission must necessarily include the interface logic (966) of
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`the bus interface circuitry (962) to enable the use of the real-time multimedia
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`mode of the PCI Expansion Bus (120). [Ex. 2003, Thornton Decl. ¶43]. In contrast,
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`one of ordinary skill in the art would appreciate that the components in Figure 21,
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`which do not have the interface logic (966) of the bus interface circuitry (962),
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`cannot utilize the “multimedia mode” of the PCI Expansion Bus (120) because
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`they are not equipped to interface with it. Id.
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`Furthermore, because the new non-standard multimedia mode utilizes the
`
`same collection of signal lines as those used for the bus when it is in the standard
`
`or “normal” PCI mode of operation, a controlling circuit referred to as “mode
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`logic” (960) must be present within the system that is operable to place the PCI
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`bus 120 in either a normal PCI mode or in a real-time/multimedia mode optimized
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`for multimedia transfers of periodic data. [Ex. 2003, Thornton Decl. ¶44 (citing
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`Lambrecht, 26:48-56; 27:18-22)]. The mode logic 960 is disclosed as being
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`present in the chipset (106). [Lambrecht, 27:2-3; FIG. 21]. A POSA would
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`therefore appreciate that the PCI bus (120) in Figure 21 of Lambrecht must either
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`be operable in a normal PCI mode or in a non-standard real-time/multimedia
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`mode optimized for multimedia transfers, but that the PCI bus cannot
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`simultaneously support both modes of operation. [Ex. 2003, Thornton Decl. ¶44
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`(citing Lambrecht, 27:18-22)]. A POSA would further appreciate that the non-
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`standard real-time/multimedia mode is used only for periodic multimedia data
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`and the normal PCI mode is utilized for addressing and control data. [Ex. 2003,
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`Thornton Decl. ¶44 (citing Lambrecht, 26:56-60; 27:57-62; 27:66-28:11; 28:15-
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`19)].
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`The only devices in Figure 21 that are equipped with the interface logic
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`(966) of the bus interface circuitry (962) are the multimedia devices 142D, 144D,
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`and 146D. [Ex. 2003, Thornton Decl. ¶45 (citing Lambrecht, Figure 22; 27:32-
`
`42)]. Therefore, one of ordinary skill in the art would recognize that only the
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`multimedia devices (142D, 144D, 146D) are equipped to utilize the “multimedia
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`mode” of the PCI Expansion Bus (120). [Ex. 2003, Thornton Decl. ¶45]. The main
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`memory (110) is not equipped with the interface logic (966) of the bus interface
`
`circuitry (962) nor is the PCI bridge chipset (106). Id. This further underscores
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`the fact that the multimedia mode of the PCI Expansion (120) can only be used
`
`for data transmission between the multimedia devices (142D, 144D, 146D), not
`
`between the multimedia device (144D) (alleged decoder) and the main memory
`
`(110) (alleged memory). Id.
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`2. No disclosure of “a decoder that requires access to the memory
`sufficient to maintain real time operation” [Independent claim
`1 and claims depending thereon]
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`13
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`The Petition identifies the multimedia device (144D) as the decoder; the
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`PCI expansion bus (120) as the shared bus, and the main memory (110) as the
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`memory. [Pet. at 11, 16]. The alleged decoder (144D) does not have the capability
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`to maintain real time operation while also accessing the alleged main memory
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`(110). [Ex. 2003, Thornton Decl. ¶46]. As discussed in Section III.A.1, supra,
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`Lambrecht does not disclose a bus that would allow the alleged decoder (144D)
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`to access the alleged main memory (110) in real time.
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`In fact, Lambrecht contemplates multimedia devices that contain dedicated
`
`multimedia memory. [Ex. 2003, Thornton Decl. ¶47 (citing e.g., Lambrecht, Figs.
`
`15 & 16 and related text)]. The multimedia devices have access to this dedicated
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`multimedia memory (160) in real time through the multimedia/real-time bus.
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`[Lambrecht, 20:57-65 (“In one embodiment, devices use the PCI bus 120 for
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`arbitration, addressing and setup, and devices use the multimedia or real-time bus
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`130 for high speed data transfers between each other and also to/from the
`
`multimedia memory 160. Thus, in one embodiment, devices use the PCI bus 120
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`to provide addressing and control signals to the multimedia memory 160 and use
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`the multimedia or real-time bus 130 for high speed data transfers to and from the
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`multimedia memory 160.”)].
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`14
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`Since Lambrecht discloses that multimedia devices may have their own
`
`dedicated multimedia memory (160), and since Lambrecht further discloses that
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`the special real-time mode of operation in FIG. 21 is operable only for the transfer
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`of multimedia data among the multimedia devices (as discussed in Section
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`IX.A.1, supra), a POSA would understand that such previously decoded pictures
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`must reside in dedicated memory present in the multimedia devices since the use
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`of the main memory would violate the real time deadlines in accordance with the
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`teachings of Lambrecht. [Ex. 2003, Thornton Decl. ¶48]. Accordingly, Lambrecht
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`does not disclose “a decoder that requires access to the memory sufficient to
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`maintain real time operation” at least because Lambrecht teaches that access to the
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`main memory does not support real time operation. Id.
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`3. No disclosure of “a shared bus … having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real
`time” [Independent claim 1 and claims depending thereon]
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`The Board has construed the term “real-time” to mean “pertaining to a data-
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`processing system that controls an ongoing process and delivers its outputs (or
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`controls its inputs) not later than the time when these are needed for effective
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`control.” [Institution Decision, paper 10 at 11]. The petitioner identifies the main
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`memory (110) as the recited memory; the PCI expansion bus (120) operating in
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`the multimedia mode as the recited “shared bus” and the multimedia device
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`15
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`(144D) as the recited decoder. [Pet. at 10-19]. However, even if the PCI expansion
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`bus (120) operating in multimedia mode did facilitate data transfer from the
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`multimedia device (144D) (alleged decoder) to the main memory (110) (alleged
`
`memory) (which as discussed above, it does not), the multimedia device (144D)
`
`(alleged decoder) would nevertheless not be able to access the main memory
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`(110) and operate in real time. [Ex. 2003, Thornton Decl. ¶49]. This is evident
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`from an analysis of the embodiment of Figure 21 and the Lambrecht specification.
`
`Id.
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`In order for any data to be transferred from the multimedia device (144D)
`
`(alleged decoder) to the main memory (110) (alleged memory), the data must be
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`transmitted through at least three components: (1) the PCI expansion bus (120);
`
`(2) the PCI Bridge Chipset (106); and (3) the memory bus (108). [Ex. 2003,
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`Thornton Decl. ¶50]. Accordingly, in order to achieve “real-time” data transfer
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`between the multimedia device (144D) and the main memory (110), all three of
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`these components must be able to facilitate real-time data transfers. Id. Figure 21
`
`of Lambrecht which shows these components is reproduced below.
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`16
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`
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`First, as discussed above, the PCI Expansion Bus (120) of Lambrecht only
`
`operates in the multimedia mode when transferring data between the multimedia
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`devices. [Ex. 2003, Thornton Decl. ¶51]. Therefore, the PCI Expansion Bus (120)
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`does not transfer data in real-time between the multimedia device (144D) (alleged
`
`decoder) and the main memory (110) (alleged memory). Id. Moreover, even if the
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`PCI Expansion Bus (120) did facilitate real-time data transfers (which it does not),
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`data could nevertheless not be transferred from the multimedia device (144D)
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`(alleged decoder) to the main memory (110) (alleged memory) in real-time
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`17
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`Patent Owner Response
`U.S. Patent No. 5,812,789
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`because Lambrecht does not disclose the PCI Bridge Chipset (106) or the memory
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`bus (108) as being capable of supporting real-time data transfer. Id.
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`Furthermore, Lambrecht’s general description of “the real time or multimedia
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`mode” is directed to transmission of periodic data between the multimedia devices
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`(142-144), not between the multimedia devices (142-144) and the main memory
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`(110). [Ex. 2003, Thornton Decl. ¶52]. Although Lambrecht references “a special
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`real time mode,” [Lambrecht, 5:42-48], one of ordinary skill in the art would
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`recognize that the recited portion of Lambrecht refers to the embodiment of Figure
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`21 where, as discussed above, the mode logic (960) places the PCI Expansion Bus
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`(120) in a “special real time mode” to facilitate data transfer between the multimedia
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`devices (142-144), not between the multimedia devices (142-144) and the main
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`memory (110). [See, III.A.1, supra].
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`Similarly, Lambrecht’s reference to a “multimedia bus 130 [that] augments or
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`supplements PCI bus 120” is related to transfer of data between the multimedia
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`devices (142-146) as is evident from the discussion of the multimedia bus (130) in
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`conjunction with Figure 1. [Ex. 2003, Thornton Decl. ¶53]. In fact, as shown in
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`Figure 1, the multimedia bus (130) is not capable of accessing or storing data in the
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`main memory (110) and only allows for data transfer and communication among the
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`multimedia devices (142-146). [See, III.A.1, supra]. Therefore, this portion of
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`18
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`Lambrecht also fails to disclose the transfer of data from the multimedia device
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`(144D) (alleged decoder) to the main memory (110) (alleged memory) in real-
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`time. [Ex. 2003, Thornton Decl. ¶53].
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`Moreover, in Lambrecht, periodic data is transferred between the multimedia
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`devices (142-146) on the multimedia bus (130), not between the multimedia device
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`(144D) (alleged decoder) and the main memory (110) (alleged memory). [Ex.
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`2003, Thornton Decl. ¶54 (citing e.g., “[t]he multimedia devices 142-146 use the
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`multimedia bus 130 to communicate data, preferably only periodic data, between the
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`respective devices.” [Lambrecht, 8:8-10]; “if a multimedia device such as device 142
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`desires to transfer periodic data streams on the multimedia bus 130, in step 322 the
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`PCI interface logic 172 in the multimedia device 142 first transfers control
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`information on the PCI bus 120 to the receiving or target device.” [Lambrecht,
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`10:24-28]; “The computer system shown in FIG. 7 includes a real-time bus, also
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`referred to as a multimedia bus 130. … Thus a multimedia data transfer initially
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`involves the transfer of control information on the dedicated control channel 502
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`followed by the transfer of data streams, preferably periodic data streams, on the
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`multimedia bus 130.” [Lambrecht, 13:15-29]; “The multimedia devices 142A-146A
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`preferably use the multimedia or real-time bus 130 only for high speed data transfers
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`of real-time stream data information. In one embodiment the multimedia bus 130
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`19
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`IPR2016-00923
`Patent Owner Response
`U.S. Patent No. 5,812,789
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`transfers only periodic stream data, i.e., data streams which require periodic
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`transfers for multimedia or communication purposes, as described above.”
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`[Lambrecht, 14:25-31]).
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`Therefore, the references to real-time transmission of periodic data do not
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`refer to the transmission of that data from the multimedia device (144D) (alleged
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`decoder) to the main memory (110) (alleged memory). [Ex. 2003, Thornton Decl.
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`¶54]. The lack of interface logic (966) to support periodic data transfers in the PCI
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`bridge chipset (106 and 106A) provides further support (as discussed above) for
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`the fact that the main memory (110) does not support periodic data accesses and
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`hence, the multimedia device serving as the alleged decoder of Lambrecht does
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`not access the main memory (110) and operate in real-time. Id.
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`In fact, the only embodiment of Lambrecht which references real-time transfer
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`of periodic data or stream data information from the multimedia devices to the main
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`memory (110) is the embodiment of Figure 20 where the “multimedia devices 902-
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`910 preferably use their respective memory data channel only” for such transfers.
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`[Ex. 2003, Thornton Decl. ¶55 (citing Lambrecht, 23:33-36)]. Even in this
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`embodiment, the PCI Expansi
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