Consolidated Petitioners
`Apple Inc.
`HTC Corp.*
`HTC America, Inc.*
`
`IPR2016-00923 (U.S. Pat. No. 5,812,789)
`
`
`Andrew S. Ehmke
`David W. O’Brien
`Michael S. Parsons
`Haynes and Boone, LLP
`May 18, 2017
`
`*Petitioner in IPR2016-00847
`joined in this proceeding
`
`1
`
`Ex. 1047
`
`
`Apple Inc.
`HTC Corp.*
`HTC America, Inc.*
`
`IPR2016-00923 (U.S. Pat. No. 5,812,789)
`
`
`Andrew S. Ehmke
`David W. O’Brien
`Michael S. Parsons
`Haynes and Boone, LLP
`May 18, 2017
`
`*Petitioner in IPR2016-00847
`joined in this proceeding
`
`1
`
`Ex. 1047
`
`
`
`Argument
`
`1
`
`Lambrecht anticipates each and every element of
`the challenged claims including:
`a a “decoder” that requires access to memory
`sufficient to maintain real time operation; and
`b a “shared bus” with sufficient bandwidth to
`allow a decoder to access memory and operate
`in real time.
`
`2
`
`Patent Owner mischaracterizes Lambrecht and
`makes incorrect assumptions about the prior art.
`
`2
`
`Ex. 1047
`
`
`
`’789 Patent, Claim 1
`
`Ex. 1001 (’789 Patent),
`claim 1.
`
`3
`
`Ex. 1047
`
`
`
`Lambrecht
`anticipates claim 1*
`
`*Patent Owner does not separately dispute the unpatentability of the dependent claim
`limitations over the recited prior art. (See Response, Paper No. 22 at 24-26).
`
`4
`
`Ex. 1047
`
`
`
`Lambrecht teaches an “electronic system”
`
`Claim 1:
`“An electronic system
`coupled to a memory…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 11;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 35)
`
`Ex. 1032 (Lambrecht) at 26:49-56
`(cited in Petition, Paper No. 2 at 10-11)
`
`5
`
`Ex. 1047
`
`
`
`Lambrecht teaches an “electronic system”
`
`Claim 1:
`“An electronic system
`coupled to a memory…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 11;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 35)
`
`Ex. 1032 (Lambrecht) at 27:4-9
`(cited in Petition, Paper No. 2 at 11-12)
`
`6
`
`Ex. 1047
`
`
`
`Lambrecht teaches a “first device”
`
`Claim 1[a]:
`“…a first device that
`requires access to
`the memory…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 12;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 37)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Petition, Paper No. 2 at 12-13)
`
`7
`
`Ex. 1047
`
`
`
`Lambrecht teaches a “decoder”
`
`Claim 1[b]:
`“…a decoder that
`requires access to the
`memory…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 14;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 39)
`
`Ex. 1032 (Lambrecht) at 27:50-56
`(cited in Petition, Paper No. 2 at 13-14)
`
`8
`
`Ex. 1047
`
`
`
`Lambrecht’s “decoder” requires access
`to the shared memory
`
`Claim 1[b]:
`“…a decoder that
`requires access to the
`memory…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 14;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 39)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Petition, Paper No. 2 at 15)
`
`9
`
`Ex. 1047
`
`
`
`Lambrecht’s “decoder” accesses the memory with
`sufficient bandwidth to maintain real time operation
`
`Claim 1[b]:
`“…sufficient to maintain
`real time operation…”
`
`Ex. 1032 (Lambrecht), Abstract
`(cited in Reply, Paper No. 27 at 10)
`
`Ex. 1032 (Lambrecht) at 26:53-60
`(cited in Petition, Paper No. 2 at 15)
`
`Ex. 1032 (Lambrecht) at 27:18-22
`(cited in Reply, Paper No. 27 at 13)
`
`10
`
`Ex. 1047
`
`
`
`Lambrecht’s PCI bus provides bandwidth sufficient
`for the decoder to operate in real time
`
`’789 Patent specifies 400 Mbytes/s as twice the required bandwidth:
`
`Ex. 1001 (’789 Patent) at 8:57-62
`(cited in Reply, Paper No. 27 at 18-19)
`
`The PCI bus in Lambrecht supports up to 524 Mbytes/s:
`
`Ex. 1019 (Shanley) at 31 (incorporated by
`reference in Lambrecht. Ex. 1032 at 6:67-
`7:4) (cited in Reply, Paper No. 27 at 19)
`
`11
`
`Ex. 1047
`
`
`
`Lambrecht teaches a “memory interface”
`
`Claim 1[c.1]:
`“…a memory interface
`for coupling to the
`memory, and coupled
`to the first device and
`to the decoder,… ”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 16; see also Ex. 1030 (Stone Decl.) ¶ 78 at 43)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Reply, Paper No. 27 at 4-5)
`
`12
`
`Ex. 1047
`
`
`
`Lambrecht’s “memory interface” includes an arbiter
`
`Claim 1[c.1]:
`“…the memory interface
`having an arbiter for
`selectively providing
`access for the first
`device and the decoder
`to the memory and…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 16; see also Ex. 1030 (Stone Decl.) ¶ 78 at 43)
`
`Ex. 1032 (Lambrecht) at 26:66-27:3
`(cited in Petition, Paper No. 2 at 16-17)
`
`13
`
`Ex. 1047
`
`
`
`Lambrecht teaches a “shared bus”
`
`Claim 1[c.2]:
`“…a shared bus coupled
`to the memory, the first
`device, and the
`decoder…”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 16; see also Ex. 1030 (Stone Decl.) ¶ 78 at 43)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Reply, Paper No. 27 at 4-5)
`
`14
`
`Ex. 1047
`
`
`
`Lambrecht’s PCI bus enables the
`decoder to access the memory
`
`Claim 1[c.2]:
`“. . . the bus having a
`sufficient bandwidth to
`enable the decoder to
`access the memory and
`operate in real time
`when the first device
`simultaneously accesses
`the bus.”
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 16; see also Ex. 1030 (Stone Decl.) ¶ 78 at 43)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Reply, Paper No. 27 at 4-5)
`
`15
`
`Ex. 1047
`
`
`
`Lambrecht’s PCI bus enables the
`decoder to operate in real time
`
`Claim 1[c.2]:
`“. . . the bus having a
`sufficient bandwidth to
`enable the decoder to
`access the memory and
`operate in real time
`when the first device
`simultaneously accesses
`the bus.”
`
`Lambrecht’s entire purpose is real- time data transfers:
`
`Ex. 1032 (Lambrecht) at 5:49-55 (cited in Petition, Paper No. 2 at 22-23)
`
`Ex. 1032 (Lambrecht) at 26:53-56 (cited in Petition, Paper No. 2 at 19)
`
`Ex. 1032 (Lambrecht) at 27:18-22 (cited in Reply, Paper No. 27 at 13)
`
`16
`
`Ex. 1047
`
`
`
`Lambrecht’s byte slice mode allows the decoder and
`first device to simultaneously access the PCI bus
`
`Claim 1[c.2]:
`“. . . the bus having a
`sufficient bandwidth to
`enable the decoder to
`access the memory and
`operate in real time
`when the first device
`simultaneously accesses
`the bus.”
`
`Ex. 1032 (Lambrecht) at 27:66-28:7
`(cited in Petition, Paper No. 2 at 17-19)
`
`17
`
`Ex. 1047
`
`
`
`Issue #1:
`Patent Owner argues (based on Lambrecht’s Fig. 1)
`that Lambrecht’s devices cannot access the
`memory while in the multimedia mode.
`
`18
`
`Ex. 1047
`
`
`
`Patent Owner argues an entirely different embodiment
`of Lambrecht than the one referenced in the Petition
`
`Patent Owner and its expert believe that the multimedia bus in Fig. 1
`behaves the same as the multimedia mode of the PCI bus in Fig. 21:
`
`Response, Paper No. 22 at 8
`
`19
`
`Ex. 1047
`
`
`
`The multimedia devices communicate
`with main memory in the multimedia mode
`In Fig. 21, Lambrecht’s PCI bus 120 provides communication between the
`devices and main memory in both the normal and the multimedia modes:
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Petition, Paper No. 2 at 16;
`Reply, Paper No. 27 at 4;
`see also Ex. 1030 (Stone Decl.) ¶ 78 at 43)
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Reply, Paper No. 27 at 4-5)
`
`20
`
`Ex. 1047
`
`
`
`Patent Owner incorrectly uses the structure of
`Fig. 1 to change the teachings of Fig. 21
`
`Fig. 1 and Fig. 21 are not the same:
`
`Fig. 1
`• PCI bus (coupled to the memory)
`• Separate multimedia bus (not
`coupled to the memory)
`
`Fig. 21
`• Single PCI bus coupled to the memory
`• The single bus operates in normal and
`multimedia modes
`
`Ex. 1032 (Lambrecht), Fig. 1
`(cited in Response, Paper No. 22 at 8)
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Response, Paper No. 22 at 8)
`
`21
`
`Ex. 1047
`
`
`
`Patent Owner’s expert failed to consider other
`teachings of Lambrecht that contradict Fig. 1
`
`Patent Owner’s expert, Dr. Thornton, failed to consider Lambrecht’s
`other embodiments that contradict Fig. 1:
`
`Ex. 1043 (Thornton Depo.) at 79:9-16
`(cited in Reply, Paper No. 27 at 10)
`
`22
`
`Ex. 1047
`
`
`
`Lambrecht’s Fig. 6 teaches using the
`multimedia bus to access the main memory
`
`Fig. 6 is also “similar” to Fig. 1 but connects the multimedia bus to the main memory:
`
`Ex. 1032 (Lambrecht), Fig. 1
`(cited in Response, Paper No. 22 at 8)
`
`Ex. 1032 (Lambrecht), Fig. 6
`(cited in Reply, Paper No. 27 at 9)
`
`The multimedia bus in Fig. 6 allows the devices to communicate with main memory:
`
`Ex. 1032 (Lambrecht) at 12:40-45
`(cited in Reply, Paper No. 27 at 9)
`
`23
`
`Ex. 1047
`
`
`
`Lambrecht’s Fig. 6 is more similar to Fig. 21
`because the buses are connected to main memory
`
`Like Fig. 6, the bus in Fig. 21 connects the devices to the main memory:
`
`Ex. 1032 (Lambrecht), Fig. 21
`Ex. 1032 (Lambrecht), Fig. 6
`(cited in Reply, Paper No. 27 at 6)
`(cited in Reply, Paper No. 27 at 9)
`When the bus is connected to main memory, the devices can access the memory:
`
`Ex. 1044 (Stone Decl.) ¶ 8
`(cited in Reply, Paper No. 27 at 9-10)
`
`24
`
`Ex. 1047
`
`
`
`Patent Owner incorrectly assumes that the
`main memory requires special interface logic
`No special logic is needed to interface main memory with the devices in the
`multimedia mode:
`
`1) Main memory is connected to the PCI bridge chipset 106 that already includes a
`memory controller for interfacing main memory.
`
`Ex. 1032 (Lambrecht) at 27:4-9
`(cited in Reply, Paper No. 27 at 12-13)
`
`Ex. 1032 (Lambrecht), Fig. 21
`(cited in Reply, Paper No. 27 at 6)
`
`25
`
`Ex. 1047
`
`
`
`The chipset’s “mode logic” handles the interface
`between the memory and the devices in either mode
`No special logic is needed to interface main memory with the devices in the
`multimedia mode:
`
`
`2)
`
`The PCI bridge chipset 106 includes mode logic 960 that controls the
`operating mode of the chipset.
`
`Ex. 1032 (Lambrecht) at 27:2-3
`(cited in Petition, Paper No. 2 at 17)
`
`Ex. 1032 (Lambrecht) at 27:18-22
`(cited in Reply, Paper No. 27 at 12-13)
`
`Ex. 1044 (Stone Decl.) ¶ 12
`(cited in Reply, Paper No. 27 at 13)
`
`26
`
`Ex. 1047
`
`
`
`Issue #2:
`Patent Owner argues that Lambrecht’s
`devices cannot simultaneously access the bus
`while in the multimedia mode.
`
`27
`
`Ex. 1047
`
`
`
`Patent Owner is incorrect that Lambrecht’s system
`must be in both modes to perform simultaneous access
`
`Byte Slice mode operates during the multimedia mode to allow multiple
`devices to simultaneously access the bus:
`
`Ex. 1032 (Lambrecht) at 27:66-28:7
`(cited in Petition, Paper No. 2 at 17-18)
`
`28
`
`Ex. 1047
`
`
`
`Patent Owner’s expert agrees that the byte slice mode
`provides for simultaneous device transfers
`
`Dr. Thornton agrees that Lambrecht’s byte slice mode provides for
`simultaneous device transfers:
`
`Ex. 1043 (Thornton Depo.) at 128:11-17
`(cited in Reply, Paper No. 27 at 22)
`
`29
`
`Ex. 1047
`
`
`
`Issue #3:
`Patent Owner argues that Lambrecht’s decoder
`necessarily has dedicated multimedia memory.
`
`30
`
`Ex. 1047
`
`
`
`Patent Owner is incorrect that Lambrecht’s decoder
`requires dedicated multimedia memory
`
`Lambrecht’s devices in Fig. 21 (decoder included) access main memory
`and thus do not require dedicated memory:
`
`Ex. 1032 (Lambrecht) at 27:56-62
`(cited in Petition, Paper No. 2 at 15; Reply, Paper No. 27 at 4-5)
`
`31
`
`Ex. 1047
`
`
`
`Patent Owner is incorrect that Lambrecht’s decoder
`requires dedicated multimedia memory
`
`Patent Owner’s position is predicated upon the assumption by its expert, Dr.
`Thornton, that all MPEG decoders at the time required dedicated memory:
`
`Ex. 2003 (Thornton Decl.) at ¶ 31
`(cited in Reply, Paper No. 27 at 15)
`
`32
`
`Ex. 1047
`
`
`
`Patent Owner is incorrect that Lambrecht’s decoder
`requires dedicated multimedia memory
`
`Dr. Thornton reiterated this requirement during deposition:
`
`Ex. 1043 (Thornton Depo.) at 88:7-89:2
`(cited in Reply, Paper No. 27 at 15)
`
`33
`
`Ex. 1047
`
`
`
`Evidence that decoders did not require
`dedicated memory
`
`Ex. 1044 (Stone Decl.) ¶ 15
`(cited in Reply, Paper No. 27 at 16)
`
`Ex. 1044 (Stone Decl.) ¶ 17
`(cited in Reply, Paper No. 27 at 16-17)
`
`34
`
`Ex. 1047
`
`
`
`Evidence that decoders did not require
`dedicated memory
`
`U.S. Patent No. 5,797,028 to Gulick et al.
`•
`Filed 11 months before the ’789 Patent
`•
`Lambrecht is a co-inventor
`
`
`Ex. 1023 (Gulick) at 6:48-55
`(cited in Reply, Paper No. 27 at 16;
`see also Ex. 1044 (Stone Decl.) ¶ 16)
`
`35
`
`Ex. 1047
`
`
`
`Evidence that decoders did not require
`dedicated memory
`
`U.S. Patent No. 5,461,679 to Normile et al.
`•
`Filed 3+ years before the ’789 Patent
`• Assigned to Petitioner Apple Inc.
`
`
`Ex. 1045 at 9:11-15
`(cited in Reply at 16;
`see also Ex. 1044
`(Stone Decl.) at ¶ 16)
`
`Ex. 1045 at 9:45-50
`(cited in Reply at 16;
`see also Ex. 1044
`(Stone Decl.) at ¶ 16)
`
`Ex. 1045 at 9:54-57
`(cited in Reply at 16;
`see also Ex. 1044
`(Stone Decl.) at ¶ 16)
`
`36
`
`Ex. 1047
`
`
`
`Conclusion
`
`1
`
`Lambrecht teaches each and every element of the
`challenged claims.
`
`2
`
`Patent Owner’s arguments are unpersuasive because
`they are mischaracterizations of Lambrecht’s
`teachings and make unsupported assumptions about
`the prior art.
`
`37
`
`Ex. 1047
`
`
`
`Consolidated Petitioners
`Apple Inc.
`HTC Corp.*
`HTC America, Inc.*
`
`IPR2016-00923 (U.S. Pat. No. 5,812,789)
`
`
`Andrew S. Ehmke
`David W. O’Brien
`Michael S. Parsons
`Haynes and Boone, LLP
`May 18, 2017
`
`*Petitioner in IPR2016-00847
`joined in this proceeding
`
`38
`
`Ex. 1047
`
`
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