UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`APPLE INC., HTC CORPORATION, AND HTC AMERICA INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-00923
`Patent No. 5,812,789
`
`_____________________
`
`
`
`DECLARATION OF HAROLD S. STONE, PH.D.,
`UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITIONER REPLY
`
`
`
`
`
`Ex. 1044
`IPR2016-00923, HTC v. PUMA
`Page 1 of 15
`
`
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`APPLE INC., HTC CORPORATION, AND HTC AMERICA INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-00923
`Patent No. 5,812,789
`
`_____________________
`
`
`
`DECLARATION OF HAROLD S. STONE, PH.D.,
`UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITIONER REPLY
`
`
`
`
`
`Ex. 1044
`IPR2016-00923, HTC v. PUMA
`Page 1 of 15
`
`
`
`
`
`
`
`I.
`
`II.
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`TABLE OF CONTENTS
`
`Introduction ...................................................................................................... 1
`
`Lambrecht’s Fig. 21 is not limited by Fig. 1. .................................................. 1
`
`III. Lambrecht’s Fig. 21 does not require special logic to operate. ....................... 8
`
`IV. Decoder devices in Lambrecht do not require dedicated memory. ................. 9
`
`V.
`
`Lambrecht’s PCI bus is capable of communicating data in real time. .......... 11
`
`VI. Conclusion ..................................................................................................... 13
`
`
`
`
`i
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 2 of 15
`
`
`
`
`
`
`I, Harold S. Stone, Ph.D., declare as follows:
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`I.
`
`Introduction
`
`1.
`
`I am the Harold S. Stone who has previously submitted a declaration
`
`in this proceeding (Ex. 1030). The terms of my engagement, my background,
`
`qualifications and prior testimony, and the legal standards and claim constructions
`
`I am applying are set forth in my previous declarations. I offer this declaration in
`
`reply to the testimony of Prof. Thornton provided in this proceeding (Exs. 2003
`
`and 1043). In forming my opinion, I have considered the materials noted in my
`
`previous declarations in these proceedings, as well as the following additional
`
`materials:
`
` Exhibit 2003 – Declaration of Mitchell A. Thornton
`
` Exhibit 1043 – Deposition Testimony of Mitchell A. Thornton
`
` Exhibit 1045 – U.S. Patent No. 5,461,679 to Normile et al.
`
`II. Lambrecht’s Fig. 21 is not limited by Fig. 1.
`
`2.
`
`In describing Fig. 1, Lambrecht states that “the multimedia devices
`
`142-146 communicate with each other via the PCI bus 120 and also communicate
`
`with the CPU and main memory 110 via the PCI bus 120” and that “[t]he
`
`multimedia devices 142-146 also communicate data between each other using the
`
`real-time bus or multimedia bus 130.” Ex. 1032 at 8:20-25. Dr. Thornton thus
`
`
`
`
`1
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 3 of 15
`
`
`
`
`
`
`concludes that: “one of ordinary skill in the art would understand that when the
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`PCI Expansion Bus (120) of Figure 21 is in the ‘normal PCI mode’ it operates like
`
`the PCI Expansion Bus of the embodiment PUMA of Figure 1. Conversely, when
`
`the PCI Expansion Bus (120) of Figure 21 is in the multimedia mode it operates
`
`like the multimedia bus (130) of the embodiment of Figure 1.” Ex. 2003 ¶ 16-17.
`
`This position is incorrect as it ignores the other embodiments of Lambrecht that are
`
`more instructive as to functionality of the embodiment in Fig. 21.
`
`3. While the computer system in Fig. 21 is similar to the system Fig.1 in
`
`that it includes a CPU 102, a PCI bridge chipset 106, memory 110, and multimedia
`
`devices 142-144, the system in Fig. 21 differs in that it includes (1) a single PCI
`
`bus that connects the various components and (2) “mode logic which selects
`
`between different modes of the PCI bus 120.” Ex. 1032 at 26:50-51. For reference,
`
`Fig. 21 from my previous declaration is provided for reference:
`
`
`
`
`2
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 4 of 15
`
`
`
`
`
`
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`Ex. 1032, Fig. 21
`
`Ex. 1032, Fig. 1
`
`
`
`4.
`
`The mode logic “is operable to place the PCI bus 120 in either a
`
`normal PCI mode or in a real-time/multimedia mode optimized for multimedia
`
`transfers of periodic data.” Ex. 1032 at 26:53-56. This allows the multimedia
`
`devices to “communicate with each other and with the CPU 102 and main
`
`memory 110 via the PCI bus 120, as is well known in the art.” Ex. 1032 at 27:57-
`
`59 (emphasis added). The mode logic also allows the multimedia devices to
`
`communicate data “using the PCI bus signal lines 120 when the PCI bus 120 is in
`
`the multimedia mode.” Ex. 1032 at 27:59-62 (emphasis added). Thus, contrary to
`
`Dr. Thornton’s flawed analysis, a POSITA would understand that in Lambrecht’s
`
`Fig. 21, the PCI bus provides for real-time multimedia data transfers over the PCI
`
`bus.
`
`
`
`
`3
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 5 of 15
`
`
`
`
`
`
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`5.
`
`There is nothing in reference to Fig. 21 that restricts the multimedia
`
`mode of the PCI bus 120 to data communication only between multimedia devices.
`
`Instead, for this purpose, the computer system in Fig. 21 provides an optional
`
`multimedia bus 130 “to augment or supplement the PCI bus 120 when the PCI bus
`
`120 is in multimedia mode.” Ex. 1032 at 27:30-31. This optional multimedia bus
`
`130 is included so that the multimedia devices can, as described in Fig. 1,
`
`“communicate data between each other using the real-time bus or multimedia bus
`
`130. When the multimedia devices 142-146 communicate using the real-time bus
`
`130, the devices are not required to obtain PCI bus mastership and they consume
`
`little or no PCI bus cycles.” Ex. 1032 at 8:24-28 (referencing Fig. 1). Thus, a
`
`POSITA would understand that including the optional multimedia bus 130 into the
`
`Fig. 21 embodiment achieves Lambrecht’s express purpose of allowing the
`
`multimedia devices to “communicate data between each other” so that “the devices
`
`are not required to obtain PCI bus mastership and they consume little or no PCI
`
`bus cycles” on the PCI bus 120. See Ex. 1032 at 8:24-28.
`
`6.
`
`Dr. Thornton’s position that the PCI bus 120 is restricted to only
`
`communicate data between multimedia devices when in the multimedia mode
`
`makes the optional inclusion of the multimedia bus 130 redundant. Under Dr.
`
`Thornton’s theory, since the multimedia mode of the PCI bus 120 would only
`
`
`
`
`4
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 6 of 15
`
`
`
`
`
`
`provide data communication between the multimedia devices, the optional
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`multimedia bus 130, if included, would perform the exact same function. A
`
`POSITA would understand the embodiment of Fig. 21 provides access for
`
`multimedia devices to memory while in multimedia mode, for otherwise, the
`
`optional bus 130 would provide nothing distinct from what is already provided by
`
`bus 120 in multimedia mode. This is not only redundant but it is contrary to the
`
`express purpose of Lambrecht. If multimedia mode were to operate only for
`
`communications between the multimedia devices as Dr. Thornton opines, then
`
`multimedia mode would consume all PCI bus cycles that could otherwise be used
`
`for memory transfers as opposed to consuming “little or no PCI bus cycles.” See
`
`Ex. 1032 at 8:24-28. And the optional multimedia bus 130 would perform the
`
`exact same function.
`
`7.
`
`It should also be noted that other embodiments of Lambrecht disclose
`
`the multimedia bus communicating data between the multimedia devices and the
`
`CPU and memory. The embodiment in Fig. 6 is such an example. As seen below,
`
`Fig. 6 is similar to Fig. 1 except that the multimedia bus in Fig. 6 is not only
`
`connected to the multimedia devices but is also connected to the PCI bridge chipset
`
`that connects the CPU and memory. Ex. 1032 at 12:22-25.
`
`
`
`
`5
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 7 of 15
`
`
`
`
`
`
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`Ex. 1032, Fig. 6
`
`Ex. 1032, Fig. 1
`
`
`
`8.
`
`Contrary to the Fig. 1 embodiment, the additional connection of the
`
`multimedia bus to the chipset in Fig. 6 is “to accommodate peripheral device
`
`accesses through the real-time bus 130A and chipset logic 106A to main memory
`
`110.” Ex. 1032 at 12:29-31. As a result, in Fig. 6, “one or more of the multimedia
`
`devices 142-146 can use the multimedia bus 130A to interface through the chipset
`
`logic 106A to the main memory 110 as desired.” Ex. 1032 at 12:43-45 Thus, Dr.
`
`Thornton is incorrect in his analysis of Fig. 21 since Lambrecht does in fact teach
`
`that when the multimedia bus is connected to the PCI bridge chipset, it can be used
`
`to communicate data between the multimedia devices and the CPU and memory in
`
`real-time.
`
`9.
`
`Additionally, Dr. Thornton’s argument fails to explain how the system
`
`in Fig. 21 would continue to “provide[] much greater performance for real-time
`
`
`
`
`6
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 8 of 15
`
`
`
`
`
`
`applications” (Ex. 1032, Abstract) if the multimedia mode of the PCI bus is limited
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`to only communicating data between the multimedia devices. In this configuration,
`
`both the PCI bus and the optional multimedia bus would be dedicated to transfers
`
`between multimedia devices, which would result in the CPU and the memory not
`
`being able to interface with the multimedia devices. Any operations requiring
`
`interface between the multimedia devices would therefore be paused until the PCI
`
`bus return to the normal mode. This configuration also negates the entire point of
`
`the multimedia bus being optionally included since the multimedia devices would
`
`be “required to obtain PCI bus mastership” and would consume all of the PCI bus
`
`cycles while in the multimedia mode. Ex. 1032 at 8:25-28.
`
`10.
`
`In light of the express teachings of all of the embodiments of
`
`Lambrecht, Dr. Thornton’s position that the multimedia mode of the PCI bus 120
`
`in Fig. 21 can only communicate data between the multimedia devices because the
`
`multimedia bus 130 of Fig. 1 can only communicate data between the multimedia
`
`devices is incorrect. Dr. Thornton fails to explain the purpose of the optional
`
`inclusion of the multimedia bus 130 in Fig. 21 to perform the same purported
`
`function and he fails to explain why the multimedia mode of the PCI bus 120
`
`would operate according to the multimedia bus of Fig. 1 rather than the multimedia
`
`bus of Fig. 6.
`
`
`
`
`7
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 9 of 15
`
`
`
`
`
`
`III. Lambrecht’s Fig. 21 does not require special logic to operate.
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`11. Dr. Thornton takes the position that the multimedia devices are not
`
`able to access the main memory when the PCI bus 120 is in multimedia mode
`
`because “one of ordinary skill in the art would recognize that only the multimedia
`
`devices (142D, 144D, 146D) are equipped to utilize the ‘multimedia mode’ of the
`
`PCI Expansion Bus (120)” since only these devices “are equipped with the
`
`interface logic (966) of the bus interface circuitry (962).” Ex. 2003 ¶ 45.
`
`12. Dr. Thornton is correct to the extent that the multimedia devices in
`
`Fig. 21 include interface logic 966 in order to interface with the multimedia mode
`
`See Ex. 1032 at 27:38-40. But Dr. Thornton is incorrect that only devices with this
`
`interface are capable of communicating using the multimedia mode. Instead,
`
`Lambrecht teaches “a host/PCI/cache bridge or chipset 106” that is coupled to a
`
`CPU 102 and a main memory 110. Ex. 1032 at 26:65-67, 27:4-5. “The chipset
`
`logic 106 preferably includes a memory controller for interfacing to the main
`
`memory 110.” Ex. 1032 at 27:8-9. The chipset logic 106 also includes a “mode
`
`logic 960 [that] is operable to place the PCI bus 120 in either a normal PCI mode
`
`or in a real-time/multimedia mode optimized for multimedia transfers of periodic
`
`data.” Ex. 1032 at 27:19-22. Since the chipset 106 interfaces the CPU and the main
`
`memory with the PCI bus, a POSITA would understand that this mode logic would
`
`
`
`
`8
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 10 of 15
`
`
`
`
`
`
`be sufficient to interface PCI bus to the main memory regardless of the PCI bus’s
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`communication mode.
`
`13. This is further supported by Lambrecht’s disclosure of Fig. 6 where
`
`no additional logic is disclosed for communication data using the multimedia bus.
`
`Instead, in Fig. 6, the chipset logic 106A “is connected to both the local expansion
`
`bus 120 as well as the real-time [multimedia] bus 130A.” Ex. 1032 at 12:23-25.
`
`The chipset 106A “can communicate directly to the PCI bus 120, and can also
`
`communicate directly with the real-time or multimedia bus 130.” Ex. 1032 at
`
`12:37-40. This allows the multimedia devices (that include both PCI bus and
`
`multimedia bus interface logic, see Fig. 2) to communicate with the CPU and the
`
`memory via either the PCI bus or the multimedia bus. See Ex. 1032 at 12:40-45.
`
`Thus, Lambrecht does not require any special logic in addition to the PCI bridge
`
`chipset for the multimedia devices to communicate with the CPU and main
`
`memory while using either the multimedia bus in Fig. 6 or the multimedia mode in
`
`Fig. 21.
`
`IV. Decoder devices in Lambrecht do not require dedicated memory.
`
`14. Dr. Thornton takes the unsupported position that “traditional MPEG
`
`decoders require a 2 Mbyte dedicated memory that is utilized during the decoding
`
`process.” Ex. 2003 ¶ 31. Based on this, Dr. Thornton goes on to assume that the
`
`video decoders discussed in Lambrecht also require dedicated multimedia memory
`
`9
`Ex. 1044
`
`
`IPR2016-00923, HTC v. PUMA
`Page 11 of 15
`
`
`
`
`
`
`and that such decoders would not use the main memory in Fig. 21. See Ex. 2003 ¶
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`48; Ex. 1043 at 88:23-89:1 (“And if [the multimedia device] were assumed to be a
`
`video decoder, one skilled in the art in 1997, when this was issued, would presume
`
`that there would be multimedia memory”).
`
`15. Dr. Thornton is incorrect that video decoders known in the art prior to
`
`the filing of the ’789 patent in 1996 or Lambrecht in 1995 required dedicated
`
`multimedia memory. This is evident from the prior art that was known before the
`
`filing of the ’789 patent.
`
`16. For example, Gulick (Ex. 1023) teaches a digital system chip 112 that
`
`“is programmable to perform various functions, such as MPEG decoding.” Ex.
`
`1023 at 6:21-22. Gulick describes, in certain instances, that the decoder chip 112
`
`can include “multimedia memory (not shown) for storing multimedia data, such as
`
`video data and audio data.” Ex. 1023 at 6:37-39. Gulick, however, also discloses
`
`that, in other instances, the decoder chip 112 “does not include multimedia
`
`memory, but rather video data and audio data are stored in the system memory 110
`
`according to a unified memory architecture.” Ex. 1023 at 6:48-51. Other systems
`
`that also predate the ’789 patent disclosed a video decoder that used shared
`
`memory. See Ex. 1007 (disclosing a system that uses either system memory or
`
`dedicated memory for at least some video decoding operations); Ex. 1045
`
`
`
`
`10
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 12 of 15
`
`
`
`
`
`
`(disclosing a system with shared memory that is used by multiple peripheral
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`devices including video decoders).
`
`17. Thus, it is clear that Dr. Thornton is wrong since a POSITA, before
`
`the filing of the ’789 patent, had full knowledge that video decoders could use
`
`main system memory according to a unified memory architecture for video
`
`decoding operations. Accordingly, it was known in the art that video decoders
`
`could utilize either dedicated multimedia memory, as shown in Lambrecht’s Figs.
`
`15 and 16, or the main memory, as shown in Lambrecht’s Figs. 6, 19, and 21, and
`
`the evidence of record shows that it was known to POSITAs that decoders could
`
`use the main system memory.
`
`V. Lambrecht’s PCI bus is capable of communicating data in real time.
`
`18. According to the ’789 patent, a bus capable of real time transfers must
`
`have “a bandwidth greater than the bandwidth required for the decoder/encoder 45
`
`to operate in real time.” Ex. 1001 at 6:29-32. In the ’789 patent, the
`
`decoder/encoder 45 operates according to the MPEG-1 or MPEG-2 standard. See
`
`Ex. 1001 at 7:45-54. In two examples provided by the ’789 patent, the bus “is
`
`capable of having a bandwidth of approximately 400 Mbytes/s. This bandwidth is
`
`at least twice the bandwidth required for an optimized decoder/encoder 45,
`
`allowing the decoder/encoder 45 to operate in real time.” Ex. 1001 at 8:57-62;
`
`9:20-25.
`
`
`
`11
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 13 of 15
`
`
`
`
`
`
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
`
`
`19. While Lambrecht does not specifically describe the bandwidth of the
`
`PCI bus used in Fig. 21 necessary to maintain real time operation with the
`
`multimedia devices (including an MPEG decoder), Shanley (Ex. 1019),
`
`incorporated by reference into Lambrecht (see Ex. 1023 at 7:1-4), states that a PCI
`
`bus “can be populated with adapters requiring fast access to each other and/or
`
`system memory and that can be accessed by the host processor at speeds
`
`approaching that of the processor’s full native bus speed.” Ex. 1019 at 30. This fast
`
`access “[s]upports 132Mbytes per second peak transfer rate for both read and write
`
`transfers, [and] 264Mbytes per second peak transfer rate for 64-bit PCI transfers.
`
`Transfer rates of up to 524Mbytes per second are achievable on a 66MHz PCI
`
`bus.” Ex. 1019 at 31.
`
`20. Based on these teachings in Lambrecht, a POSITA would have
`
`understood that Lambrecht’s PCI bus could support data transfer rates (e.g.,
`
`memory reads and writes) up to 524 Mbytes per second, which is greater than the
`
`400 Mbytes per second transfer rate indicated in the ’789 patent as being twice the
`
`bandwidth necessary to maintain real time operation of an MPEG decoder. Thus,
`
`Lambrecht’s use of a PCI bus to transfer data from an MPEG decoder to memory
`
`discloses a bus having sufficient bandwidth to operate in real time.
`
`
`
`
`12
`
`Ex. 1044
`
`IPR2016-00923, HTC v. PUMA
`Page 14 of 15
`
`
`
`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in lPR20l6—00923
`
`VI. Conclusion
`
`21.
`
`I hereby declare under penalty of perjury under the laws of the United
`
`States of America that the foregoing is true and correct, and that all statements
`
`made of my own knowledge are true and that all statements made on information
`
`and belief are believed to be true. I understand that willful false statements are
`
`punishable by fine or imprisonment or both. See 18 U.S.C. § 1001.
`
`Date: February 24, 2017
`
`Respectfully submitted,
`
`§tS‘7é»,<o
`
`Harold S. Stone, Ph.D.
`
`EX. 1044
`
`IPR20l6-00923, HTC V. PUMA
`
`Page 15 of 15
`
`IPR2016-00923, HTC v. PUMA
`Page 15 of 15
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
