`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`APPLE INC., HTC CORPORATION, AND HTC AMERICA INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-00923
`Patent No. 5,812,789
`
`_____________________
`
`
`
`DECLARATION OF HAROLD S. STONE, PH.D.,
`UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITIONER REPLY
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`Ex. 1044
`IPR2016-00923, HTC v. PUMA
`Page 1 of 15
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`I.
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`II.
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`TABLE OF CONTENTS
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`Introduction ...................................................................................................... 1
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`Lambrecht’s Fig. 21 is not limited by Fig. 1. .................................................. 1
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`III. Lambrecht’s Fig. 21 does not require special logic to operate. ....................... 8
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`IV. Decoder devices in Lambrecht do not require dedicated memory. ................. 9
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`V.
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`Lambrecht’s PCI bus is capable of communicating data in real time. .......... 11
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`VI. Conclusion ..................................................................................................... 13
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`i
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`Ex. 1044
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`I, Harold S. Stone, Ph.D., declare as follows:
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`I.
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`Introduction
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`1.
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`I am the Harold S. Stone who has previously submitted a declaration
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`in this proceeding (Ex. 1030). The terms of my engagement, my background,
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`qualifications and prior testimony, and the legal standards and claim constructions
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`I am applying are set forth in my previous declarations. I offer this declaration in
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`reply to the testimony of Prof. Thornton provided in this proceeding (Exs. 2003
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`and 1043). In forming my opinion, I have considered the materials noted in my
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`previous declarations in these proceedings, as well as the following additional
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`materials:
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` Exhibit 2003 – Declaration of Mitchell A. Thornton
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` Exhibit 1043 – Deposition Testimony of Mitchell A. Thornton
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` Exhibit 1045 – U.S. Patent No. 5,461,679 to Normile et al.
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`II. Lambrecht’s Fig. 21 is not limited by Fig. 1.
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`2.
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`In describing Fig. 1, Lambrecht states that “the multimedia devices
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`142-146 communicate with each other via the PCI bus 120 and also communicate
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`with the CPU and main memory 110 via the PCI bus 120” and that “[t]he
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`multimedia devices 142-146 also communicate data between each other using the
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`real-time bus or multimedia bus 130.” Ex. 1032 at 8:20-25. Dr. Thornton thus
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`1
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`concludes that: “one of ordinary skill in the art would understand that when the
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`PCI Expansion Bus (120) of Figure 21 is in the ‘normal PCI mode’ it operates like
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`the PCI Expansion Bus of the embodiment PUMA of Figure 1. Conversely, when
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`the PCI Expansion Bus (120) of Figure 21 is in the multimedia mode it operates
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`like the multimedia bus (130) of the embodiment of Figure 1.” Ex. 2003 ¶ 16-17.
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`This position is incorrect as it ignores the other embodiments of Lambrecht that are
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`more instructive as to functionality of the embodiment in Fig. 21.
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`3. While the computer system in Fig. 21 is similar to the system Fig.1 in
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`that it includes a CPU 102, a PCI bridge chipset 106, memory 110, and multimedia
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`devices 142-144, the system in Fig. 21 differs in that it includes (1) a single PCI
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`bus that connects the various components and (2) “mode logic which selects
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`between different modes of the PCI bus 120.” Ex. 1032 at 26:50-51. For reference,
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`Fig. 21 from my previous declaration is provided for reference:
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`2
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`Ex. 1044
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`Ex. 1032, Fig. 21
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`Ex. 1032, Fig. 1
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`4.
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`The mode logic “is operable to place the PCI bus 120 in either a
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`normal PCI mode or in a real-time/multimedia mode optimized for multimedia
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`transfers of periodic data.” Ex. 1032 at 26:53-56. This allows the multimedia
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`devices to “communicate with each other and with the CPU 102 and main
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`memory 110 via the PCI bus 120, as is well known in the art.” Ex. 1032 at 27:57-
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`59 (emphasis added). The mode logic also allows the multimedia devices to
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`communicate data “using the PCI bus signal lines 120 when the PCI bus 120 is in
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`the multimedia mode.” Ex. 1032 at 27:59-62 (emphasis added). Thus, contrary to
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`Dr. Thornton’s flawed analysis, a POSITA would understand that in Lambrecht’s
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`Fig. 21, the PCI bus provides for real-time multimedia data transfers over the PCI
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`bus.
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`3
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`5.
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`There is nothing in reference to Fig. 21 that restricts the multimedia
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`mode of the PCI bus 120 to data communication only between multimedia devices.
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`Instead, for this purpose, the computer system in Fig. 21 provides an optional
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`multimedia bus 130 “to augment or supplement the PCI bus 120 when the PCI bus
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`120 is in multimedia mode.” Ex. 1032 at 27:30-31. This optional multimedia bus
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`130 is included so that the multimedia devices can, as described in Fig. 1,
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`“communicate data between each other using the real-time bus or multimedia bus
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`130. When the multimedia devices 142-146 communicate using the real-time bus
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`130, the devices are not required to obtain PCI bus mastership and they consume
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`little or no PCI bus cycles.” Ex. 1032 at 8:24-28 (referencing Fig. 1). Thus, a
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`POSITA would understand that including the optional multimedia bus 130 into the
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`Fig. 21 embodiment achieves Lambrecht’s express purpose of allowing the
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`multimedia devices to “communicate data between each other” so that “the devices
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`are not required to obtain PCI bus mastership and they consume little or no PCI
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`bus cycles” on the PCI bus 120. See Ex. 1032 at 8:24-28.
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`6.
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`Dr. Thornton’s position that the PCI bus 120 is restricted to only
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`communicate data between multimedia devices when in the multimedia mode
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`makes the optional inclusion of the multimedia bus 130 redundant. Under Dr.
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`Thornton’s theory, since the multimedia mode of the PCI bus 120 would only
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`4
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`provide data communication between the multimedia devices, the optional
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`multimedia bus 130, if included, would perform the exact same function. A
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`POSITA would understand the embodiment of Fig. 21 provides access for
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`multimedia devices to memory while in multimedia mode, for otherwise, the
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`optional bus 130 would provide nothing distinct from what is already provided by
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`bus 120 in multimedia mode. This is not only redundant but it is contrary to the
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`express purpose of Lambrecht. If multimedia mode were to operate only for
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`communications between the multimedia devices as Dr. Thornton opines, then
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`multimedia mode would consume all PCI bus cycles that could otherwise be used
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`for memory transfers as opposed to consuming “little or no PCI bus cycles.” See
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`Ex. 1032 at 8:24-28. And the optional multimedia bus 130 would perform the
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`exact same function.
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`7.
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`It should also be noted that other embodiments of Lambrecht disclose
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`the multimedia bus communicating data between the multimedia devices and the
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`CPU and memory. The embodiment in Fig. 6 is such an example. As seen below,
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`Fig. 6 is similar to Fig. 1 except that the multimedia bus in Fig. 6 is not only
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`connected to the multimedia devices but is also connected to the PCI bridge chipset
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`that connects the CPU and memory. Ex. 1032 at 12:22-25.
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`5
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`Ex. 1032, Fig. 6
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`Ex. 1032, Fig. 1
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`8.
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`Contrary to the Fig. 1 embodiment, the additional connection of the
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`multimedia bus to the chipset in Fig. 6 is “to accommodate peripheral device
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`accesses through the real-time bus 130A and chipset logic 106A to main memory
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`110.” Ex. 1032 at 12:29-31. As a result, in Fig. 6, “one or more of the multimedia
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`devices 142-146 can use the multimedia bus 130A to interface through the chipset
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`logic 106A to the main memory 110 as desired.” Ex. 1032 at 12:43-45 Thus, Dr.
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`Thornton is incorrect in his analysis of Fig. 21 since Lambrecht does in fact teach
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`that when the multimedia bus is connected to the PCI bridge chipset, it can be used
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`to communicate data between the multimedia devices and the CPU and memory in
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`real-time.
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`9.
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`Additionally, Dr. Thornton’s argument fails to explain how the system
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`in Fig. 21 would continue to “provide[] much greater performance for real-time
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`6
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`applications” (Ex. 1032, Abstract) if the multimedia mode of the PCI bus is limited
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`to only communicating data between the multimedia devices. In this configuration,
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`both the PCI bus and the optional multimedia bus would be dedicated to transfers
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`between multimedia devices, which would result in the CPU and the memory not
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`being able to interface with the multimedia devices. Any operations requiring
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`interface between the multimedia devices would therefore be paused until the PCI
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`bus return to the normal mode. This configuration also negates the entire point of
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`the multimedia bus being optionally included since the multimedia devices would
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`be “required to obtain PCI bus mastership” and would consume all of the PCI bus
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`cycles while in the multimedia mode. Ex. 1032 at 8:25-28.
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`10.
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`In light of the express teachings of all of the embodiments of
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`Lambrecht, Dr. Thornton’s position that the multimedia mode of the PCI bus 120
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`in Fig. 21 can only communicate data between the multimedia devices because the
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`multimedia bus 130 of Fig. 1 can only communicate data between the multimedia
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`devices is incorrect. Dr. Thornton fails to explain the purpose of the optional
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`inclusion of the multimedia bus 130 in Fig. 21 to perform the same purported
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`function and he fails to explain why the multimedia mode of the PCI bus 120
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`would operate according to the multimedia bus of Fig. 1 rather than the multimedia
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`bus of Fig. 6.
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`7
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`III. Lambrecht’s Fig. 21 does not require special logic to operate.
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`11. Dr. Thornton takes the position that the multimedia devices are not
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`able to access the main memory when the PCI bus 120 is in multimedia mode
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`because “one of ordinary skill in the art would recognize that only the multimedia
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`devices (142D, 144D, 146D) are equipped to utilize the ‘multimedia mode’ of the
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`PCI Expansion Bus (120)” since only these devices “are equipped with the
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`interface logic (966) of the bus interface circuitry (962).” Ex. 2003 ¶ 45.
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`12. Dr. Thornton is correct to the extent that the multimedia devices in
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`Fig. 21 include interface logic 966 in order to interface with the multimedia mode
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`See Ex. 1032 at 27:38-40. But Dr. Thornton is incorrect that only devices with this
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`interface are capable of communicating using the multimedia mode. Instead,
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`Lambrecht teaches “a host/PCI/cache bridge or chipset 106” that is coupled to a
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`CPU 102 and a main memory 110. Ex. 1032 at 26:65-67, 27:4-5. “The chipset
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`logic 106 preferably includes a memory controller for interfacing to the main
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`memory 110.” Ex. 1032 at 27:8-9. The chipset logic 106 also includes a “mode
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`logic 960 [that] is operable to place the PCI bus 120 in either a normal PCI mode
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`or in a real-time/multimedia mode optimized for multimedia transfers of periodic
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`data.” Ex. 1032 at 27:19-22. Since the chipset 106 interfaces the CPU and the main
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`memory with the PCI bus, a POSITA would understand that this mode logic would
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`be sufficient to interface PCI bus to the main memory regardless of the PCI bus’s
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`communication mode.
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`13. This is further supported by Lambrecht’s disclosure of Fig. 6 where
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`no additional logic is disclosed for communication data using the multimedia bus.
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`Instead, in Fig. 6, the chipset logic 106A “is connected to both the local expansion
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`bus 120 as well as the real-time [multimedia] bus 130A.” Ex. 1032 at 12:23-25.
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`The chipset 106A “can communicate directly to the PCI bus 120, and can also
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`communicate directly with the real-time or multimedia bus 130.” Ex. 1032 at
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`12:37-40. This allows the multimedia devices (that include both PCI bus and
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`multimedia bus interface logic, see Fig. 2) to communicate with the CPU and the
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`memory via either the PCI bus or the multimedia bus. See Ex. 1032 at 12:40-45.
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`Thus, Lambrecht does not require any special logic in addition to the PCI bridge
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`chipset for the multimedia devices to communicate with the CPU and main
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`memory while using either the multimedia bus in Fig. 6 or the multimedia mode in
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`Fig. 21.
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`IV. Decoder devices in Lambrecht do not require dedicated memory.
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`14. Dr. Thornton takes the unsupported position that “traditional MPEG
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`decoders require a 2 Mbyte dedicated memory that is utilized during the decoding
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`process.” Ex. 2003 ¶ 31. Based on this, Dr. Thornton goes on to assume that the
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`video decoders discussed in Lambrecht also require dedicated multimedia memory
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`and that such decoders would not use the main memory in Fig. 21. See Ex. 2003 ¶
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`48; Ex. 1043 at 88:23-89:1 (“And if [the multimedia device] were assumed to be a
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`video decoder, one skilled in the art in 1997, when this was issued, would presume
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`that there would be multimedia memory”).
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`15. Dr. Thornton is incorrect that video decoders known in the art prior to
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`the filing of the ’789 patent in 1996 or Lambrecht in 1995 required dedicated
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`multimedia memory. This is evident from the prior art that was known before the
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`filing of the ’789 patent.
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`16. For example, Gulick (Ex. 1023) teaches a digital system chip 112 that
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`“is programmable to perform various functions, such as MPEG decoding.” Ex.
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`1023 at 6:21-22. Gulick describes, in certain instances, that the decoder chip 112
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`can include “multimedia memory (not shown) for storing multimedia data, such as
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`video data and audio data.” Ex. 1023 at 6:37-39. Gulick, however, also discloses
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`that, in other instances, the decoder chip 112 “does not include multimedia
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`memory, but rather video data and audio data are stored in the system memory 110
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`according to a unified memory architecture.” Ex. 1023 at 6:48-51. Other systems
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`that also predate the ’789 patent disclosed a video decoder that used shared
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`memory. See Ex. 1007 (disclosing a system that uses either system memory or
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`dedicated memory for at least some video decoding operations); Ex. 1045
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`10
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`(disclosing a system with shared memory that is used by multiple peripheral
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`devices including video decoders).
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`17. Thus, it is clear that Dr. Thornton is wrong since a POSITA, before
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`the filing of the ’789 patent, had full knowledge that video decoders could use
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`main system memory according to a unified memory architecture for video
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`decoding operations. Accordingly, it was known in the art that video decoders
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`could utilize either dedicated multimedia memory, as shown in Lambrecht’s Figs.
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`15 and 16, or the main memory, as shown in Lambrecht’s Figs. 6, 19, and 21, and
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`the evidence of record shows that it was known to POSITAs that decoders could
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`use the main system memory.
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`V. Lambrecht’s PCI bus is capable of communicating data in real time.
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`18. According to the ’789 patent, a bus capable of real time transfers must
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`have “a bandwidth greater than the bandwidth required for the decoder/encoder 45
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`to operate in real time.” Ex. 1001 at 6:29-32. In the ’789 patent, the
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`decoder/encoder 45 operates according to the MPEG-1 or MPEG-2 standard. See
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`Ex. 1001 at 7:45-54. In two examples provided by the ’789 patent, the bus “is
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`capable of having a bandwidth of approximately 400 Mbytes/s. This bandwidth is
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`at least twice the bandwidth required for an optimized decoder/encoder 45,
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`allowing the decoder/encoder 45 to operate in real time.” Ex. 1001 at 8:57-62;
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`9:20-25.
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`11
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in IPR2016-00923
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`19. While Lambrecht does not specifically describe the bandwidth of the
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`PCI bus used in Fig. 21 necessary to maintain real time operation with the
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`multimedia devices (including an MPEG decoder), Shanley (Ex. 1019),
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`incorporated by reference into Lambrecht (see Ex. 1023 at 7:1-4), states that a PCI
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`bus “can be populated with adapters requiring fast access to each other and/or
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`system memory and that can be accessed by the host processor at speeds
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`approaching that of the processor’s full native bus speed.” Ex. 1019 at 30. This fast
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`access “[s]upports 132Mbytes per second peak transfer rate for both read and write
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`transfers, [and] 264Mbytes per second peak transfer rate for 64-bit PCI transfers.
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`Transfer rates of up to 524Mbytes per second are achievable on a 66MHz PCI
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`bus.” Ex. 1019 at 31.
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`20. Based on these teachings in Lambrecht, a POSITA would have
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`understood that Lambrecht’s PCI bus could support data transfer rates (e.g.,
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`memory reads and writes) up to 524 Mbytes per second, which is greater than the
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`400 Mbytes per second transfer rate indicated in the ’789 patent as being twice the
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`bandwidth necessary to maintain real time operation of an MPEG decoder. Thus,
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`Lambrecht’s use of a PCI bus to transfer data from an MPEG decoder to memory
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`discloses a bus having sufficient bandwidth to operate in real time.
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`12
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`Declaration of Harold S. Stone, Ph.D. in support of
`Petitioner Reply in lPR20l6—00923
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`VI. Conclusion
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`21.
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`I hereby declare under penalty of perjury under the laws of the United
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`States of America that the foregoing is true and correct, and that all statements
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`made of my own knowledge are true and that all statements made on information
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`and belief are believed to be true. I understand that willful false statements are
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`punishable by fine or imprisonment or both. See 18 U.S.C. § 1001.
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`Date: February 24, 2017
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`Respectfully submitted,
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`§tS‘7é»,<o
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`Harold S. Stone, Ph.D.
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`EX. 1044
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