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`US0ll6070003A
`
`United States Patent
`Gave et al.
`
`[19]
`
`[ll] Patent Number:
`
`6,070,003
`
`[451 Date of Patent:
`
`May 30, 2000
`
`W0 88i‘081l'i'F
`
`ll}.-‘I988 Wi|’().
`
`(}Tl[l.lR PUl?ol.[C.-"\Ti()NS
`
`A. M. Despain, et a1., "High Perfonnance Frolog, The
`Multiplicative Elfect of Several Levels of Implementation",
`ll;‘E.l_~'., pp.
`l?8—184, 1986.
`"Vl'l'ce Parallel C Compiler". by T. Butler. published by
`Visual
`Information Technologies,
`Inc. Plano TX, pp.
`74l—?4?.
`"A Single Board image computer with 64 Parallel 1’ruccs-
`sors", by Stephen Wilson. published in Electronic Imaging
`’87, International Electronic lmaging Exposition & Confer-
`ence. (198?) pp. 470-475.
`"The Androx Parallel Image Array Processor". by Wayne
`Threatl, in liiectronic imaging ’8'.l', lntemalional Electronic
`imagining Exposition & Con1'crcnce{1987), pp. 1061-1064.
`"Real Time 3[) Object Tracking in a Rapid Prototyping
`|3nvironment", by Robert J. (iove in Electronic Imaging '88
`(1933).
`"Integration of Symbolic and Multiple Digital Signal Pru-
`cessors with the Explorer.-‘Odyssey for Image Processing and
`Understanding Applications", by Robert J. (iove, in Pro-
`ceeding of the H:'r':'I:' fnrernntiartrtl Syt'lJp(.\Yitt'rtt' an Circrtfts
`and .8‘/vsrrzrtis. pp. 968-97} (May, 198?).
`
`(List continued on next page.)
`
`Prirtirtry l§xrtr:tiner—l{evin J. Teska
`Assisrrtrit Exrtrm'mer—Ky]c J. Choi
`.-lttarnedvglgerit, or Fr'r:.=t—Rolaert D. M:irshall,.lr.; W. James
`Brady, ll]; Frederick J. 'li;|ccky, Jr.
`
`[57]
`
`ABSTRACT
`
`There is disclosed a mu]ti—processor system and method
`arranged.
`in one embodiment. as an image and graphics
`processor. The image processor is structured with several
`individual processors all having communication links to
`several memories. A crtisqliar switch serves to establish the
`processor memory links. The entire image pl‘0IL‘C!-.i‘-B(l1‘,l|.‘lC1lJ(1-
`ing the individual processors. the erossl1:Ir switch and the
`memories, is oontained on El single silicon chip.
`
`[54]
`
`I75]
`
`SYSTEM AND METHOD OF MEMORY
`ACCESS IN APPAR.r’\'I'US HAVING PLURAL
`PROCESSORS AND PLURAL MEMORIES
`
`Inventors: Robert .1. (love, Plano, 'l'ex.; Keith
`Balrtter; Nicholas Kt.-rin lng-Simmorts,
`both of Bedford. United Kingdom; Karl
`Mm-ion Gultag. Missouri City, Tex.
`
`[73]
`
`Assignce: Texas Instruments Incorporated,
`Ballas. Tex.
`
`[31]
`I32]
`
`Appl. No.: 0lil264,5it2
`1-‘iled:
`Jun. 22, 1994
`
`[63]
`
`[511
`[53]
`[58]
`
`[551
`
`Related 1.3.5. Application Data
`
`Continuation of application No. 0?.-"43T,552_. Nov. 1?. 1939,
`abandoned.
`
`Int. Cl.’
`.
`U.S. CI.
`Field of Search
`
`1161" I316
`.... .. 395,812
`395.9200. 300
`
`References Cited
`
`U.S. PA'l'EN'I' DOCUMENTS
`
`l2!l‘J82 Barnes et al.
`4.365.202
`ll.«'1l)8:‘s Rttu et al.
`4.553.203
`l2i'l‘»'fl5
`\«"inu.‘ent el al.
`4,.’§I‘/2.535
`12.-‘W84’:
`liloutel al
`4_.o33_.245
`.
`E1987 .r\.ndrew.s
`4.044.490
`5i’I‘J8S Rodman ..
`4_.'!4?_.(t43
`ZIIIJS9 Shelor
`4_.3lJ7',184
`3.-"I989 Ran el al.
`4:8! 1,20!
`:">i'I99t'l Jennings ..
`4,930,102
`ll},-"1990 George et al.
`4,965,718
`[H991 Grondalslti
`..
`4.985.832
`5.»"l991
`(ionin cl ai.
`5.02[l.(l50
`3.51991 C.'1r\«'cy cl rtl.
`5,04-l.9?1
`ll’).-"I991 Chang
`5,l'l.‘iI‘i,t'Kll'l
`151992 Rau el 31.
`5.083.267
`?.-'l 992 Jackson at 211.
`5_l33,fl?3
`S,-"1992
`Ilcchtel iii.
`5,1-1-2,fJ8[I
`FOREIGN PATENT DOCUMl.’.NTS
`
`
`
`3‘J5."3(l(l
`3'.~l:‘1.I'8(|0
`3f:4t'2tl']
`34-l-'J.-"325.l.|3
`3f)4.I‘9(lll
`3o4t’2m
`3I‘>4Nl.KJ
`395895
`395.*8(lfi
`395;"8{|l'I
`3‘l5.r'80(t
`3(J5.I’3l'.Kl
`395,-‘S00
`395."8(]"l
`395,-’3'.I‘S
`395.'8tI"l
`.. 3'.J5I8lII
`
`U 245 9% ll.-‘I08?
`
`European Put. 011'.
`
`.
`
`16 Claims, 35 Drawing Sheets
`
`I.lil'El'l'R'.""I MB “(Ll
`
`EU5
`
`
`
`0001
`0001
`
`Volkswagen 1009
`Volkswagen 1009
`
`

`
`6,070,003
`Page 2
`
`OTHER PUBLICATIONS
`
`"The Use of Parallel-Processing Computers in Digital
`Image Processing", by Lew Brown. published by Alliant
`Computer Systems Corp, Lillelon. MA.
`“The Connection Machine”, by W.D. Hillis, published in
`Jllte MIT Press (1985).
`“Handling Real Time Images Comes Naturally to Systolic
`Array Chip", by Ilannaway, Shea Bishop,
`in Electronic
`Desigri, p. 289-30(J (I984).
`“Systolic Array Chip Recognizes Visual Patterns Quicker
`Than a Wink", by W.W. Smith, P. Sullivan,
`in Electronic
`Design, pp. 257-266 ([984).
`“Design of a Massively Parallel Processor“, by Kenneth
`Batcher, IEEE Transactions on Compttters, v. C-29, No. 9
`(1980).
`"High Resolution Frame Grabbing and Processing Through
`Parallel Architecture", by Daniel Crevier published by
`Coreco, lnc., Quebec, Canada.
`
`Multiple Digital Signal Pl‘(‘-lCC5'S.‘S(ll’ Environment for Intelli-
`gent Signal Processing by Gass el al., in Proceedings ofthc
`IEEE, V. 75, No. 9 (Sep. l987) pp. 1246-125.
`
`"Architecture and Design of the Mars Ilardware Accelera-
`tor", Agra Wall, et. in 24"" ACMHEEE Design Automation
`Conference (1987), pp. 1tJ1-107.
`
`"Digital Video 8: image Processors“, by O'Brien, Mather 8:
`Holland, published by Plessey Semiconductors (1989).
`
`"An Architceturcal Study. Design and Implementation of
`Digital Image Acquisition, Processing and Display Systems
`with Micro-Processor-Based Personal Computers and
`Chat'ge—Coupled Device Imaging Teclinology", at disserta-
`tion by Robert J. Go SMU (1986).
`
`"A Medium Grained Parallel Computer for Image Pm-cess-
`ing", by RS. COR, published by Digital Teelinology Center,
`Eastman Kodak Co., Rochester NY.
`
`0002
`
`

`
`May 30, 2000
`
`Sheet 1 of 35
`
`6,070,003
`
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`
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`
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`
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`
`May 30, 2000
`
`Sheet 2 of 35
`
`6,070,003
`
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`
`

`
`U.S. Patent
`
`May 30, 2000
`
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`6,070,003
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`May 30, 2000
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`6,070,003
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`6,070,003
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`U.S. Patent
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`May 30, 2000
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`Sheet 16 of 35
`
`6,070,003
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`May 30, 2000
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`Sheet 17 of 35
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`6,070,003
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`May 30, 2000
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`Sheet 18 of 35
`
`6,070,003
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`ADDRESS UNIT
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`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 19 of 35
`
`6,070,003
`
`IMMEDIATE
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`U.S. Patent
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`May 30, 2000
`
`Sheet 20 of 35
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`6,070,003
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`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 21 of 35
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`6,070,003
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`(EITHER Epr CAN PUSH THE RETURN ADDRESS).
`Epr — PUSH RET IF A CALL.
`Fd1 — DELAY SLOT 1
`INSTRUCTi0N FETCH.
`Fd2 — DELAY SLOT 2 INSTRUCTION FETCH.
`Fbu — FETCH INSTRUCTION FROM BRANCH ADDRESS.
`.
`— INTERRUPTS LOCKED OUT.
`
`0023
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 22 of 35
`
`6,070,003
`
`SIMD "MASTER" PP TO "SU\\r‘E" PP! INTERRUPT SIGNAL
`
`SIMD "SLAIIE" PP TO "I.IASTER’ PP INTERRUPT SIGNAL
`
`Eps
`
`A i
`
`f"
`
`Aps
`$Fira
`
`I
`
`pI::=veC
`ret:=pc
`
`pc+1
`
`pc+1
`
`I
`
`pc+1
`
`pc+1
`
`pc+1
`
`pc
`
`pr:
`
`=
`
`[nt — INTERRUPT OCCURS.
`
`VECTOR EETCH INTO PC].
`(PC TO RET.
`Fpv — PSEUDO INSTRUCTION.
`Apv - CALCULATE INTERRUPT VECTOR AOORESS.
`Epv - COPY PC TO RET.
`FETCH INTERRUPT VECTOR INTO PC.
`Fpr — PSEUOO INSTRUCTION.
`(PUSH RET).
`Apr — CALCULATE STACK PUSH AOORESS
`Epr ~ PUSH RET ONTO STACK.
`[PUSH SR).
`Fps ~ PSEUDO INSTRUCTION.
`Aps — CALCULATE STACK PUSH AOORESS.
`I ANO CLD BITS [N SR.
`Eps - PUSH SR ONTO STACK.
`CLEAR S.
`Fin — FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`$
`— SYNC.
`INTERRUPTS AN0 LOOPING OISAOLEO UNTIL AFTER SR HAS BEEN PUSHEO.
`NEITHER OE FIRST TwO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`
`FIG. 39
`
`0024
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 23 of 35
`
`6,070,003
`
`I! SIMD |"MASTER" PP TO “SLAVE” PP's INTERRUPT SIGNAL
`»
`I
`I
`31010 "SLAVEL PP T0 "MASTER" PP INTERRUPT SIGNAL
`
`I
`
`_
`
`I
`
`,
`
`‘
`
`-
`
`|
`
`'
`I
`SYNC ESIGNAII.
`I
`
`I
`
`.
`
`i
`
`I
`
`'
`
`A
`
`.
`
`F
`
`F'|A'E
`Fid
`
`Each
`
`(Arum
`
`, Fnrn
`
`I
`
`I
`
`l
`
`pc+1 pc+1Ipc+1I
`
`pc
`
`pc
`
`pc
`
`pc
`
`I
`
`pc
`
`pc
`
`Ipc+1I
`
`Fid — IDLE INSTRUCTION FETCHED.
`PIPELINE NOT LOADED.
`Fnm - NO MASTER PHASE ON INSTRUCTION FETCH.
`Anm — NO MASTER PHASE ON INSTRUCTION FETCH. ADDRESS REGISTERS NOT MODIFIED.
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT OPERATIONS
`KILLED.
`Enm — NO MASTER PHASE IN DATA UNIT.
`InI — INTERRUPT OCCURS.
`EIL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`Fpv — PSEUDO INSTRUCTION.
`(PC TO RET.
`VECTOR FETCH INTO PC).
`Apv - CALCULATE INTERRUPT VECTOR ADDRESS.
`Epv - COPY PC TO RET.
`FETCH INTERRUPT VECTOR INTO PC.
`Fpr — PSEUDO INSTRUCTION.
`(PUSH RET).
`Apr — CALCULATE STACK PUSH ADDRESS.
`Epr — PUSH RET ONTO STACK.
`Fps — PSEUDO INSTRUCTION MOSH SR).
`Aps - CALCULATE STACK PUSH ADDRESS.
`I AND CLD BITS IN SR.
`Eps — PUSH SR ONTO STACK.
`CLEAR S,
`Fin - FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`3
`- SYNC,
`INTERRUPTS AND LOOPING DISABLED UNTIL Al-TER SR HAS BEEN PUSHED.
`NEITHER OF FIRST TWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`
`FIG. 40
`
`0025
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 24 of 35
`
`6,070,003
`
`FIG. 47
`
`'
`'
`
`I
`INCOMING SYNC SIGNAL
`
`pc+1
`
`pc+1I
`
`pc
`
`pc
`
`pc
`
`Ipc+1
`
`pc+1
`
`PC UNALTERED.
`PIPE NOT LOADED.
`Fns — NO SYNC CONDITION.
`Anm — NO MASTER PHASE IN ADDRESS UNIT.
`ADDRESS REGISTERS NOT MODIFIED.
`
`LOADS
`STORES COMPLETE TO MEMORY.
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT
`OPERATIONS KILLED.
`Enm - NO MASTER PHASE [N DATA UNIT.
`EIL — TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESIGNATION REG|STER(S).
`DATA UNIT PERFORMS [TS ALU/MPY OPERATIONS.
`
`LOADS:
`
`(ASSUMING N0 SiGN—EXTENSIDN)
`
`FIG. 42
`
`SOURCE DATA:
`
`BYTE NO.
`3 2 1 O
`
`0DDOh
`00040
`
`0 c 0 A
`H 0 F E
`
`(MEMORY)
`
`DESTINATION
`
`'? ? ? ?
`
`(REGISTER)
`
`16—BiT
`
`ADD.
`
`LOADS”.
`
`REG VALUE
`
`32—BlT
`
`.13
`|c>
`
`ADD.
`
`Lggggm
`
`TU|c>
`
`E
`
`f—J'_'at:DoasDC:c:r:(2
`f"'l’l—I'—l—l"-
`
`
`OOOOh
`OOO2h
`
`O O B A
`— — — —
`
`O0O1h ---B
`OOO3h
`O O C —
`
`OOO2h
`OOO4h
`
`D O D C
`— - - -
`
`000311
`000511
`
`can:or:$-Qcar:
`
`
`
`cs-0car:cu-oz::::1M-0Usc'>'~>mmD5on(1:03>32-
`
`0026
`
`C
`
`I-'f_'l—I’l’l—n"|'—CDCat:cat:on:I:u:c:
`
`
`
`
`
`D C B A
`
`OOOOh
`OOO4h
`
`0001 h
`OOO5h
`
`OOO2h
`D0061’:
`
`OOO3h
`O-OO7h
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 25 of 35
`
`6,070,003
`
`SOURCE DATA:
`
`DCBA
`
`(REGISTER)
`
`BYTE N0.
`3210
`
`????
`????
`
`(MEMORY)
`
`32—BlT
`
`OP.
`
`ADD.
`
`5TgRE5___
`
`REG VALUE
`
`o\_'|}_aq3}
`
`D ?
`
`.
`
`D ?
`
`.
`
`ST
`
`000Dh
`
`D C B A
`
`STU
`
`0O04h
`
`—
`
`DESTINATION DATA:
`
`00O0h
`U004h
`
`0DDOh
`00D4h
`
`16—BlT
`
`STORES...
`
`
`
`
`
`f)-Q-Q-Q5.‘)-.3-c-
`
`ST
`
`000ih
`
`STU
`
`0005h
`
`ST
`
`O002h
`
`O0U6h
`
`OO0.3h
`
`000?h
`
`
`
`amon;-on-or;
`
`-03>-Q3?
`
`.Q},.Q:=,..
`Q-o-o--.3
`
`0027
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 26 of 35
`
`6,070,003
`
`ADD WITH SATURATE
`
`MAXIMUM
`
`TRANSPARENCY
`
`ADDM
`MRGM
`
`D0. D1, D2
`D2. D3. D2
`
`CMPM
`MRGM
`
`DO
`
`COLOUR EXPANSION
`
`COLOUR COMPRESSION
`
`GUIDED COPY
`
`LD
`MRGM
`
`«A0. MFLAGS
`D0. D1. D1
`
`CMPM
`
`D0, D1, D2
`
`89 23 CD 5?
`89 89 89 89
`
`— 00 09 44 co)
`MFLAGS = '2? '9? ?? ?!3
`
`LD
`MRGM
`
`1-A0. MFLAGS
`D0. D1, D2
`
`xx xx xx x5
`
`11111111
`88 38 88 83
`
`1188 B811
`
`GROUP
`E1535
`L
`
`C
`or 2
` BLOCK
`GROUPS
`
` “”f‘
`1—————LIuE or 512 PlxELs:———‘
`
`0028
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 27 of 35
`
`6,070,003
`
`CAMERA
`
`4500
`
`FIG. 46
`
`IMAGE
`PROCESSOR
`
`0029
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 28 of 35
`
`6,070,003
`
`TELEPHONE
`LINE
`
`ACQUISITION
`
`I UNIT I
`
`CONTROLLER
`
`CCD's
`
`OBJECT OR
`
`DOCWENT
`
`FOR comma
`
`COPY OR
`FACSEMILE
`PRODUCT
`
`STATISTICAL
`ACCUMULATED
`ECORDKEEPIN
`
`PANEL
`
`[SP
`
`DISPLAY n 5101
`
`0030
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 29 of 35
`
`6,070,003
`
`5206
`
`SCANNER
`
`FRONT END
`PROCESSOR
`
`IMAGING
`
`DEVICE
`
`ADDRESS
`GENERATOR
`
`OUTPUT
`DEVICE
`
`0031
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 30 of 35
`
`6,070,003
`
`_.——
`I
`'""5Z2‘6n
`5428!
`I
`
`0032
`
`

`
`U.S. Patent
`
`DM02W3v,.m
`
`Sheet 31 of 35
`
`6,070,003
`
`.|?....J4_5nD_..!Ru.u._
`
`_U...UnUnUnUnUnUnUnU
`
`000000000
`
`001111100
`
`nunU1._U4InU.UnUnU
`
`nU.Hu.|._U.£nU0nH.U
`
`nunu.|UnunU_UnunU
`
`000000000
`
`000000000
`
`1234567'8
`
`01234
`
`0033
`
`

`
`May 30, 2000
`
`Sheet 32 of 35
`
`6,070,003
`
`
`
`32-BITADDRESSBUS
`
`5701
`
`B x 64 BIT FIFO
`
`SOURCE E
`ADDRESS
`
`GENERATOR B
`
`DESTINATION IE
`ADDRESS
`GENERATOR
`
`EXPAND/ALIGN LOGIC
`
`{'5'95::
`Eh.I
`ILIJ
`)<|—
`E
`
`PIXEL INPUT
`(A/D CONVERTER)
`
`0034
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 33 of 35
`
`6,070,003
`
`0I_M_0 GENERAL CASE
`
`{PRIOR ART)
`
`FIG, 5 .9
`
`CONTROLLER
`
`+DATA PATH
`
`INSTRUCTION
`MEMORY
`
`6002 MIGENERAL CASE
`
`FIG. 60
`(PRIOR ART)
`
`CONTROLLER
`
`5004
`
`am
`
`5040
`
`DATA PATH 4:05
`
`0035
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 34 of 35
`
`6,070,003
`
`I ———— —_4
`INSTRUCTION
`MEMORY
`
`I
`I
`
`I I I I I I I I I I I I I I I I I I I I I
`
`‘I
`.l om MEMORY
`
`I
`
`I
`
`I
`
`I
`
`
`
`PROCESSORSYNCBUS
`
`
`
`PROCESSORSYNCHUS
`
`:5 ___ INSTRUCTION
`finned I
`I
`I
`“Em
`.I DATA MEMORY
`3362 .—:1 '
`'
`'
`—'-5‘ CONTROLLER 4-R: '”i‘TE’1IJ§gI°“
`G
`I
`I
`I
`
`. DATA PATH Illil
`
`I02
`
`-:5‘ CONTROLLER 4————— '”5TRUC“0“
`]
`|
`|
`MEMORY
`i
`I
`I
`T’
`DATA PATH (1'j'?'l* DATA MEMORY
`I___l
`I_ _ _ _ _ ___.._I
`
`INSTRUCTION
`MEMORY
`
`INSTRUCTION
`MEMORY
`
`R3-9 DATA MEMORY
`
`0036
`
`

`
`U.S. Patent
`
`May 30, 2000
`
`Sheet 35 of 35
`
`6,070,003
`
`2O
`I‘ — — — — ——4
`I_“')_|
`N. CONTROLLER :“ INSTRUCTION
`
`3”“ 1 '
`I00
`IEl..............III
`
`I
`
`I
`I
`DATA PATH SR1-F DATA MEMORY
`
`I
`
`I
`
`INSTRUCTION
`MEMORY
`
`Iv
`
`.” DATA MEMORY
`‘OI
`I
`I
`I
`3002 '
`
`I INSTRUCTION
`MEMORY
`
`CONTROLLER
`*
`I
`I
`I
`.”||| DATA MEMORY
`
`310g
`
`I02
`
`3100
`
`103
`
`E?_____________________
`L____-____HLH___~,____A‘v_'> Z G
`
`ElIGI
`
`Ix ._:___ INSTRUCTION
`I
`I
`I
`MEMORY
`T’
`I
`I
`I
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`
`I.,__I
`
`I_ _ _ _ _ ___I
`
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`
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`
`_I
`
`I‘ '_ [;Sfi?|JETBN—
`
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`I
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`
`I
`
`I
`
`I
`
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`
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`
`I
`
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`'
`I
`
`'
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`
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`I
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`
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`PROCESSORSYNCBUS
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`II
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`. DATA PATH III DATA MEMORY
`
`,_._j INSTRUCTION
`MEMORY
`
`I
`
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`
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`
`I
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`I
`I
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`
`I_ _ _I
`
`I. _ _ _ _ _ _
`
`0037
`
`

`
`6,t}7tl,{}03
`
`1
`SYSTEM AND ME1‘H()I} O1" MPZMORY
`ACCESS IN APPARATUS HAVING PLURAL
`PROCESSORS AND PLURAL MEMORIES
`
`This application is a Continuation of application Ser. No.
`t't'H437,852, tiled Nov. 17, 1989 abandoned.
`
`5
`
`TECHNICAL FIELD OF THE INVENTION
`
`'I‘his invention relates generally to rnu1ti—proce-ssor sys-
`tents and mtlrc particularly to such systems and methods
`where the several processors are interconnectahle to many
`dilferent memory addressing spaces by a multi-port switch.
`CROSS—REFERENCE TO RELATED
`APPI .I(.‘ATI ON
`
`All of the following patent applications are cross-
`referenced to one another, and all have been assigned to
`Texas Instruments Incorporated. These applications have
`been concurrently tiled and are hereby incorporated in this
`patent application by reference.
`
`2
`and assuming only four processors in the system, a mini-
`mum of twelve buses must be switched. When it is realized
`that additional buses may be required for master processors
`and control processors to handle simultaneous data input!
`output on a particular memory module and processing via a
`particular processor on other memory modules, the problem
`is compounded. In some situations it may be desirable to
`isolate certain memories [or access only by a particular
`processor, such as a master processor.
`Making the problem even more severe is the fact that in
`a multi-processing system the true power comes from the
`ability of any processor to communicate with any memory
`at any time combined with the ability of the processors to
`communicate with each other, all occurring simultaneously.
`There is thus a need in the art for a system which handles
`multi-processors having multi-memories such that
`the
`address space from all of the memories is available to one or
`more processors concurrently even when the processors are
`handling different instruction streams.
`One method of solving the huge interconnection problem
`in complex systems such as the image processing system
`shown in one embodiment of the invention is to construct the
`entire processor as a single device. Conceptually this might
`appear easy to achieve, but
`in reality the problems are
`complicated.
`First of all, an architecture must be created which allows
`for the eflicient movement of information, while at the same
`time consuming a minmum amount of precious silicon chip
`space in order to achieve a high performance to cost ratio.
`The architecture must allow a very high degree of flexibility,
`since once fabricated,
`it cannot easily be modilied for
`different applications. Also, since the processing capability
`of the system will be high, there is a need for high bandwidth
`of each data inputloutput signal which moves information on
`and off the chip. This is so since the physical number of leads
`which can attach to any one chip is limited.
`It is also desirable to design an entire parallel processor
`system, such as an image processor, on a single silicon chip
`while maintaining the system flexible enough to satisfy wide
`ranging and constantly changing operational criteria.
`It is further desirable to construct such a single chip
`parallel processor system where the processor memory
`interface is easily adaptable to operation in various modes,
`such as SIMD and MIMI). as well as adaptable to ellicient
`on-off chip data communications.
`SUMMARY OF THE INVENTION
`
`These problems have been solved by designing a multi-
`processing system to handle image processing and graphics
`and by constructing a crossbar switch capable of intercon-
`necting any processor with any memory in many configu-
`rations for the interchange of data. The system is capable of
`connecting n parallel processors to m memories where m is
`greater than n. The system. in one embodiment. has four
`processors capable of operating in either the SIMD or
`MIMD modes. Each processor has three buses, two for data
`and one for instructions. The data ports are divided into
`global and local ports. The global port of each processor is
`arranged to access, via a crossbar switch, any one of the
`individual addressable memory spaces. The local port is
`arranged to access, via the same crossbar switch, only a
`subset of the addressable memory spaces, while the instruc-
`tion port is even more limited in that it can access only one
`memory. The limitations imposed on the local and instruc-
`tion ports allow for a minimization of the crossbar buses,
`thereby saving substrate space.
`
`431.353
`
`43135:;
`
`437,353
`
`U.S. Pat. Application ‘["itle
`431591
`Multi-Processor With Crossbar link of
`Processors and Memories and Method of
`Operation
`SIMIJEMIMD Rcconfigttrnble Multi-Processor
`and Method of Operation
`Reconfigurable Comunicatiorts for Multi-
`Proccssor and Method of Operation
`Synehmnimd MIMI) Multi-Processors, System
`and Method of Operation
`Sliced Addressing Mttlti-Processor and Method
`of Operation
`Ones Counting Circuit and Method of
`Operation
`Mentory Circuit Reconfigurable as Data Memory
`or Instruction Cache and Method of Upcmtiort
`Imaging Computer and Method of Operation
`Switch Matrix llavirtg Integrated Crosspoirtt
`ltogic and Method of Operation
`
`43T,946
`-t3'r.s5r
`
`437,351
`
`437,854
`43?,H?S
`
`BACKGROUND OF THE. INVENTION
`
`In the world of computers and processors there is an
`unrelenting drive for additional computing power and faster
`calculation times. In this context, then, systems in which
`several processors can be combined to work in parallel with
`one another are necessary.
`Imaging systems which obtain visual images and perform
`various manipulations with respect to the data and then
`control the display of the imaged and stored data inherently
`require large amounts of computations and memory. Such
`imaging systems are prime candidates for multi-processing
`where different processors perform dilferenl tasks concur- _
`rently in parallel. These processors can be working together
`in the single instruction, multiple data mode (SIMD) where
`all ofthe processors are operating from the same instruction
`stream hut obtaining data from various sources or the
`processors can be working together
`in the multiple
`instruction, multiple data mode (MIMD) where each pro-
`cessor is working from a different set of instructions and
`working on data from dilferent sources. For ditferent
`operations, dilferent configurations are necessary.
`In a mulli-processor system each processor can have
`several buses or ports for the communication of data. Thus,
`assuming two buses for data and one bus for instructions,
`
`0038
`
`

`
`6,(}7(),{}03
`
`3
`The crossbar switch allows the processors to be tied
`together on a cycle by cycle basis for the purposes of
`allowing a common loading of data or instructions from
`memory.
`’lhus, it is a technical advancement that a crossbar switch
`has been arranged to allow several processors to access
`several memories on a random basis and to do so concur-
`rently on a cycle by cycle basis. The processors may still
`communicate with one another and with a common memory
`during any cycle while communicating with separate memo-
`ries during other cycles.
`The problems inherent with constructing a single chip
`image processor having a high degree of versatility have
`been solved by the architecture of establishing a multi—link,
`mu lti-bus crossbar switch between the individual processors
`and the individual memories. This architecture, coupled with
`the design of the high density switch, allows the system to
`perfonn in both the SIMD and MIMI) modes and allows for
`access of all processors to all memories. The crossbar switch
`is constructed with difierenl length links serving dilferent
`functions so as to conserve space while still providing a high
`degree of operational llcxibility.
`In one embodiment a transfer processor operates to con-
`trol ort—chip;’oll'—chip communications while a master pro-
`cessor serves to control
`‘C(l1'I'tITl|.lt‘1lC3IlOt't!i
`to a cornrnort
`memory. In operation, any processor can access any of a
`number of memories, while certain memories are dedicated
`to handling instructions for the individual processors.
`
`BRIEF DESCRIPTION 01’ TIIE DRAWINGS
`
`For a more cotnplcte understanding of the present inven-
`tion and for further advantages thereof, reference is now
`made to the following detailed description taken in cortjttnc-—
`tion with accompanying drawings in which
`FIGS. 1 and 2 show an overall view of the elements of the
`image processing system;
`FIG. 3 shows a series of image processing systems
`interconnected together into an expanded system;
`FIG. 4 shows details ol‘ the t.2t'()SSl".|at‘ switch matrix inlet‘-
`connecting the parallel processors and the memories;
`FIGS. 5 and 6 show prior art configurations;
`FIG. 7 shows an improved configuration;
`FIGS. 8 and 9 show prior art schematic representations of
`processor memory interaction;
`FIG. 10 shows some reconfigurable modes of operations
`of an improved multi-processor;
`FIG. 11 is a graph showing some algorithms and control
`for the image processing system;
`FIGS. 12-15 show image pixel tlow for SIMI) and MIMI)
`operational modes;
`FIG. 16 shows the interrupt polling communication
`between the processors;
`FIG.17 shows a schematic representation of the layout of
`the processors and memory interconnected by the crossbar
`switch;
`FIGS. 18 and 19 show details of the crosspoints of the
`crossbar switch;
`FIG. 20 is a graph of wave [onns of the contention logic
`for memory access;
`FIGS. 21-23 show the synchronization control between
`processors;
`FIGS. 24-27 show details of the sliced addressing tech-
`nique;
`
`_
`
`4
`FIG. 28 shows details of the rearrangement ofthe instruc-
`tion data memory for the SIMDEMIMID operational modes;
`FIG. 29 shows details of a master processor;
`FIGS. 30-34 show details of the parallel processors;
`FIGS. 35-45 show figures useful in understanding meth-
`cds of operation of the parallel processor;
`FIGS. 46-48 show an image processor operating as a
`personal computer;
`I-‘IGS. 49-52 show system arrangements for use of the
`imaging system on a local and remote basis;
`FIG. 53 is a functional block diagram of an imaging
`system;
`FIG. 54 is a logic schematic oi‘ the ones oounting circuit
`matrix;
`
`FIG. 55 is a logic schematic ola minimized matrix ofthe
`ones counting circuit;
`FIG. 56 is an example of an application of a ones counting
`circuit;
`
`FIG. 57 shows a block diagram of the transfer processor;
`FIG. 58 shows a block diagram of the parallel processor
`system used with a VRAM; and
`FIGS. 59-64 show various operational mode relation-
`ships.
`
`l)E'I'AlI.El) [)ESCRIP1'ION OF THE
`INVENTION
`
`Prior to beginning a discussion of the operation of the
`system, it may be helpful to understand how parallel pro-
`cessing systems have operated in the prior art.
`FIG. 5 shows a system having parallel processors 50-53
`accessing a single memory 55. The system shown in FIG. 5
`is typically called a shared memory system where all of the
`parallel processors 50-53 share data in and out I‘ the same
`memory 55.
`FIG. 6 shows another prior art system where memory
`65-68 is distributed with respect to processors 60-63 on a
`one-[or-one basis. In this type of system, the various pro-
`cessors access their respective memory in parallel and thus
`operate without memory contention between the processors.
`The system operating structures shown in FIGS. 5 and 6, as
`will he discussed hereinafter, are suitable for a particular
`type of problem. and each is optimized for that
`type of
`problem. In the past, systems tended to be either shared or
`distributed.
`
`As processing requirements become more complex and
`the speed of operation becomes critical, it is important for
`systems to be able to handle a wide range of operations,
`some of which are best perlonned in the shared memory
`mode, and some of which are best performed in a distributed
`memory mode. The structure shown in FIGS.
`1 and 2
`accomplishes this result by allowing a system to have
`parallel processing working hnth in the shared and in the
`distributed mode. While in these modes, various operational
`arrangements such as SIMD and MIMD can be achieved.
`Multi-Processors and Memory Interconnection
`As shown in FIG. 1, there is a set of parallel processors
`100-103 and a master processor 12 connected to a series of
`memories 10 via a cycle—rate local connection network
`switch matrix 2|] called a crossbar switch. The urns-shar
`switch, as will be shown, is operative on a cycle by cycle
`basis to interconnect the various processors with the various
`memories so that dilferent combinations of distributed and
`shared memory arrangements can be achieved from time to
`time as necessary for the particular operation. Also. as will
`
`0039
`
`

`
`6,070,003
`
`6
`in actuality the parameter memory can be several RAMS per
`processor which makes communication more efficient and
`allows the processors to communicate with the RAMS
`concurrently.
`FIG. 4 shows a more detailed view ot‘FtGS. 1 and 2 where
`the four parallel processors I00-103 are shown intercon-
`nected by communication bus 40 and also shown connected
`to memory 10 via crossbar switch matrix 20. The various
`crosspoints of the crossbar switch will be referred to by their
`coordinate locations starting in a lower left corner with 0-0.
`in the numbering scheme, the vertical number will be used
`first. Thus. the lower left corner cro.s-spoint is known as 0-0,
`and the one immediately to the right
`in the hottorn row
`would be 1-0. FIG. 19 which will be discussed hereinafter,
`shows the details of a particular crosspoint, such as cross-
`point 1-5. Continuing now in FIG. 4, the individual parallel
`processors, such as parallel processor 103, are shown having
`a global data connection (G), a local data connection (1.) and
`an instruction connection (1). Each of these will be detailed
`hereinafter, and each serves a different purpose. For
`example, the global connection allows processor 103 to be
`connected to any of the several
`individual memories of
`memory 10, which can be for data from any of the various
`individual memorie